/* SPDX-License-Identifier: GPL-2.0 */ /* * max98396.h -- MAX98396 ALSA SoC audio driver header * * Copyright(c) 2022, Analog Devices Inc. */ #ifndef _MAX98396_H #define _MAX98396_H #define MAX98396_R2000_SW_RESET … #define MAX98396_R2001_INT_RAW1 … #define MAX98396_R2002_INT_RAW2 … #define MAX98396_R2003_INT_RAW3 … #define MAX98396_R2004_INT_RAW4 … #define MAX98396_R2006_INT_STATE1 … #define MAX98396_R2007_INT_STATE2 … #define MAX98396_R2008_INT_STATE3 … #define MAX98396_R2009_INT_STATE4 … #define MAX98396_R200B_INT_FLAG1 … #define MAX98396_R200C_INT_FLAG2 … #define MAX98396_R200D_INT_FLAG3 … #define MAX98396_R200E_INT_FLAG4 … #define MAX98396_R2010_INT_EN1 … #define MAX98396_R2011_INT_EN2 … #define MAX98396_R2012_INT_EN3 … #define MAX98396_R2013_INT_EN4 … #define MAX98396_R2015_INT_FLAG_CLR1 … #define MAX98396_R2016_INT_FLAG_CLR2 … #define MAX98396_R2017_INT_FLAG_CLR3 … #define MAX98396_R2018_INT_FLAG_CLR4 … #define MAX98396_R201F_IRQ_CTRL … #define MAX98396_R2020_THERM_WARN_THRESH … #define MAX98396_R2021_THERM_WARN_THRESH2 … #define MAX98396_R2022_THERM_SHDN_THRESH … #define MAX98396_R2023_THERM_HYSTERESIS … #define MAX98396_R2024_THERM_FOLDBACK_SET … #define MAX98396_R2027_THERM_FOLDBACK_EN … #define MAX98396_R2030_NOISEGATE_MODE_CTRL … #define MAX98396_R2033_NOISEGATE_MODE_EN … #define MAX98396_R2038_CLK_MON_CTRL … #define MAX98396_R2039_DATA_MON_CTRL … #define MAX98396_R203F_ENABLE_CTRLS … #define MAX98396_R2040_PIN_CFG … #define MAX98396_R2041_PCM_MODE_CFG … #define MAX98396_R2042_PCM_CLK_SETUP … #define MAX98396_R2043_PCM_SR_SETUP … #define MAX98396_R2044_PCM_TX_CTRL_1 … #define MAX98396_R2045_PCM_TX_CTRL_2 … #define MAX98396_R2046_PCM_TX_CTRL_3 … #define MAX98396_R2047_PCM_TX_CTRL_4 … #define MAX98396_R2048_PCM_TX_CTRL_5 … #define MAX98396_R2049_PCM_TX_CTRL_6 … #define MAX98396_R204A_PCM_TX_CTRL_7 … #define MAX98396_R204B_PCM_TX_CTRL_8 … #define MAX98396_R204C_PCM_TX_HIZ_CTRL_1 … #define MAX98396_R204D_PCM_TX_HIZ_CTRL_2 … #define MAX98396_R204E_PCM_TX_HIZ_CTRL_3 … #define MAX98396_R204F_PCM_TX_HIZ_CTRL_4 … #define MAX98396_R2050_PCM_TX_HIZ_CTRL_5 … #define MAX98396_R2051_PCM_TX_HIZ_CTRL_6 … #define MAX98396_R2052_PCM_TX_HIZ_CTRL_7 … #define MAX98396_R2053_PCM_TX_HIZ_CTRL_8 … #define MAX98396_R2055_PCM_RX_SRC1 … #define MAX98396_R2056_PCM_RX_SRC2 … #define MAX98396_R2058_PCM_BYPASS_SRC … #define MAX98396_R205D_PCM_TX_SRC_EN … #define MAX98396_R205E_PCM_RX_EN … #define MAX98396_R205F_PCM_TX_EN … #define MAX98396_R2070_ICC_RX_EN_A … #define MAX98396_R2071_ICC_RX_EN_B … #define MAX98396_R2072_ICC_TX_CTRL … #define MAX98396_R207F_ICC_EN … #define MAX98396_R2083_TONE_GEN_DC_CFG … #define MAX98396_R2084_TONE_GEN_DC_LVL1 … #define MAX98396_R2085_TONE_GEN_DC_LVL2 … #define MAX98396_R2086_TONE_GEN_DC_LVL3 … #define MAX98396_R208F_TONE_GEN_EN … #define MAX98396_R2090_AMP_VOL_CTRL … #define MAX98396_R2091_AMP_PATH_GAIN … #define MAX98396_R2092_AMP_DSP_CFG … #define MAX98396_R2093_SSM_CFG … #define MAX98396_R2094_SPK_CLS_DG_THRESH … #define MAX98396_R2095_SPK_CLS_DG_HDR … #define MAX98396_R2096_SPK_CLS_DG_HOLD_TIME … #define MAX98396_R2097_SPK_CLS_DG_DELAY … #define MAX98396_R2098_SPK_CLS_DG_MODE … #define MAX98396_R2099_SPK_CLS_DG_VBAT_LVL … #define MAX98396_R209A_SPK_EDGE_CTRL … #define MAX98396_R209C_SPK_EDGE_CTRL1 … #define MAX98396_R209D_SPK_EDGE_CTRL2 … #define MAX98396_R209E_AMP_CLIP_GAIN … #define MAX98396_R209F_BYPASS_PATH_CFG … #define MAX98396_R20A0_AMP_SUPPLY_CTL … #define MAX98396_R20AF_AMP_EN … #define MAX98396_R20B0_ADC_SR … #define MAX98396_R20B1_ADC_PVDD_CFG … #define MAX98396_R20B2_ADC_VBAT_CFG … #define MAX98396_R20B3_ADC_THERMAL_CFG … #define MAX98396_R20B4_ADC_READBACK_CTRL1 … #define MAX98396_R20B5_ADC_READBACK_CTRL2 … #define MAX98396_R20B6_ADC_PVDD_READBACK_MSB … #define MAX98396_R20B7_ADC_PVDD_READBACK_LSB … #define MAX98396_R20B8_ADC_VBAT_READBACK_MSB … #define MAX98396_R20B9_ADC_VBAT_READBACK_LSB … #define MAX98396_R20BA_ADC_TEMP_READBACK_MSB … #define MAX98396_R20BB_ADC_TEMP_READBACK_LSB … #define MAX98396_R20BC_ADC_LO_PVDD_READBACK_MSB … #define MAX98396_R20BD_ADC_LO_PVDD_READBACK_LSB … #define MAX98396_R20BE_ADC_LO_VBAT_READBACK_MSB … #define MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB … #define MAX98396_R20C7_ADC_CFG … #define MAX98396_R20D0_DHT_CFG1 … #define MAX98396_R20D1_LIMITER_CFG1 … #define MAX98396_R20D2_LIMITER_CFG2 … #define MAX98396_R20D3_DHT_CFG2 … #define MAX98396_R20D4_DHT_CFG3 … #define MAX98396_R20D5_DHT_CFG4 … #define MAX98396_R20D6_DHT_HYSTERESIS_CFG … #define MAX98396_R20DF_DHT_EN … #define MAX98396_R20E0_IV_SENSE_PATH_CFG … #define MAX98396_R20E4_IV_SENSE_PATH_EN … #define MAX98396_R20E5_BPE_STATE … #define MAX98396_R20E6_BPE_L3_THRESH_MSB … #define MAX98396_R20E7_BPE_L3_THRESH_LSB … #define MAX98396_R20E8_BPE_L2_THRESH_MSB … #define MAX98396_R20E9_BPE_L2_THRESH_LSB … #define MAX98396_R20EA_BPE_L1_THRESH_MSB … #define MAX98396_R20EB_BPE_L1_THRESH_LSB … #define MAX98396_R20EC_BPE_L0_THRESH_MSB … #define MAX98396_R20ED_BPE_L0_THRESH_LSB … #define MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME … #define MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME … #define MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME … #define MAX98396_R20F1_BPE_L0_HOLD_TIME … #define MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP … #define MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP … #define MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP … #define MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP … #define MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN … #define MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN … #define MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN … #define MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN … #define MAX98396_R20FA_BPE_L3_ATT_REL_RATE … #define MAX98396_R20FB_BPE_L2_ATT_REL_RATE … #define MAX98396_R20FC_BPE_L1_ATT_REL_RATE … #define MAX98396_R20FD_BPE_L0_ATT_REL_RATE … #define MAX98396_R20FE_BPE_L3_LIMITER_CFG … #define MAX98396_R20FF_BPE_L2_LIMITER_CFG … #define MAX98396_R2100_BPE_L1_LIMITER_CFG … #define MAX98396_R2101_BPE_L0_LIMITER_CFG … #define MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE … #define MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE … #define MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE … #define MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE … #define MAX98396_R2106_BPE_THRESH_HYSTERESIS … #define MAX98396_R2107_BPE_INFINITE_HOLD_CLR … #define MAX98396_R2108_BPE_SUPPLY_SRC … #define MAX98396_R2109_BPE_LOW_STATE … #define MAX98396_R210A_BPE_LOW_GAIN … #define MAX98396_R210B_BPE_LOW_LIMITER … #define MAX98396_R210D_BPE_EN … #define MAX98396_R210E_AUTO_RESTART … #define MAX98396_R210F_GLOBAL_EN … #define MAX98396_R21FF_REVISION_ID … /* MAX98927 Registers */ #define MAX98397_R203A_SPK_MON_THRESH … #define MAX98397_R204C_PCM_TX_CTRL_9 … #define MAX98397_R204D_PCM_TX_HIZ_CTRL_1 … #define MAX98397_R204E_PCM_TX_HIZ_CTRL_2 … #define MAX98397_R204F_PCM_TX_HIZ_CTRL_3 … #define MAX98397_R2050_PCM_TX_HIZ_CTRL_4 … #define MAX98397_R2051_PCM_TX_HIZ_CTRL_5 … #define MAX98397_R2052_PCM_TX_HIZ_CTRL_6 … #define MAX98397_R2053_PCM_TX_HIZ_CTRL_7 … #define MAX98397_R2054_PCM_TX_HIZ_CTRL_8 … #define MAX98397_R2056_PCM_RX_SRC1 … #define MAX98397_R2057_PCM_RX_SRC2 … #define MAX98397_R2060_PCM_TX_SUPPLY_SEL … #define MAX98397_R209B_SPK_PATH_WB_ONLY … #define MAX98397_R20B4_ADC_VDDH_CFG … #define MAX98397_R20B5_ADC_READBACK_CTRL1 … #define MAX98397_R20B6_ADC_READBACK_CTRL2 … #define MAX98397_R20B7_ADC_PVDD_READBACK_MSB … #define MAX98397_R20B8_ADC_PVDD_READBACK_LSB … #define MAX98397_R20B9_ADC_VBAT_READBACK_MSB … #define MAX98397_R20BA_ADC_VBAT_READBACK_LSB … #define MAX98397_R20BB_ADC_TEMP_READBACK_MSB … #define MAX98397_R20BC_ADC_TEMP_READBACK_LSB … #define MAX98397_R20BD_ADC_VDDH__READBACK_MSB … #define MAX98397_R20BE_ADC_VDDH_READBACK_LSB … #define MAX98397_R20BF_ADC_LO_PVDD_READBACK_MSB … #define MAX98397_R20C0_ADC_LO_PVDD_READBACK_LSB … #define MAX98397_R20C1_ADC_LO_VBAT_READBACK_MSB … #define MAX98397_R20C2_ADC_LO_VBAT_READBACK_LSB … #define MAX98397_R20C3_ADC_LO_VDDH_READBACK_MSB … #define MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB … #define MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE … #define MAX98397_R22FF_REVISION_ID … #define GET_REG_ADDR_REV_ID(x) … /* MAX98396_R2024_THERM_FOLDBACK_SET */ #define MAX98396_THERM_FB_SLOPE1_SHIFT … #define MAX98396_THERM_FB_SLOPE2_SHIFT … #define MAX98396_THERM_FB_REL_SHIFT … #define MAX98396_THERM_FB_HOLD_SHIFT … /* MAX98396_R2038_CLK_MON_CTRL */ #define MAX98396_CLK_MON_AUTO_RESTART_MASK … #define MAX98396_CLK_MON_AUTO_RESTART_SHIFT … /* MAX98396_R2039_DATA_MON_CTRL */ #define MAX98396_DMON_MAG_THRESH_SHIFT … #define MAX98396_DMON_MAG_THRESH_MASK … #define MAX98396_DMON_STUCK_THRESH_SHIFT … #define MAX98396_DMON_STUCK_THRESH_MASK … #define MAX98396_DMON_DURATION_MASK … /* MAX98396_R203F_ENABLE_CTRLS */ #define MAX98396_CTRL_CMON_EN_SHIFT … #define MAX98396_CTRL_DMON_STUCK_EN_MASK … #define MAX98396_CTRL_DMON_MAG_EN_MASK … /* MAX98396_R2041_PCM_MODE_CFG */ #define MAX98396_PCM_MODE_CFG_FORMAT_MASK … #define MAX98396_PCM_TX_CH_INTERLEAVE_MASK … #define MAX98396_PCM_FORMAT_I2S … #define MAX98396_PCM_FORMAT_LJ … #define MAX98396_PCM_FORMAT_TDM_MODE0 … #define MAX98396_PCM_FORMAT_TDM_MODE1 … #define MAX98396_PCM_FORMAT_TDM_MODE2 … #define MAX98396_PCM_MODE_CFG_CHANSZ_MASK … #define MAX98396_PCM_MODE_CFG_CHANSZ_16 … #define MAX98396_PCM_MODE_CFG_CHANSZ_24 … #define MAX98396_PCM_MODE_CFG_CHANSZ_32 … #define MAX98396_PCM_MODE_CFG_LRCLKEDGE … /* MAX98396_R2042_PCM_CLK_SETUP */ #define MAX98396_PCM_MODE_CFG_BCLKEDGE … #define MAX98396_PCM_CLK_SETUP_BSEL_MASK … #define MAX98396_PCM_BCLKEDGE_BSEL_MASK … /* MAX98396_R2043_PCM_SR_SETUP */ #define MAX98396_PCM_SR_SHIFT … #define MAX98396_IVADC_SR_SHIFT … #define MAX98396_PCM_SR_MASK … #define MAX98396_IVADC_SR_MASK … #define MAX98396_PCM_SR_8000 … #define MAX98396_PCM_SR_11025 … #define MAX98396_PCM_SR_12000 … #define MAX98396_PCM_SR_16000 … #define MAX98396_PCM_SR_22050 … #define MAX98396_PCM_SR_24000 … #define MAX98396_PCM_SR_32000 … #define MAX98396_PCM_SR_44100 … #define MAX98396_PCM_SR_48000 … #define MAX98396_PCM_SR_88200 … #define MAX98396_PCM_SR_96000 … #define MAX98396_PCM_SR_176400 … #define MAX98396_PCM_SR_192000 … /* MAX98396_R2055_PCM_RX_SRC1 */ #define MAX98396_PCM_RX_MASK … /* MAX98396_R2056_PCM_RX_SRC2 */ #define MAX98396_PCM_DMIX_CH1_SHIFT … #define MAX98396_PCM_DMIX_CH0_SRC_MASK … #define MAX98396_PCM_DMIX_CH1_SRC_MASK … /* MAX98396_R205E_PCM_RX_EN */ #define MAX98396_PCM_RX_EN_MASK … #define MAX98396_PCM_RX_BYP_EN_MASK … /* MAX98396_R2092_AMP_DSP_CFG */ #define MAX98396_DSP_SPK_DCBLK_EN_SHIFT … #define MAX98396_DSP_SPK_DITH_EN_SHIFT … #define MAX98396_DSP_SPK_INVERT_SHIFT … #define MAX98396_DSP_SPK_VOL_RMPUP_SHIFT … #define MAX98396_DSP_SPK_VOL_RMPDN_SHIFT … #define MAX98396_DSP_SPK_SAFE_EN_SHIFT … #define MAX98396_DSP_SPK_WB_FLT_EN_SHIFT … /* MAX98396_R20A0_AMP_SUPPLY_CTL */ #define MAX98396_AMP_SUPPLY_NOVBAT … /* MAX98396_R20E0_IV_SENSE_PATH_CFG */ #define MAX98396_IV_SENSE_DCBLK_EN_MASK … #define MAX98396_IV_SENSE_DCBLK_EN_SHIFT … #define MAX98396_IV_SENSE_DITH_EN_SHIFT … #define MAX98396_IV_SENSE_WB_FLT_EN_SHIFT … /* MAX98396_R210E_AUTO_RESTART_BEHAVIOR */ #define MAX98396_PVDD_UVLO_RESTART_SHFT … #define MAX98396_VBAT_UVLO_RESTART_SHFT … #define MAX98396_THEM_SHDN_RESTART_SHFT … #define MAX98396_OVC_RESTART_SHFT … enum { … }; #define MAX98396_NUM_CORE_SUPPLIES … struct max98396_priv { … }; #endif
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