linux/sound/soc/codecs/msm8916-wcd-analog.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2016, The Linux Foundation. All rights reserved.

#include <linux/module.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <linux/types.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/jack.h>

#define CDC_D_REVISION1
#define CDC_D_PERPH_SUBTYPE
#define CDC_D_INT_EN_SET
#define CDC_D_INT_EN_CLR
#define MBHC_SWITCH_INT
#define MBHC_MIC_ELECTRICAL_INS_REM_DET
#define MBHC_BUTTON_PRESS_DET
#define MBHC_BUTTON_RELEASE_DET
#define CDC_D_CDC_RST_CTL
#define RST_CTL_DIG_SW_RST_N_MASK
#define RST_CTL_DIG_SW_RST_N_RESET
#define RST_CTL_DIG_SW_RST_N_REMOVE_RESET

#define CDC_D_CDC_TOP_CLK_CTL
#define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK
#define TOP_CLK_CTL_A_MCLK_EN_ENABLE
#define TOP_CLK_CTL_A_MCLK2_EN_ENABLE

#define CDC_D_CDC_ANA_CLK_CTL
#define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK
#define ANA_CLK_CTL_EAR_HPHR_CLK_EN
#define ANA_CLK_CTL_EAR_HPHL_CLK_EN
#define ANA_CLK_CTL_SPKR_CLK_EN_MASK
#define ANA_CLK_CTL_SPKR_CLK_EN
#define ANA_CLK_CTL_TXA_CLK25_EN

#define CDC_D_CDC_DIG_CLK_CTL
#define DIG_CLK_CTL_RXD1_CLK_EN
#define DIG_CLK_CTL_RXD2_CLK_EN
#define DIG_CLK_CTL_RXD3_CLK_EN
#define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK
#define DIG_CLK_CTL_D_MBHC_CLK_EN
#define DIG_CLK_CTL_TXD_CLK_EN
#define DIG_CLK_CTL_NCP_CLK_EN_MASK
#define DIG_CLK_CTL_NCP_CLK_EN
#define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK
#define DIG_CLK_CTL_RXD_PDM_CLK_EN

#define CDC_D_CDC_CONN_TX1_CTL
#define CONN_TX1_SERIAL_TX1_MUX
#define CONN_TX1_SERIAL_TX1_ADC_1
#define CONN_TX1_SERIAL_TX1_RX_PDM_LB
#define CONN_TX1_SERIAL_TX1_ZERO

#define CDC_D_CDC_CONN_TX2_CTL
#define CONN_TX2_SERIAL_TX2_MUX
#define CONN_TX2_SERIAL_TX2_ADC_2
#define CONN_TX2_SERIAL_TX2_RX_PDM_LB
#define CONN_TX2_SERIAL_TX2_ZERO
#define CDC_D_CDC_CONN_HPHR_DAC_CTL
#define CDC_D_CDC_CONN_RX1_CTL
#define CDC_D_CDC_CONN_RX2_CTL
#define CDC_D_CDC_CONN_RX3_CTL
#define CDC_D_CDC_CONN_RX_LB_CTL
#define CDC_D_SEC_ACCESS
#define CDC_D_PERPH_RESET_CTL3
#define CDC_D_PERPH_RESET_CTL4
#define CDC_A_REVISION1
#define CDC_A_REVISION2
#define CDC_A_REVISION3
#define CDC_A_REVISION4
#define CDC_A_PERPH_TYPE
#define CDC_A_PERPH_SUBTYPE
#define CDC_A_INT_RT_STS
#define CDC_A_INT_SET_TYPE
#define CDC_A_INT_POLARITY_HIGH
#define CDC_A_INT_POLARITY_LOW
#define CDC_A_INT_LATCHED_CLR
#define CDC_A_INT_EN_SET
#define CDC_A_INT_EN_CLR
#define CDC_A_INT_LATCHED_STS
#define CDC_A_INT_PENDING_STS
#define CDC_A_INT_MID_SEL
#define CDC_A_INT_PRIORITY
#define CDC_A_MICB_1_EN
#define MICB_1_EN_MICB_ENABLE
#define MICB_1_EN_BYP_CAP_MASK
#define MICB_1_EN_NO_EXT_BYP_CAP
#define MICB_1_EN_EXT_BYP_CAP
#define MICB_1_EN_PULL_DOWN_EN_MASK
#define MICB_1_EN_PULL_DOWN_EN_ENABLE
#define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK
#define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA
#define MICB_1_EN_PULL_UP_EN_MASK
#define MICB_1_EN_TX3_GND_SEL_MASK
#define MICB_1_EN_TX3_GND_SEL_TX_GND

#define CDC_A_MICB_1_VAL
#define MICB_MIN_VAL
#define MICB_STEP_SIZE
#define MICB_VOLTAGE_REGVAL(v)
#define MICB_1_VAL_MICB_OUT_VAL_MASK
#define MICB_1_VAL_MICB_OUT_VAL_V2P70V
#define MICB_1_VAL_MICB_OUT_VAL_V1P80V
#define CDC_A_MICB_1_CTL

#define MICB_1_CTL_CFILT_REF_SEL_MASK
#define MICB_1_CTL_CFILT_REF_SEL_HPF_REF
#define MICB_1_CTL_EXT_PRECHARG_EN_MASK
#define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE
#define MICB_1_CTL_INT_PRECHARG_BYP_MASK
#define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL

#define CDC_A_MICB_1_INT_RBIAS
#define MICB_1_INT_TX1_INT_RBIAS_EN_MASK
#define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE
#define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE

#define MICB_1_INT_TX1_INT_PULLUP_EN_MASK
#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS
#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND

#define MICB_1_INT_TX2_INT_RBIAS_EN_MASK
#define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE
#define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE
#define MICB_1_INT_TX2_INT_PULLUP_EN_MASK
#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS
#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND

#define MICB_1_INT_TX3_INT_RBIAS_EN_MASK
#define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE
#define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE
#define MICB_1_INT_TX3_INT_PULLUP_EN_MASK
#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS
#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND

#define CDC_A_MICB_2_EN
#define CDC_A_MICB_2_EN_ENABLE
#define CDC_A_MICB_2_PULL_DOWN_EN_MASK
#define CDC_A_MICB_2_PULL_DOWN_EN
#define CDC_A_TX_1_2_ATEST_CTL_2
#define CDC_A_MASTER_BIAS_CTL
#define CDC_A_MBHC_DET_CTL_1
#define CDC_A_MBHC_DET_CTL_L_DET_EN
#define CDC_A_MBHC_DET_CTL_GND_DET_EN
#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION
#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL
#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK
#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT
#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO
#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL
#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK
#define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN
#define CDC_A_MBHC_DET_CTL_2
#define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0
#define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD
#define CDC_A_PLUG_TYPE_MASK
#define CDC_A_HPHL_PLUG_TYPE_NO
#define CDC_A_GND_PLUG_TYPE_NO
#define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK
#define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN
#define CDC_A_MBHC_FSM_CTL
#define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN
#define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK
#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA
#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK
#define CDC_A_MBHC_DBNC_TIMER
#define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS
#define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS
#define CDC_A_MBHC_BTN0_ZDET_CTL_0
#define CDC_A_MBHC_BTN1_ZDET_CTL_1
#define CDC_A_MBHC_BTN2_ZDET_CTL_2
#define CDC_A_MBHC_BTN3_CTL
#define CDC_A_MBHC_BTN4_CTL
#define CDC_A_MBHC_BTN_VREF_FINE_SHIFT
#define CDC_A_MBHC_BTN_VREF_FINE_MASK
#define CDC_A_MBHC_BTN_VREF_COARSE_MASK
#define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT
#define CDC_A_MBHC_BTN_VREF_MASK
#define CDC_A_MBHC_RESULT_1
#define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK
#define CDC_A_TX_1_EN
#define CDC_A_TX_2_EN
#define CDC_A_TX_1_2_TEST_CTL_1
#define CDC_A_TX_1_2_TEST_CTL_2
#define CDC_A_TX_1_2_ATEST_CTL
#define CDC_A_TX_1_2_OPAMP_BIAS
#define CDC_A_TX_3_EN
#define CDC_A_NCP_EN
#define CDC_A_NCP_CLK
#define CDC_A_NCP_FBCTRL
#define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK
#define CDC_A_NCP_FBCTRL_FB_CLK_INV
#define CDC_A_NCP_BIAS
#define CDC_A_NCP_VCTRL
#define CDC_A_NCP_TEST
#define CDC_A_NCP_CLIM_ADDR
#define CDC_A_RX_CLOCK_DIVIDER
#define CDC_A_RX_COM_OCP_CTL
#define CDC_A_RX_COM_OCP_COUNT
#define CDC_A_RX_COM_BIAS_DAC
#define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK
#define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE
#define RX_COM_BIAS_DAC_DAC_REF_EN_MASK
#define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE

#define CDC_A_RX_HPH_BIAS_PA
#define CDC_A_RX_HPH_BIAS_LDO_OCP
#define CDC_A_RX_HPH_BIAS_CNP
#define CDC_A_RX_HPH_CNP_EN
#define CDC_A_RX_HPH_L_PA_DAC_CTL
#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK
#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET
#define CDC_A_RX_HPH_R_PA_DAC_CTL
#define RX_HPH_R_PA_DAC_CTL_DATA_RESET
#define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK

#define CDC_A_RX_EAR_CTL
#define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK
#define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE
#define RX_EAR_CTL_PA_EAR_PA_EN_MASK
#define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE
#define RX_EAR_CTL_PA_SEL_MASK
#define RX_EAR_CTL_PA_SEL

#define CDC_A_SPKR_DAC_CTL
#define SPKR_DAC_CTL_DAC_RESET_MASK
#define SPKR_DAC_CTL_DAC_RESET_NORMAL

#define CDC_A_SPKR_DRV_CTL
#define SPKR_DRV_CTL_DEF_MASK
#define SPKR_DRV_CLASSD_PA_EN_MASK
#define SPKR_DRV_CLASSD_PA_EN_ENABLE
#define SPKR_DRV_CAL_EN
#define SPKR_DRV_SETTLE_EN
#define SPKR_DRV_FW_EN
#define SPKR_DRV_BOOST_SET
#define SPKR_DRV_CMFB_SET
#define SPKR_DRV_GAIN_SET
#define SPKR_DRV_CTL_DEF_VAL
#define CDC_A_SPKR_OCP_CTL
#define CDC_A_SPKR_PWRSTG_CTL
#define SPKR_PWRSTG_CTL_DAC_EN_MASK
#define SPKR_PWRSTG_CTL_DAC_EN
#define SPKR_PWRSTG_CTL_MASK
#define SPKR_PWRSTG_CTL_BBM_MASK
#define SPKR_PWRSTG_CTL_BBM_EN
#define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK
#define SPKR_PWRSTG_CTL_HBRDGE_EN
#define SPKR_PWRSTG_CTL_CLAMP_EN_MASK
#define SPKR_PWRSTG_CTL_CLAMP_EN

#define CDC_A_SPKR_DRV_DBG
#define CDC_A_CURRENT_LIMIT
#define CDC_A_BOOST_EN_CTL
#define CDC_A_SLOPE_COMP_IP_ZERO
#define CDC_A_SEC_ACCESS
#define CDC_A_PERPH_RESET_CTL3
#define CDC_A_PERPH_RESET_CTL4

#define MSM8916_WCD_ANALOG_RATES
#define MSM8916_WCD_ANALOG_FORMATS

static int btn_mask =;
static int hs_jack_mask =;

static const char * const supply_names[] =;

#define MBHC_MAX_BUTTONS

struct pm8916_wcd_analog_priv {};

static const char *const adc2_mux_text[] =;
static const char *const rdac2_mux_text[] =;
static const char *const hph_text[] =;

static const struct soc_enum hph_enum =;

static const struct snd_kcontrol_new ear_mux =;
static const struct snd_kcontrol_new hphl_mux =;
static const struct snd_kcontrol_new hphr_mux =;

/* ADC2 MUX */
static const struct soc_enum adc2_enum =;

/* RDAC2 MUX */
static const struct soc_enum rdac2_mux_enum =;

static const struct snd_kcontrol_new spkr_switch[] =;

static const struct snd_kcontrol_new rdac2_mux =;
static const struct snd_kcontrol_new tx_adc2_mux =;

/* Analog Gain control 0 dB to +24 dB in 6 dB steps */
static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);

static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] =;

static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
{}

static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component,
					    int event, unsigned int cap_mode)
{}

static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w,
						struct snd_kcontrol *kcontrol,
						int event)
{}

static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w,
					     struct snd_kcontrol *kcontrol,
					     int event)
{}

static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w,
					     struct snd_kcontrol *kcontrol,
					     int event)
{}

static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
				      bool micbias2_enabled)
{}

static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
{}

static int pm8916_wcd_analog_enable_micbias_int2(struct
						  snd_soc_dapm_widget
						  *w, struct snd_kcontrol
						  *kcontrol, int event)
{}

static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
					 struct snd_kcontrol *kcontrol,
					 int event)
{}

static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
					    struct snd_kcontrol *kcontrol,
					    int event)
{}

static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w,
					    struct snd_kcontrol *kcontrol,
					    int event)
{}

static const struct reg_default wcd_reg_defaults_2_0[] =;

static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
{}

static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
{}

static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] =;

static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] =;

static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
				      struct snd_soc_jack *jack,
				      void *data)
{}

static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
{}

static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
{}

static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
{}

static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] =;

static const struct snd_soc_component_driver pm8916_wcd_analog =;

static int pm8916_wcd_analog_parse_dt(struct device *dev,
				       struct pm8916_wcd_analog_priv *priv)
{}

static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
{}

static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] =;

MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);

static struct platform_driver pm8916_wcd_analog_spmi_driver =;

module_platform_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();