// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2016, The Linux Foundation. All rights reserved. #include <linux/module.h> #include <linux/err.h> #include <linux/kernel.h> #include <linux/delay.h> #include <linux/types.h> #include <linux/clk.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/mfd/syscon.h> #include <sound/soc.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/tlv.h> #define LPASS_CDC_CLK_RX_RESET_CTL … #define LPASS_CDC_CLK_TX_RESET_B1_CTL … #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK … #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK … #define LPASS_CDC_CLK_DMIC_B1_CTL … #define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK … #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2 … #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3 … #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4 … #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6 … #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16 … #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK … #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE … #define LPASS_CDC_CLK_RX_I2S_CTL … #define RX_I2S_CTL_RX_I2S_MODE_MASK … #define RX_I2S_CTL_RX_I2S_MODE_16 … #define RX_I2S_CTL_RX_I2S_MODE_32 … #define RX_I2S_CTL_RX_I2S_FS_RATE_MASK … #define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ … #define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ … #define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ … #define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ … #define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ … #define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ … #define LPASS_CDC_CLK_TX_I2S_CTL … #define TX_I2S_CTL_TX_I2S_MODE_MASK … #define TX_I2S_CTL_TX_I2S_MODE_16 … #define TX_I2S_CTL_TX_I2S_MODE_32 … #define TX_I2S_CTL_TX_I2S_FS_RATE_MASK … #define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ … #define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ … #define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ … #define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ … #define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ … #define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ … #define LPASS_CDC_CLK_OTHR_RESET_B1_CTL … #define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL … #define LPASS_CDC_CLK_OTHR_CTL … #define LPASS_CDC_CLK_RX_B1_CTL … #define LPASS_CDC_CLK_MCLK_CTL … #define MCLK_CTL_MCLK_EN_MASK … #define MCLK_CTL_MCLK_EN_ENABLE … #define MCLK_CTL_MCLK_EN_DISABLE … #define LPASS_CDC_CLK_PDM_CTL … #define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK … #define LPASS_CDC_CLK_PDM_CTL_PDM_EN … #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK … #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB … #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK … #define LPASS_CDC_CLK_SD_CTL … #define LPASS_CDC_RX1_B1_CTL … #define LPASS_CDC_RX2_B1_CTL … #define LPASS_CDC_RX3_B1_CTL … #define LPASS_CDC_RX1_B2_CTL … #define LPASS_CDC_RX2_B2_CTL … #define LPASS_CDC_RX3_B2_CTL … #define LPASS_CDC_RX1_B3_CTL … #define LPASS_CDC_RX2_B3_CTL … #define LPASS_CDC_RX3_B3_CTL … #define LPASS_CDC_RX1_B4_CTL … #define LPASS_CDC_RX2_B4_CTL … #define LPASS_CDC_RX3_B4_CTL … #define LPASS_CDC_RX1_B5_CTL … #define LPASS_CDC_RX2_B5_CTL … #define LPASS_CDC_RX3_B5_CTL … #define LPASS_CDC_RX1_B6_CTL … #define RXn_B6_CTL_MUTE_MASK … #define RXn_B6_CTL_MUTE_ENABLE … #define RXn_B6_CTL_MUTE_DISABLE … #define LPASS_CDC_RX2_B6_CTL … #define LPASS_CDC_RX3_B6_CTL … #define LPASS_CDC_RX1_VOL_CTL_B1_CTL … #define LPASS_CDC_RX2_VOL_CTL_B1_CTL … #define LPASS_CDC_RX3_VOL_CTL_B1_CTL … #define LPASS_CDC_RX1_VOL_CTL_B2_CTL … #define LPASS_CDC_RX2_VOL_CTL_B2_CTL … #define LPASS_CDC_RX3_VOL_CTL_B2_CTL … #define LPASS_CDC_TOP_GAIN_UPDATE … #define LPASS_CDC_TOP_CTL … #define TOP_CTL_DIG_MCLK_FREQ_MASK … #define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ … #define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ … #define LPASS_CDC_DEBUG_DESER1_CTL … #define LPASS_CDC_DEBUG_DESER2_CTL … #define LPASS_CDC_DEBUG_B1_CTL_CFG … #define LPASS_CDC_DEBUG_B2_CTL_CFG … #define LPASS_CDC_DEBUG_B3_CTL_CFG … #define LPASS_CDC_IIR1_GAIN_B1_CTL … #define LPASS_CDC_IIR2_GAIN_B1_CTL … #define LPASS_CDC_IIR1_GAIN_B2_CTL … #define LPASS_CDC_IIR2_GAIN_B2_CTL … #define LPASS_CDC_IIR1_GAIN_B3_CTL … #define LPASS_CDC_IIR2_GAIN_B3_CTL … #define LPASS_CDC_IIR1_GAIN_B4_CTL … #define LPASS_CDC_IIR2_GAIN_B4_CTL … #define LPASS_CDC_IIR1_GAIN_B5_CTL … #define LPASS_CDC_IIR2_GAIN_B5_CTL … #define LPASS_CDC_IIR1_GAIN_B6_CTL … #define LPASS_CDC_IIR2_GAIN_B6_CTL … #define LPASS_CDC_IIR1_GAIN_B7_CTL … #define LPASS_CDC_IIR2_GAIN_B7_CTL … #define LPASS_CDC_IIR1_GAIN_B8_CTL … #define LPASS_CDC_IIR2_GAIN_B8_CTL … #define LPASS_CDC_IIR1_CTL … #define LPASS_CDC_IIR2_CTL … #define LPASS_CDC_IIR1_GAIN_TIMER_CTL … #define LPASS_CDC_IIR2_GAIN_TIMER_CTL … #define LPASS_CDC_IIR1_COEF_B1_CTL … #define LPASS_CDC_IIR2_COEF_B1_CTL … #define LPASS_CDC_IIR1_COEF_B2_CTL … #define LPASS_CDC_IIR2_COEF_B2_CTL … #define LPASS_CDC_CONN_RX1_B1_CTL … #define LPASS_CDC_CONN_RX1_B2_CTL … #define LPASS_CDC_CONN_RX1_B3_CTL … #define LPASS_CDC_CONN_RX2_B1_CTL … #define LPASS_CDC_CONN_RX2_B2_CTL … #define LPASS_CDC_CONN_RX2_B3_CTL … #define LPASS_CDC_CONN_RX3_B1_CTL … #define LPASS_CDC_CONN_RX3_B2_CTL … #define LPASS_CDC_CONN_TX_B1_CTL … #define LPASS_CDC_CONN_EQ1_B1_CTL … #define LPASS_CDC_CONN_EQ1_B2_CTL … #define LPASS_CDC_CONN_EQ1_B3_CTL … #define LPASS_CDC_CONN_EQ1_B4_CTL … #define LPASS_CDC_CONN_EQ2_B1_CTL … #define LPASS_CDC_CONN_EQ2_B2_CTL … #define LPASS_CDC_CONN_EQ2_B3_CTL … #define LPASS_CDC_CONN_EQ2_B4_CTL … #define LPASS_CDC_CONN_TX_I2S_SD1_CTL … #define LPASS_CDC_TX1_VOL_CTL_TIMER … #define LPASS_CDC_TX2_VOL_CTL_TIMER … #define LPASS_CDC_TX1_VOL_CTL_GAIN … #define LPASS_CDC_TX2_VOL_CTL_GAIN … #define LPASS_CDC_TX1_VOL_CTL_CFG … #define TX_VOL_CTL_CFG_MUTE_EN_MASK … #define TX_VOL_CTL_CFG_MUTE_EN_ENABLE … #define LPASS_CDC_TX2_VOL_CTL_CFG … #define LPASS_CDC_TX1_MUX_CTL … #define TX_MUX_CTL_CUT_OFF_FREQ_MASK … #define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT … #define TX_MUX_CTL_CF_NEG_3DB_4HZ … #define TX_MUX_CTL_CF_NEG_3DB_75HZ … #define TX_MUX_CTL_CF_NEG_3DB_150HZ … #define TX_MUX_CTL_HPF_BP_SEL_MASK … #define TX_MUX_CTL_HPF_BP_SEL_BYPASS … #define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS … #define LPASS_CDC_TX2_MUX_CTL … #define LPASS_CDC_TX1_CLK_FS_CTL … #define LPASS_CDC_TX2_CLK_FS_CTL … #define LPASS_CDC_TX1_DMIC_CTL … #define LPASS_CDC_TX2_DMIC_CTL … #define TXN_DMIC_CTL_CLK_SEL_MASK … #define TXN_DMIC_CTL_CLK_SEL_DIV2 … #define TXN_DMIC_CTL_CLK_SEL_DIV3 … #define TXN_DMIC_CTL_CLK_SEL_DIV4 … #define TXN_DMIC_CTL_CLK_SEL_DIV6 … #define TXN_DMIC_CTL_CLK_SEL_DIV16 … #define MSM8916_WCD_DIGITAL_RATES … #define MSM8916_WCD_DIGITAL_FORMATS … /* Codec supports 2 IIR filters */ enum { … }; /* Codec supports 5 bands */ enum { … }; #define WCD_IIR_FILTER_SIZE … #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) … struct wcd_iir_filter_ctl { … }; struct msm8916_wcd_digital_priv { … }; static const unsigned long rx_gain_reg[] = …; static const unsigned long tx_gain_reg[] = …; static const char *const rx_mix1_text[] = …; static const char * const rx_mix2_text[] = …; static const char *const dec_mux_text[] = …; static const char *const cic_mux_text[] = …; /* RX1 MIX1 */ static const struct soc_enum rx_mix1_inp_enum[] = …; /* RX2 MIX1 */ static const struct soc_enum rx2_mix1_inp_enum[] = …; /* RX3 MIX1 */ static const struct soc_enum rx3_mix1_inp_enum[] = …; /* RX1 MIX2 */ static const struct soc_enum rx_mix2_inp1_chain_enum = …; /* RX2 MIX2 */ static const struct soc_enum rx2_mix2_inp1_chain_enum = …; /* DEC */ static const struct soc_enum dec1_mux_enum = …; static const struct soc_enum dec2_mux_enum = …; /* CIC */ static const struct soc_enum cic1_mux_enum = …; static const struct soc_enum cic2_mux_enum = …; /* RDAC2 MUX */ static const struct snd_kcontrol_new dec1_mux = …; static const struct snd_kcontrol_new dec2_mux = …; static const struct snd_kcontrol_new cic1_mux = …; static const struct snd_kcontrol_new cic2_mux = …; static const struct snd_kcontrol_new rx_mix1_inp1_mux = …; static const struct snd_kcontrol_new rx_mix1_inp2_mux = …; static const struct snd_kcontrol_new rx_mix1_inp3_mux = …; static const struct snd_kcontrol_new rx2_mix1_inp1_mux = …; static const struct snd_kcontrol_new rx2_mix1_inp2_mux = …; static const struct snd_kcontrol_new rx2_mix1_inp3_mux = …; static const struct snd_kcontrol_new rx3_mix1_inp1_mux = …; static const struct snd_kcontrol_new rx3_mix1_inp2_mux = …; static const struct snd_kcontrol_new rx3_mix1_inp3_mux = …; static const struct snd_kcontrol_new rx1_mix2_inp1_mux = …; static const struct snd_kcontrol_new rx2_mix2_inp1_mux = …; /* Digital Gain control -84 dB to +40 dB in 1 dB steps */ static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); /* Cutoff Freq for High Pass Filter at -3dB */ static const char * const hpf_cutoff_text[] = …; static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4, hpf_cutoff_text); static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4, hpf_cutoff_text); /* cut off for dc blocker inside rx chain */ static const char * const dc_blocker_cutoff_text[] = …; static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0, dc_blocker_cutoff_text); static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0, dc_blocker_cutoff_text); static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0, dc_blocker_cutoff_text); static int msm8x16_wcd_codec_set_iir_gain(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static uint32_t get_iir_band_coeff(struct snd_soc_component *component, int iir_idx, int band_idx, int coeff_idx) { … } static int msm8x16_wcd_get_iir_band_audio_mixer( struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static void set_iir_band_coeff(struct snd_soc_component *component, int iir_idx, int band_idx, uint32_t value) { … } static int msm8x16_wcd_put_iir_band_audio_mixer( struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wcd_iir_filter_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *ucontrol) { … } static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = …; static int msm8916_wcd_digital_enable_interpolator( struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static const char * const iir_inp1_text[] = …; static const struct soc_enum iir1_inp1_mux_enum = …; static const struct soc_enum iir2_inp1_mux_enum = …; static const struct snd_kcontrol_new iir1_inp1_mux = …; static const struct snd_kcontrol_new iir2_inp1_mux = …; static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = …; static int msm8916_wcd_digital_get_clks(struct platform_device *pdev, struct msm8916_wcd_digital_priv *priv) { … } static int msm8916_wcd_digital_component_probe(struct snd_soc_component *component) { … } static int msm8916_wcd_digital_component_set_sysclk(struct snd_soc_component *component, int clk_id, int source, unsigned int freq, int dir) { … } static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = …; static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = …; static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = …; static const struct snd_soc_component_driver msm8916_wcd_digital = …; static const struct regmap_config msm8916_codec_regmap_config = …; static int msm8916_wcd_digital_probe(struct platform_device *pdev) { … } static void msm8916_wcd_digital_remove(struct platform_device *pdev) { … } static const struct of_device_id msm8916_wcd_digital_match_table[] = …; MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table); static struct platform_driver msm8916_wcd_digital_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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