// SPDX-License-Identifier: GPL-2.0 // // mt6351.c -- mt6351 ALSA SoC audio codec driver // // Copyright (c) 2018 MediaTek Inc. // Author: KaiChieh Chuang <[email protected]> #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/delay.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/soc.h> #include <sound/tlv.h> #include "mt6351.h" /* MT6351_TOP_CLKSQ */ #define RG_CLKSQ_EN_AUD_BIT … /* MT6351_TOP_CKPDN_CON0 */ #define RG_AUDNCP_CK_PDN_BIT … #define RG_AUDIF_CK_PDN_BIT … #define RG_AUD_CK_PDN_BIT … #define RG_ZCD13M_CK_PDN_BIT … /* MT6351_AUDDEC_ANA_CON0 */ #define RG_AUDDACLPWRUP_VAUDP32_BIT … #define RG_AUDDACRPWRUP_VAUDP32_BIT … #define RG_AUD_DAC_PWR_UP_VA32_BIT … #define RG_AUD_DAC_PWL_UP_VA32_BIT … #define RG_AUDHSPWRUP_VAUDP32_BIT … #define RG_AUDHPLPWRUP_VAUDP32_BIT … #define RG_AUDHPRPWRUP_VAUDP32_BIT … #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT … #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK … #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT … #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK … #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT … #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK … #define RG_AUDHSSCDISABLE_VAUDP32 … #define RG_AUDHPLSCDISABLE_VAUDP32_BIT … #define RG_AUDHPRSCDISABLE_VAUDP32_BIT … /* MT6351_AUDDEC_ANA_CON1 */ #define RG_HSOUTPUTSTBENH_VAUDP32_BIT … /* MT6351_AUDDEC_ANA_CON3 */ #define RG_AUDLOLPWRUP_VAUDP32_BIT … #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT … #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK … #define RG_AUDLOLSCDISABLE_VAUDP32_BIT … #define RG_LOOUTPUTSTBENH_VAUDP32_BIT … /* MT6351_AUDDEC_ANA_CON6 */ #define RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT … #define RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT … #define RG_ABIDEC_RSVD0_VAUDP32_HS_BIT … #define RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT … /* MT6351_AUDDEC_ANA_CON9 */ #define RG_AUDIBIASPWRDN_VAUDP32_BIT … #define RG_RSTB_DECODER_VA32_BIT … #define RG_AUDGLB_PWRDN_VA32_BIT … #define RG_LCLDO_DEC_EN_VA32_BIT … #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT … /* MT6351_AUDDEC_ANA_CON10 */ #define RG_NVREG_EN_VAUDP32_BIT … #define RG_AUDGLB_LP2_VOW_EN_VA32 … /* MT6351_AFE_UL_DL_CON0 */ #define RG_AFE_ON_BIT … /* MT6351_AFE_DL_SRC2_CON0_L */ #define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT … /* MT6351_AFE_UL_SRC_CON0_L */ #define UL_SRC_ON_TMP_CTL … /* MT6351_AFE_TOP_CON0 */ #define RG_DL_SINE_ON_SFT … #define RG_DL_SINE_ON_MASK … #define RG_UL_SINE_ON_SFT … #define RG_UL_SINE_ON_MASK … /* MT6351_AUDIO_TOP_CON0 */ #define AUD_TOP_PDN_RESERVED_BIT … #define AUD_TOP_PWR_CLK_DIS_CTL_BIT … #define AUD_TOP_PDN_ADC_CTL_BIT … #define AUD_TOP_PDN_DAC_CTL_BIT … #define AUD_TOP_PDN_AFE_CTL_BIT … /* MT6351_AFE_SGEN_CFG0 */ #define SGEN_C_MUTE_SW_CTL_BIT … #define SGEN_C_DAC_EN_CTL_BIT … /* MT6351_AFE_NCP_CFG0 */ #define RG_NCP_ON_BIT … /* MT6351_LDO_VUSB33_CON0 */ #define RG_VUSB33_EN … #define RG_VUSB33_ON_CTRL … /* MT6351_LDO_VA18_CON0 */ #define RG_VA18_EN … #define RG_VA18_ON_CTRL … /* MT6351_AUDENC_ANA_CON0 */ #define RG_AUDPREAMPLON … #define RG_AUDPREAMPLDCCEN … #define RG_AUDPREAMPLDCPRECHARGE … #define RG_AUDPREAMPLINPUTSEL_SFT … #define RG_AUDPREAMPLINPUTSEL_MASK … #define RG_AUDADCLPWRUP … #define RG_AUDADCLINPUTSEL_SFT … #define RG_AUDADCLINPUTSEL_MASK … /* MT6351_AUDENC_ANA_CON1 */ #define RG_AUDPREAMPRON … #define RG_AUDPREAMPRDCCEN … #define RG_AUDPREAMPRDCPRECHARGE … #define RG_AUDPREAMPRINPUTSEL_SFT … #define RG_AUDPREAMPRINPUTSEL_MASK … #define RG_AUDADCRPWRUP … #define RG_AUDADCRINPUTSEL_SFT … #define RG_AUDADCRINPUTSEL_MASK … /* MT6351_AUDENC_ANA_CON3 */ #define RG_AUDADCCLKRSTB … /* MT6351_AUDENC_ANA_CON9 */ #define RG_AUDPWDBMICBIAS0 … #define RG_AUDMICBIAS0VREF … #define RG_AUDMICBIAS0LOWPEN … #define RG_AUDPWDBMICBIAS2 … #define RG_AUDMICBIAS2VREF … #define RG_AUDMICBIAS2LOWPEN … /* MT6351_AUDENC_ANA_CON10 */ #define RG_AUDPWDBMICBIAS1 … #define RG_AUDMICBIAS1DCSW1NEN … #define RG_AUDMICBIAS1VREF … #define RG_AUDMICBIAS1LOWPEN … enum { … }; /* Supply subseq */ enum { … }; #define REG_STRIDE … struct mt6351_priv { … }; static void set_hp_gain_zero(struct snd_soc_component *cmpnt) { … } static unsigned int get_cap_reg_val(struct snd_soc_component *cmpnt, unsigned int rate) { … } static unsigned int get_play_reg_val(struct snd_soc_component *cmpnt, unsigned int rate) { … } static int mt6351_codec_dai_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops mt6351_codec_dai_ops = …; #define MT6351_FORMATS … static struct snd_soc_dai_driver mt6351_dai_driver[] = …; enum { … }; static void hp_gain_ramp_set(struct snd_soc_component *cmpnt, int hp_gain_ctl) { … } static void hp_zcd_enable(struct snd_soc_component *cmpnt) { … } static void hp_zcd_disable(struct snd_soc_component *cmpnt) { … } static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0); static const struct snd_kcontrol_new mt6351_snd_controls[] = …; /* MUX */ /* LOL MUX */ static const char *const lo_in_mux_map[] = …; static int lo_in_mux_map_value[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum, MT6351_AUDDEC_ANA_CON3, RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT, RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK, lo_in_mux_map, lo_in_mux_map_value); static const struct snd_kcontrol_new lo_in_mux_control = …; /*HP MUX */ static const char *const hp_in_mux_map[] = …; static int hp_in_mux_map_value[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum, MT6351_AUDDEC_ANA_CON0, RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT, RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK, hp_in_mux_map, hp_in_mux_map_value); static const struct snd_kcontrol_new hpl_in_mux_control = …; static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum, MT6351_AUDDEC_ANA_CON0, RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT, RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK, hp_in_mux_map, hp_in_mux_map_value); static const struct snd_kcontrol_new hpr_in_mux_control = …; /* RCV MUX */ static const char *const rcv_in_mux_map[] = …; static int rcv_in_mux_map_value[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, MT6351_AUDDEC_ANA_CON0, RG_AUDHSMUXINPUTSEL_VAUDP32_SFT, RG_AUDHSMUXINPUTSEL_VAUDP32_MASK, rcv_in_mux_map, rcv_in_mux_map_value); static const struct snd_kcontrol_new rcv_in_mux_control = …; /* DAC In MUX */ static const char *const dac_in_mux_map[] = …; static int dac_in_mux_map_value[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, MT6351_AFE_TOP_CON0, RG_DL_SINE_ON_SFT, RG_DL_SINE_ON_MASK, dac_in_mux_map, dac_in_mux_map_value); static const struct snd_kcontrol_new dac_in_mux_control = …; /* AIF Out MUX */ static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, MT6351_AFE_TOP_CON0, RG_UL_SINE_ON_SFT, RG_UL_SINE_ON_MASK, dac_in_mux_map, dac_in_mux_map_value); static const struct snd_kcontrol_new aif_out_mux_control = …; /* ADC L MUX */ static const char *const adc_left_mux_map[] = …; static int adc_left_mux_map_value[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, MT6351_AUDENC_ANA_CON0, RG_AUDADCLINPUTSEL_SFT, RG_AUDADCLINPUTSEL_MASK, adc_left_mux_map, adc_left_mux_map_value); static const struct snd_kcontrol_new adc_left_mux_control = …; /* ADC R MUX */ static const char *const adc_right_mux_map[] = …; static int adc_right_mux_map_value[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, MT6351_AUDENC_ANA_CON1, RG_AUDADCRINPUTSEL_SFT, RG_AUDADCRINPUTSEL_MASK, adc_right_mux_map, adc_right_mux_map_value); static const struct snd_kcontrol_new adc_right_mux_control = …; /* PGA L MUX */ static const char *const pga_left_mux_map[] = …; static int pga_left_mux_map_value[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLINPUTSEL_SFT, RG_AUDPREAMPLINPUTSEL_MASK, pga_left_mux_map, pga_left_mux_map_value); static const struct snd_kcontrol_new pga_left_mux_control = …; /* PGA R MUX */ static const char *const pga_right_mux_map[] = …; static int pga_right_mux_map_value[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRINPUTSEL_SFT, RG_AUDPREAMPRINPUTSEL_MASK, pga_right_mux_map, pga_right_mux_map_value); static const struct snd_kcontrol_new pga_right_mux_control = …; static int mt_reg_set_clr_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_ncp_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_sgen_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_aif_in_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_hp_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_aif_out_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_adc_clkgen_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_pga_left_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_pga_right_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } /* DAPM Widgets */ static const struct snd_soc_dapm_widget mt6351_dapm_widgets[] = …; static const struct snd_soc_dapm_route mt6351_dapm_routes[] = …; static int mt6351_codec_init_reg(struct snd_soc_component *cmpnt) { … } static int mt6351_codec_probe(struct snd_soc_component *cmpnt) { … } static const struct snd_soc_component_driver mt6351_soc_component_driver = …; static int mt6351_codec_driver_probe(struct platform_device *pdev) { … } static const struct of_device_id mt6351_of_match[] = …; static struct platform_driver mt6351_codec_driver = …; module_platform_driver(…) … /* Module information */ MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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