linux/sound/soc/codecs/mt6660.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
 */

#ifndef __SND_SOC_MT6660_H
#define __SND_SOC_MT6660_H

#include <linux/mutex.h>
#include <linux/regmap.h>

#pragma pack(push, 1)
struct mt6660_platform_data { … };

struct mt6660_chip { … };
#pragma pack(pop)

#define MT6660_REG_DEVID …
#define MT6660_REG_SYSTEM_CTRL …
#define MT6660_REG_IRQ_STATUS1 …
#define MT6660_REG_ADDA_CLOCK …
#define MT6660_REG_SERIAL_CFG1 …
#define MT6660_REG_DATAO_SEL …
#define MT6660_REG_TDM_CFG3 …
#define MT6660_REG_HPF_CTRL …
#define MT6660_REG_HPF1_COEF …
#define MT6660_REG_HPF2_COEF …
#define MT6660_REG_PATH_BYPASS …
#define MT6660_REG_WDT_CTRL …
#define MT6660_REG_HCLIP_CTRL …
#define MT6660_REG_VOL_CTRL …
#define MT6660_REG_SPS_CTRL …
#define MT6660_REG_SIGMAX …
#define MT6660_REG_CALI_T0 …
#define MT6660_REG_BST_CTRL …
#define MT6660_REG_PROTECTION_CFG …
#define MT6660_REG_DA_GAIN …
#define MT6660_REG_AUDIO_IN2_SEL …
#define MT6660_REG_SIG_GAIN …
#define MT6660_REG_PLL_CFG1 …
#define MT6660_REG_DRE_CTRL …
#define MT6660_REG_DRE_THDMODE …
#define MT6660_REG_DRE_CORASE …
#define MT6660_REG_PWM_CTRL …
#define MT6660_REG_DC_PROTECT_CTRL …
#define MT6660_REG_ADC_USB_MODE …
#define MT6660_REG_INTERNAL_CFG …
#define MT6660_REG_RESV0 …
#define MT6660_REG_RESV1 …
#define MT6660_REG_RESV2 …
#define MT6660_REG_RESV3 …
#define MT6660_REG_RESV6 …
#define MT6660_REG_RESV7 …
#define MT6660_REG_RESV10 …
#define MT6660_REG_RESV11 …
#define MT6660_REG_RESV16 …
#define MT6660_REG_RESV17 …
#define MT6660_REG_RESV19 …
#define MT6660_REG_RESV21 …
#define MT6660_REG_RESV23 …
#define MT6660_REG_RESV31 …
#define MT6660_REG_RESV40 …

#endif /* __SND_SOC_MT6660_H */