/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt1019.h -- RT1019 ALSA SoC audio amplifier driver * * Copyright(c) 2021 Realtek Semiconductor Corp. */ #ifndef __RT1019_H__ #define __RT1019_H__ #define RT1019_DEVICE_ID_VAL … #define RT1019_DEVICE_ID_VAL2 … #define RT1019_RESET … #define RT1019_IDS_CTRL … #define RT1019_ASEL_CTRL … #define RT1019_PWR_STRP_2 … #define RT1019_BEEP_TONE … #define RT1019_VER_ID … #define RT1019_VEND_ID_1 … #define RT1019_VEND_ID_2 … #define RT1019_DEV_ID_1 … #define RT1019_DEV_ID_2 … #define RT1019_SDB_CTRL … #define RT1019_CLK_TREE_1 … #define RT1019_CLK_TREE_2 … #define RT1019_CLK_TREE_3 … #define RT1019_PLL_1 … #define RT1019_PLL_2 … #define RT1019_PLL_3 … #define RT1019_TDM_1 … #define RT1019_TDM_2 … #define RT1019_TDM_3 … #define RT1019_DMIX_MONO_1 … #define RT1019_DMIX_MONO_2 … #define RT1019_BEEP_1 … #define RT1019_BEEP_2 … /* 0x0019 Power On Strap Control-2 */ #define RT1019_AUTO_BITS_SEL_MASK … #define RT1019_AUTO_BITS_SEL_AUTO … #define RT1019_AUTO_BITS_SEL_MANU … #define RT1019_AUTO_CLK_SEL_MASK … #define RT1019_AUTO_CLK_SEL_AUTO … #define RT1019_AUTO_CLK_SEL_MANU … /* 0x0100 Clock Tree Control-1 */ #define RT1019_CLK_SYS_PRE_SEL_MASK … #define RT1019_CLK_SYS_PRE_SEL_SFT … #define RT1019_CLK_SYS_PRE_SEL_BCLK … #define RT1019_CLK_SYS_PRE_SEL_PLL … #define RT1019_PLL_SRC_MASK … #define RT1019_PLL_SRC_SFT … #define RT1019_PLL_SRC_SEL_BCLK … #define RT1019_PLL_SRC_SEL_RC … #define RT1019_SEL_FIFO_MASK … #define RT1019_SEL_FIFO_DIV1 … #define RT1019_SEL_FIFO_DIV2 … #define RT1019_SEL_FIFO_DIV4 … /* 0x0101 clock tree control-2 */ #define RT1019_SYS_DIV_DA_FIL_MASK … #define RT1019_SYS_DIV_DA_FIL_DIV1 … #define RT1019_SYS_DIV_DA_FIL_DIV2 … #define RT1019_SYS_DIV_DA_FIL_DIV4 … #define RT1019_SYS_DA_OSR_MASK … #define RT1019_SYS_DA_OSR_DIV1 … #define RT1019_SYS_DA_OSR_DIV2 … #define RT1019_SYS_DA_OSR_DIV4 … #define RT1019_ASRC_256FS_MASK … #define RT1019_ASRC_256FS_DIV1 … #define RT1019_ASRC_256FS_DIV2 … #define RT1019_ASRC_256FS_DIV4 … /* 0x0102 clock tree control-3 */ #define RT1019_SEL_CLK_CAL_MASK … #define RT1019_SEL_CLK_CAL_DIV1 … #define RT1019_SEL_CLK_CAL_DIV2 … #define RT1019_SEL_CLK_CAL_DIV4 … /* 0x0311 PLL-1 */ #define RT1019_PLL_M_MASK … #define RT1019_PLL_M_SFT … #define RT1019_PLL_M_BP_MASK … #define RT1019_PLL_M_BP_SFT … #define RT1019_PLL_Q_8_8_MASK … /* 0x0312 PLL-2 */ #define RT1019_PLL_Q_7_0_MASK … /* 0x0313 PLL-3 */ #define RT1019_PLL_K_MASK … /* 0x0400 TDM Control-1 */ #define RT1019_TDM_BCLK_MASK … #define RT1019_TDM_BCLK_NORM … #define RT1019_TDM_BCLK_INV … #define RT1019_TDM_CL_MASK … #define RT1019_TDM_CL_8 … #define RT1019_TDM_CL_32 … #define RT1019_TDM_CL_24 … #define RT1019_TDM_CL_20 … #define RT1019_TDM_CL_16 … /* 0x0401 TDM Control-2 */ #define RT1019_I2S_CH_TX_MASK … #define RT1019_I2S_CH_TX_SFT … #define RT1019_I2S_TX_2CH … #define RT1019_I2S_TX_4CH … #define RT1019_I2S_TX_6CH … #define RT1019_I2S_TX_8CH … #define RT1019_I2S_DF_MASK … #define RT1019_I2S_DF_SFT … #define RT1019_I2S_DF_I2S … #define RT1019_I2S_DF_LEFT … #define RT1019_I2S_DF_PCM_A_R … #define RT1019_I2S_DF_PCM_B_R … #define RT1019_I2S_DF_PCM_A_F … #define RT1019_I2S_DF_PCM_B_F … #define RT1019_I2S_DL_MASK … #define RT1019_I2S_DL_SFT … #define RT1019_I2S_DL_16 … #define RT1019_I2S_DL_20 … #define RT1019_I2S_DL_24 … #define RT1019_I2S_DL_32 … #define RT1019_I2S_DL_8 … /* TDM1 Control-3 (0x0402) */ #define RT1019_TDM_I2S_TX_L_DAC1_1_MASK … #define RT1019_TDM_I2S_TX_R_DAC1_1_MASK … #define RT1019_TDM_I2S_TX_L_DAC1_1_SFT … #define RT1019_TDM_I2S_TX_R_DAC1_1_SFT … /* System Clock Source */ enum { … }; /* PLL1 Source */ enum { … }; enum { … }; struct rt1019_priv { … }; #endif /* __RT1019_H__ */
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