/* SPDX-License-Identifier: GPL-2.0-only */ /* * RT1305.h -- RT1305 ALSA SoC amplifier component driver * * Copyright 2018 Realtek Semiconductor Corp. * Author: Shuming Fan <[email protected]> */ #ifndef _RT1305_H_ #define _RT1305_H_ #define RT1305_DEVICE_ID_NUM … #define RT1305_RESET … #define RT1305_CLK_1 … #define RT1305_CLK_2 … #define RT1305_CLK_3 … #define RT1305_DFLL_REG … #define RT1305_CAL_EFUSE_CLOCK … #define RT1305_PLL0_1 … #define RT1305_PLL0_2 … #define RT1305_PLL1_1 … #define RT1305_PLL1_2 … #define RT1305_MIXER_CTRL_1 … #define RT1305_MIXER_CTRL_2 … #define RT1305_DAC_SET_1 … #define RT1305_DAC_SET_2 … #define RT1305_ADC_SET_1 … #define RT1305_ADC_SET_2 … #define RT1305_ADC_SET_3 … #define RT1305_PATH_SET … #define RT1305_SPDIF_IN_SET_1 … #define RT1305_SPDIF_IN_SET_2 … #define RT1305_SPDIF_IN_SET_3 … #define RT1305_SPDIF_OUT_SET_1 … #define RT1305_SPDIF_OUT_SET_2 … #define RT1305_SPDIF_OUT_SET_3 … #define RT1305_I2S_SET_1 … #define RT1305_I2S_SET_2 … #define RT1305_PBTL_MONO_MODE_SRC … #define RT1305_MANUALLY_I2C_DEVICE … #define RT1305_POWER_STATUS … #define RT1305_POWER_CTRL_1 … #define RT1305_POWER_CTRL_2 … #define RT1305_POWER_CTRL_3 … #define RT1305_POWER_CTRL_4 … #define RT1305_POWER_CTRL_5 … #define RT1305_CLOCK_DETECT … #define RT1305_BIQUAD_SET_1 … #define RT1305_BIQUAD_SET_2 … #define RT1305_ADJUSTED_HPF_1 … #define RT1305_ADJUSTED_HPF_2 … #define RT1305_EQ_SET_1 … #define RT1305_EQ_SET_2 … #define RT1305_SPK_TEMP_PROTECTION_0 … #define RT1305_SPK_TEMP_PROTECTION_1 … #define RT1305_SPK_TEMP_PROTECTION_2 … #define RT1305_SPK_TEMP_PROTECTION_3 … #define RT1305_SPK_DC_DETECT_1 … #define RT1305_SPK_DC_DETECT_2 … #define RT1305_LOUDNESS … #define RT1305_THERMAL_FOLD_BACK_1 … #define RT1305_THERMAL_FOLD_BACK_2 … #define RT1305_SILENCE_DETECT … #define RT1305_ALC_DRC_1 … #define RT1305_ALC_DRC_2 … #define RT1305_ALC_DRC_3 … #define RT1305_ALC_DRC_4 … #define RT1305_PRIV_INDEX … #define RT1305_PRIV_DATA … #define RT1305_SPK_EXCURSION_LIMITER_7 … #define RT1305_VERSION_ID … #define RT1305_VENDOR_ID … #define RT1305_DEVICE_ID … #define RT1305_EFUSE_1 … #define RT1305_EFUSE_2 … #define RT1305_EFUSE_3 … #define RT1305_DC_CALIB_1 … #define RT1305_DC_CALIB_2 … #define RT1305_DC_CALIB_3 … #define RT1305_DAC_OFFSET_1 … #define RT1305_DAC_OFFSET_2 … #define RT1305_DAC_OFFSET_3 … #define RT1305_DAC_OFFSET_4 … #define RT1305_DAC_OFFSET_5 … #define RT1305_DAC_OFFSET_6 … #define RT1305_DAC_OFFSET_7 … #define RT1305_DAC_OFFSET_8 … #define RT1305_DAC_OFFSET_9 … #define RT1305_DAC_OFFSET_10 … #define RT1305_DAC_OFFSET_11 … #define RT1305_DAC_OFFSET_12 … #define RT1305_DAC_OFFSET_13 … #define RT1305_DAC_OFFSET_14 … #define RT1305_TRIM_1 … #define RT1305_TRIM_2 … #define RT1305_TUNE_INTERNAL_OSC … #define RT1305_BIQUAD1_H0_L_28_16 … #define RT1305_BIQUAD3_A2_R_15_0 … #define RT1305_MAX_REG … /* CLOCK-1 (0x04) */ #define RT1305_SEL_PLL_SRC_2_MASK … #define RT1305_SEL_PLL_SRC_2_SFT … #define RT1305_SEL_PLL_SRC_2_MCLK … #define RT1305_SEL_PLL_SRC_2_RCCLK … #define RT1305_DIV_PLL_SRC_2_MASK … #define RT1305_DIV_PLL_SRC_2_SFT … #define RT1305_SEL_PLL_SRC_1_MASK … #define RT1305_SEL_PLL_SRC_1_SFT … #define RT1305_SEL_PLL_SRC_1_PLL2 … #define RT1305_SEL_PLL_SRC_1_BCLK … #define RT1305_SEL_PLL_SRC_1_DFLL … #define RT1305_SEL_FS_SYS_PRE_MASK … #define RT1305_SEL_FS_SYS_PRE_SFT … #define RT1305_SEL_FS_SYS_PRE_MCLK … #define RT1305_SEL_FS_SYS_PRE_PLL … #define RT1305_SEL_FS_SYS_PRE_RCCLK … #define RT1305_DIV_FS_SYS_MASK … #define RT1305_DIV_FS_SYS_SFT … /* PLL1M/N/K Code-1 (0x0c) */ #define RT1305_PLL_1_M_SFT … #define RT1305_PLL_1_M_BYPASS_MASK … #define RT1305_PLL_1_M_BYPASS_SFT … #define RT1305_PLL_1_M_BYPASS … #define RT1305_PLL_1_N_MASK … /* DAC Setting (0x14) */ #define RT1305_DVOL_MUTE_L_EN_SFT … #define RT1305_DVOL_MUTE_R_EN_SFT … /* I2S Setting-1 (0x2d) */ #define RT1305_SEL_I2S_OUT_MODE_MASK … #define RT1305_SEL_I2S_OUT_MODE_SFT … #define RT1305_SEL_I2S_OUT_MODE_S … #define RT1305_SEL_I2S_OUT_MODE_M … /* I2S Setting-2 (0x2e) */ #define RT1305_I2S_DF_SEL_MASK … #define RT1305_I2S_DF_SEL_SFT … #define RT1305_I2S_DF_SEL_I2S … #define RT1305_I2S_DF_SEL_LEFT … #define RT1305_I2S_DF_SEL_PCM_A … #define RT1305_I2S_DF_SEL_PCM_B … #define RT1305_I2S_DL_SEL_MASK … #define RT1305_I2S_DL_SEL_SFT … #define RT1305_I2S_DL_SEL_16B … #define RT1305_I2S_DL_SEL_20B … #define RT1305_I2S_DL_SEL_24B … #define RT1305_I2S_DL_SEL_8B … #define RT1305_I2S_BCLK_MASK … #define RT1305_I2S_BCLK_SFT … #define RT1305_I2S_BCLK_NORMAL … #define RT1305_I2S_BCLK_INV … /* Power Control-1 (0x3a) */ #define RT1305_POW_PDB_JD_MASK … #define RT1305_POW_PDB_JD … #define RT1305_POW_PDB_JD_BIT … #define RT1305_POW_PLL0_EN … #define RT1305_POW_PLL0_EN_BIT … #define RT1305_POW_PLL1_EN … #define RT1305_POW_PLL1_EN_BIT … #define RT1305_POW_PDB_JD_POLARITY … #define RT1305_POW_PDB_JD_POLARITY_BIT … #define RT1305_POW_MBIAS_LV … #define RT1305_POW_MBIAS_LV_BIT … #define RT1305_POW_BG_MBIAS_LV … #define RT1305_POW_BG_MBIAS_LV_BIT … #define RT1305_POW_LDO2 … #define RT1305_POW_LDO2_BIT … #define RT1305_POW_BG2 … #define RT1305_POW_BG2_BIT … #define RT1305_POW_LDO2_IB2 … #define RT1305_POW_LDO2_IB2_BIT … #define RT1305_POW_VREF … #define RT1305_POW_VREF_BIT … #define RT1305_POW_VREF1 … #define RT1305_POW_VREF1_BIT … #define RT1305_POW_VREF2 … #define RT1305_POW_VREF2_BIT … /* Power Control-2 (0x3b) */ #define RT1305_POW_DISC_VREF … #define RT1305_POW_DISC_VREF_BIT … #define RT1305_POW_FASTB_VREF … #define RT1305_POW_FASTB_VREF_BIT … #define RT1305_POW_ULTRA_FAST_VREF … #define RT1305_POW_ULTRA_FAST_VREF_BIT … #define RT1305_POW_CKXEN_DAC … #define RT1305_POW_CKXEN_DAC_BIT … #define RT1305_POW_EN_CKGEN_DAC … #define RT1305_POW_EN_CKGEN_DAC_BIT … #define RT1305_POW_DAC1_L … #define RT1305_POW_DAC1_L_BIT … #define RT1305_POW_DAC1_R … #define RT1305_POW_DAC1_R_BIT … #define RT1305_POW_CLAMP … #define RT1305_POW_CLAMP_BIT … #define RT1305_POW_BUFL … #define RT1305_POW_BUFL_BIT … #define RT1305_POW_BUFR … #define RT1305_POW_BUFR_BIT … #define RT1305_POW_EN_CKGEN_ADC … #define RT1305_POW_EN_CKGEN_ADC_BIT … #define RT1305_POW_ADC3_L … #define RT1305_POW_ADC3_L_BIT … #define RT1305_POW_ADC3_R … #define RT1305_POW_ADC3_R_BIT … #define RT1305_POW_TRIOSC … #define RT1305_POW_TRIOSC_BIT … #define RT1305_POR_AVDD1 … #define RT1305_POR_AVDD1_BIT … #define RT1305_POR_AVDD2 … #define RT1305_POR_AVDD2_BIT … /* Power Control-3 (0x3c) */ #define RT1305_POW_VSENSE_RCH … #define RT1305_POW_VSENSE_RCH_BIT … #define RT1305_POW_VSENSE_LCH … #define RT1305_POW_VSENSE_LCH_BIT … #define RT1305_POW_ISENSE_RCH … #define RT1305_POW_ISENSE_RCH_BIT … #define RT1305_POW_ISENSE_LCH … #define RT1305_POW_ISENSE_LCH_BIT … #define RT1305_POW_POR_AVDD1 … #define RT1305_POW_POR_AVDD1_BIT … #define RT1305_POW_POR_AVDD2 … #define RT1305_POW_POR_AVDD2_BIT … #define RT1305_EN_K_HV … #define RT1305_EN_K_HV_BIT … #define RT1305_EN_PRE_K_HV … #define RT1305_EN_PRE_K_HV_BIT … #define RT1305_EN_EFUSE_1P8V … #define RT1305_EN_EFUSE_1P8V_BIT … #define RT1305_EN_EFUSE_5V … #define RT1305_EN_EFUSE_5V_BIT … #define RT1305_EN_VCM_6172 … #define RT1305_EN_VCM_6172_BIT … #define RT1305_POR_EFUSE … #define RT1305_POR_EFUSE_BIT … /* Clock Detect (0x3f) */ #define RT1305_SEL_CLK_DET_SRC_MASK … #define RT1305_SEL_CLK_DET_SRC_SFT … #define RT1305_SEL_CLK_DET_SRC_MCLK … #define RT1305_SEL_CLK_DET_SRC_BCLK … /* System Clock Source */ enum { … }; /* PLL Source 1/2 */ enum { … }; enum { … }; #define R0_UPPER … #define R0_LOWER … #endif /* end of _RT1305_H_ */
Codebase Browser
linux