/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt5645.h -- RT5645 ALSA SoC audio driver * * Copyright 2013 Realtek Microelectronics * Author: Bard Liao <[email protected]> */ #ifndef __RT5645_H__ #define __RT5645_H__ /* Info */ #define RT5645_RESET … #define RT5645_VENDOR_ID … #define RT5645_VENDOR_ID1 … #define RT5645_VENDOR_ID2 … /* I/O - Output */ #define RT5645_SPK_VOL … #define RT5645_HP_VOL … #define RT5645_LOUT1 … #define RT5645_LOUT_CTRL … /* I/O - Input */ #define RT5645_IN1_CTRL1 … #define RT5645_IN1_CTRL2 … #define RT5645_IN1_CTRL3 … #define RT5645_IN2_CTRL … #define RT5645_INL1_INR1_VOL … #define RT5645_SPK_FUNC_LIM … #define RT5645_ADJ_HPF_CTRL … /* I/O - ADC/DAC/DMIC */ #define RT5645_DAC1_DIG_VOL … #define RT5645_DAC2_DIG_VOL … #define RT5645_DAC_CTRL … #define RT5645_STO1_ADC_DIG_VOL … #define RT5645_MONO_ADC_DIG_VOL … #define RT5645_ADC_BST_VOL1 … #define RT5645_ADC_BST_VOL2 … /* Mixer - D-D */ #define RT5645_STO1_ADC_MIXER … #define RT5645_MONO_ADC_MIXER … #define RT5645_AD_DA_MIXER … #define RT5645_STO_DAC_MIXER … #define RT5645_MONO_DAC_MIXER … #define RT5645_DIG_MIXER … #define RT5650_A_DAC_SOUR … #define RT5645_DIG_INF1_DATA … /* Mixer - PDM */ #define RT5645_PDM_OUT_CTRL … /* Mixer - ADC */ #define RT5645_REC_L1_MIXER … #define RT5645_REC_L2_MIXER … #define RT5645_REC_R1_MIXER … #define RT5645_REC_R2_MIXER … /* Mixer - DAC */ #define RT5645_HPMIXL_CTRL … #define RT5645_HPOMIXL_CTRL … #define RT5645_HPMIXR_CTRL … #define RT5645_HPOMIXR_CTRL … #define RT5645_HPO_MIXER … #define RT5645_SPK_L_MIXER … #define RT5645_SPK_R_MIXER … #define RT5645_SPO_MIXER … #define RT5645_SPO_CLSD_RATIO … #define RT5645_OUT_L_GAIN1 … #define RT5645_OUT_L_GAIN2 … #define RT5645_OUT_L1_MIXER … #define RT5645_OUT_R_GAIN1 … #define RT5645_OUT_R_GAIN2 … #define RT5645_OUT_R1_MIXER … #define RT5645_LOUT_MIXER … /* Haptic */ #define RT5645_HAPTIC_CTRL1 … #define RT5645_HAPTIC_CTRL2 … #define RT5645_HAPTIC_CTRL3 … #define RT5645_HAPTIC_CTRL4 … #define RT5645_HAPTIC_CTRL5 … #define RT5645_HAPTIC_CTRL6 … #define RT5645_HAPTIC_CTRL7 … #define RT5645_HAPTIC_CTRL8 … #define RT5645_HAPTIC_CTRL9 … #define RT5645_HAPTIC_CTRL10 … /* Power */ #define RT5645_PWR_DIG1 … #define RT5645_PWR_DIG2 … #define RT5645_PWR_ANLG1 … #define RT5645_PWR_ANLG2 … #define RT5645_PWR_MIXER … #define RT5645_PWR_VOL … /* Private Register Control */ #define RT5645_PRIV_INDEX … #define RT5645_PRIV_DATA … /* Format - ADC/DAC */ #define RT5645_I2S1_SDP … #define RT5645_I2S2_SDP … #define RT5645_ADDA_CLK1 … #define RT5645_ADDA_CLK2 … #define RT5645_DMIC_CTRL1 … #define RT5645_DMIC_CTRL2 … /* Format - TDM Control */ #define RT5645_TDM_CTRL_1 … #define RT5645_TDM_CTRL_2 … #define RT5645_TDM_CTRL_3 … #define RT5650_TDM_CTRL_4 … /* Function - Analog */ #define RT5645_GLB_CLK … #define RT5645_PLL_CTRL1 … #define RT5645_PLL_CTRL2 … #define RT5645_ASRC_1 … #define RT5645_ASRC_2 … #define RT5645_ASRC_3 … #define RT5645_ASRC_4 … #define RT5645_DEPOP_M1 … #define RT5645_DEPOP_M2 … #define RT5645_DEPOP_M3 … #define RT5645_CHARGE_PUMP … #define RT5645_MICBIAS … #define RT5645_A_JD_CTRL1 … #define RT5645_VAD_CTRL4 … #define RT5645_CLSD_OUT_CTRL … /* Function - Digital */ #define RT5645_ADC_EQ_CTRL1 … #define RT5645_ADC_EQ_CTRL2 … #define RT5645_EQ_CTRL1 … #define RT5645_EQ_CTRL2 … #define RT5645_ALC_CTRL_1 … #define RT5645_ALC_CTRL_2 … #define RT5645_ALC_CTRL_3 … #define RT5645_ALC_CTRL_4 … #define RT5645_ALC_CTRL_5 … #define RT5645_JD_CTRL … #define RT5645_IRQ_CTRL1 … #define RT5645_IRQ_CTRL2 … #define RT5645_IRQ_CTRL3 … #define RT5645_INT_IRQ_ST … #define RT5645_GPIO_CTRL1 … #define RT5645_GPIO_CTRL2 … #define RT5645_GPIO_CTRL3 … #define RT5645_BASS_BACK … #define RT5645_MP3_PLUS1 … #define RT5645_MP3_PLUS2 … #define RT5645_ADJ_HPF1 … #define RT5645_ADJ_HPF2 … #define RT5645_HP_CALIB_AMP_DET … #define RT5645_SV_ZCD1 … #define RT5645_SV_ZCD2 … #define RT5645_IL_CMD … #define RT5645_IL_CMD2 … #define RT5645_IL_CMD3 … #define RT5650_4BTN_IL_CMD1 … #define RT5650_4BTN_IL_CMD2 … #define RT5645_DRC1_HL_CTRL1 … #define RT5645_DRC2_HL_CTRL1 … #define RT5645_MUTI_DRC_CTRL1 … #define RT5645_ADC_MONO_HP_CTRL1 … #define RT5645_ADC_MONO_HP_CTRL2 … #define RT5645_DRC2_CTRL1 … #define RT5645_DRC2_CTRL2 … #define RT5645_DRC2_CTRL3 … #define RT5645_DRC2_CTRL4 … #define RT5645_DRC2_CTRL5 … #define RT5645_JD_CTRL3 … #define RT5645_JD_CTRL4 … /* General Control */ #define RT5645_GEN_CTRL1 … #define RT5645_GEN_CTRL2 … #define RT5645_GEN_CTRL3 … /* Index of Codec Private Register definition */ #define RT5645_DIG_VOL … #define RT5645_PR_ALC_CTRL_1 … #define RT5645_PR_ALC_CTRL_2 … #define RT5645_PR_ALC_CTRL_3 … #define RT5645_PR_ALC_CTRL_4 … #define RT5645_PR_ALC_CTRL_5 … #define RT5645_PR_ALC_CTRL_6 … #define RT5645_BIAS_CUR1 … #define RT5645_BIAS_CUR3 … #define RT5645_CLSD_INT_REG1 … #define RT5645_MAMP_INT_REG2 … #define RT5645_CHOP_DAC_ADC … #define RT5645_MIXER_INT_REG … #define RT5645_3D_SPK … #define RT5645_WND_1 … #define RT5645_WND_2 … #define RT5645_WND_3 … #define RT5645_WND_4 … #define RT5645_WND_5 … #define RT5645_WND_8 … #define RT5645_DIP_SPK_INF … #define RT5645_HP_DCC_INT1 … #define RT5645_EQ_BW_LOP … #define RT5645_EQ_GN_LOP … #define RT5645_EQ_FC_BP1 … #define RT5645_EQ_BW_BP1 … #define RT5645_EQ_GN_BP1 … #define RT5645_EQ_FC_BP2 … #define RT5645_EQ_BW_BP2 … #define RT5645_EQ_GN_BP2 … #define RT5645_EQ_FC_BP3 … #define RT5645_EQ_BW_BP3 … #define RT5645_EQ_GN_BP3 … #define RT5645_EQ_FC_BP4 … #define RT5645_EQ_BW_BP4 … #define RT5645_EQ_GN_BP4 … #define RT5645_EQ_FC_HIP1 … #define RT5645_EQ_GN_HIP1 … #define RT5645_EQ_FC_HIP2 … #define RT5645_EQ_BW_HIP2 … #define RT5645_EQ_GN_HIP2 … #define RT5645_EQ_PRE_VOL … #define RT5645_EQ_PST_VOL … /* global definition */ #define RT5645_L_MUTE … #define RT5645_L_MUTE_SFT … #define RT5645_VOL_L_MUTE … #define RT5645_VOL_L_SFT … #define RT5645_R_MUTE … #define RT5645_R_MUTE_SFT … #define RT5645_VOL_R_MUTE … #define RT5645_VOL_R_SFT … #define RT5645_L_VOL_MASK … #define RT5645_L_VOL_SFT … #define RT5645_R_VOL_MASK … #define RT5645_R_VOL_SFT … /* IN1 Control 1 (0x0a) */ #define RT5645_CBJ_BST1_MASK … #define RT5645_CBJ_BST1_SFT … #define RT5645_CBJ_JD_HP_EN … #define RT5645_CBJ_JD_MIC_EN … #define RT5645_CBJ_JD_MIC_SW_EN … #define RT5645_CBJ_MIC_SEL_R … #define RT5645_CBJ_MIC_SEL_L … #define RT5645_CBJ_MIC_SW … #define RT5645_CBJ_BST1_EN … /* IN1 Control 2 (0x0b) */ #define RT5645_CBJ_MN_JD … #define RT5645_CAPLESS_EN … #define RT5645_CBJ_DET_MODE … /* IN1 Control 3 (0x0c) */ #define RT5645_CBJ_TIE_G_L … #define RT5645_CBJ_TIE_G_R … /* IN2 Control (0x0d) */ #define RT5645_BST_MASK1 … #define RT5645_BST_SFT1 … #define RT5645_BST_MASK2 … #define RT5645_BST_SFT2 … #define RT5645_IN_DF2 … #define RT5645_IN_SFT2 … /* INL and INR Volume Control (0x0f) */ #define RT5645_INL_SEL_MASK … #define RT5645_INL_SEL_SFT … #define RT5645_INL_SEL_IN4P … #define RT5645_INL_SEL_MONOP … #define RT5645_INL_VOL_MASK … #define RT5645_INL_VOL_SFT … #define RT5645_INR_SEL_MASK … #define RT5645_INR_SEL_SFT … #define RT5645_INR_SEL_IN4N … #define RT5645_INR_SEL_MONON … #define RT5645_INR_VOL_MASK … #define RT5645_INR_VOL_SFT … /* DAC1 Digital Volume (0x19) */ #define RT5645_DAC_L1_VOL_MASK … #define RT5645_DAC_L1_VOL_SFT … #define RT5645_DAC_R1_VOL_MASK … #define RT5645_DAC_R1_VOL_SFT … /* DAC2 Digital Volume (0x1a) */ #define RT5645_DAC_L2_VOL_MASK … #define RT5645_DAC_L2_VOL_SFT … #define RT5645_DAC_R2_VOL_MASK … #define RT5645_DAC_R2_VOL_SFT … /* DAC2 Control (0x1b) */ #define RT5645_M_DAC_L2_VOL … #define RT5645_M_DAC_L2_VOL_SFT … #define RT5645_M_DAC_R2_VOL … #define RT5645_M_DAC_R2_VOL_SFT … #define RT5645_DAC2_L_SEL_MASK … #define RT5645_DAC2_L_SEL_SFT … #define RT5645_DAC2_R_SEL_MASK … #define RT5645_DAC2_R_SEL_SFT … /* ADC Digital Volume Control (0x1c) */ #define RT5645_ADC_L_VOL_MASK … #define RT5645_ADC_L_VOL_SFT … #define RT5645_ADC_R_VOL_MASK … #define RT5645_ADC_R_VOL_SFT … /* Mono ADC Digital Volume Control (0x1d) */ #define RT5645_MONO_ADC_L_VOL_MASK … #define RT5645_MONO_ADC_L_VOL_SFT … #define RT5645_MONO_ADC_R_VOL_MASK … #define RT5645_MONO_ADC_R_VOL_SFT … /* ADC Boost Volume Control (0x1e) */ #define RT5645_STO1_ADC_L_BST_MASK … #define RT5645_STO1_ADC_L_BST_SFT … #define RT5645_STO1_ADC_R_BST_MASK … #define RT5645_STO1_ADC_R_BST_SFT … #define RT5645_STO1_ADC_COMP_MASK … #define RT5645_STO1_ADC_COMP_SFT … /* ADC Boost Volume Control (0x20) */ #define RT5645_MONO_ADC_L_BST_MASK … #define RT5645_MONO_ADC_L_BST_SFT … #define RT5645_MONO_ADC_R_BST_MASK … #define RT5645_MONO_ADC_R_BST_SFT … #define RT5645_MONO_ADC_COMP_MASK … #define RT5645_MONO_ADC_COMP_SFT … /* Stereo2 ADC Mixer Control (0x26) */ #define RT5645_STO2_ADC_SRC_MASK … #define RT5645_STO2_ADC_SRC_SFT … /* Stereo ADC Mixer Control (0x27) */ #define RT5645_M_ADC_L1 … #define RT5645_M_ADC_L1_SFT … #define RT5645_M_ADC_L2 … #define RT5645_M_ADC_L2_SFT … #define RT5645_ADC_1_SRC_MASK … #define RT5645_ADC_1_SRC_SFT … #define RT5645_ADC_1_SRC_ADC … #define RT5645_ADC_1_SRC_DACMIX … #define RT5645_ADC_2_SRC_MASK … #define RT5645_ADC_2_SRC_SFT … #define RT5645_DMIC_SRC_MASK … #define RT5645_DMIC_SRC_SFT … #define RT5645_M_ADC_R1 … #define RT5645_M_ADC_R1_SFT … #define RT5645_M_ADC_R2 … #define RT5645_M_ADC_R2_SFT … #define RT5645_DMIC3_SRC_MASK … #define RT5645_DMIC3_SRC_SFT … /* Mono ADC Mixer Control (0x28) */ #define RT5645_M_MONO_ADC_L1 … #define RT5645_M_MONO_ADC_L1_SFT … #define RT5645_M_MONO_ADC_L2 … #define RT5645_M_MONO_ADC_L2_SFT … #define RT5645_MONO_ADC_L1_SRC_MASK … #define RT5645_MONO_ADC_L1_SRC_SFT … #define RT5645_MONO_ADC_L1_SRC_DACMIXL … #define RT5645_MONO_ADC_L1_SRC_ADCL … #define RT5645_MONO_ADC_L2_SRC_MASK … #define RT5645_MONO_ADC_L2_SRC_SFT … #define RT5645_MONO_DMIC_L_SRC_MASK … #define RT5645_MONO_DMIC_L_SRC_SFT … #define RT5645_M_MONO_ADC_R1 … #define RT5645_M_MONO_ADC_R1_SFT … #define RT5645_M_MONO_ADC_R2 … #define RT5645_M_MONO_ADC_R2_SFT … #define RT5645_MONO_ADC_R1_SRC_MASK … #define RT5645_MONO_ADC_R1_SRC_SFT … #define RT5645_MONO_ADC_R1_SRC_ADCR … #define RT5645_MONO_ADC_R1_SRC_DACMIXR … #define RT5645_MONO_ADC_R2_SRC_MASK … #define RT5645_MONO_ADC_R2_SRC_SFT … #define RT5645_MONO_DMIC_R_SRC_MASK … #define RT5645_MONO_DMIC_R_SRC_SFT … /* ADC Mixer to DAC Mixer Control (0x29) */ #define RT5645_M_ADCMIX_L … #define RT5645_M_ADCMIX_L_SFT … #define RT5645_M_DAC1_L … #define RT5645_M_DAC1_L_SFT … #define RT5645_DAC1_R_SEL_MASK … #define RT5645_DAC1_R_SEL_SFT … #define RT5645_DAC1_R_SEL_IF1 … #define RT5645_DAC1_R_SEL_IF2 … #define RT5645_DAC1_R_SEL_IF3 … #define RT5645_DAC1_R_SEL_IF4 … #define RT5645_DAC1_L_SEL_MASK … #define RT5645_DAC1_L_SEL_SFT … #define RT5645_DAC1_L_SEL_IF1 … #define RT5645_DAC1_L_SEL_IF2 … #define RT5645_DAC1_L_SEL_IF3 … #define RT5645_DAC1_L_SEL_IF4 … #define RT5645_M_ADCMIX_R … #define RT5645_M_ADCMIX_R_SFT … #define RT5645_M_DAC1_R … #define RT5645_M_DAC1_R_SFT … /* Stereo DAC Mixer Control (0x2a) */ #define RT5645_M_DAC_L1 … #define RT5645_M_DAC_L1_SFT … #define RT5645_DAC_L1_STO_L_VOL_MASK … #define RT5645_DAC_L1_STO_L_VOL_SFT … #define RT5645_M_DAC_L2 … #define RT5645_M_DAC_L2_SFT … #define RT5645_DAC_L2_STO_L_VOL_MASK … #define RT5645_DAC_L2_STO_L_VOL_SFT … #define RT5645_M_ANC_DAC_L … #define RT5645_M_ANC_DAC_L_SFT … #define RT5645_M_DAC_R1_STO_L … #define RT5645_M_DAC_R1_STO_L_SFT … #define RT5645_DAC_R1_STO_L_VOL_MASK … #define RT5645_DAC_R1_STO_L_VOL_SFT … #define RT5645_M_DAC_R1 … #define RT5645_M_DAC_R1_SFT … #define RT5645_DAC_R1_STO_R_VOL_MASK … #define RT5645_DAC_R1_STO_R_VOL_SFT … #define RT5645_M_DAC_R2 … #define RT5645_M_DAC_R2_SFT … #define RT5645_DAC_R2_STO_R_VOL_MASK … #define RT5645_DAC_R2_STO_R_VOL_SFT … #define RT5645_M_ANC_DAC_R … #define RT5645_M_ANC_DAC_R_SFT … #define RT5645_M_DAC_L1_STO_R … #define RT5645_M_DAC_L1_STO_R_SFT … #define RT5645_DAC_L1_STO_R_VOL_MASK … #define RT5645_DAC_L1_STO_R_VOL_SFT … /* Mono DAC Mixer Control (0x2b) */ #define RT5645_M_DAC_L1_MONO_L … #define RT5645_M_DAC_L1_MONO_L_SFT … #define RT5645_DAC_L1_MONO_L_VOL_MASK … #define RT5645_DAC_L1_MONO_L_VOL_SFT … #define RT5645_M_DAC_L2_MONO_L … #define RT5645_M_DAC_L2_MONO_L_SFT … #define RT5645_DAC_L2_MONO_L_VOL_MASK … #define RT5645_DAC_L2_MONO_L_VOL_SFT … #define RT5645_M_DAC_R2_MONO_L … #define RT5645_M_DAC_R2_MONO_L_SFT … #define RT5645_DAC_R2_MONO_L_VOL_MASK … #define RT5645_DAC_R2_MONO_L_VOL_SFT … #define RT5645_M_DAC_R1_MONO_R … #define RT5645_M_DAC_R1_MONO_R_SFT … #define RT5645_DAC_R1_MONO_R_VOL_MASK … #define RT5645_DAC_R1_MONO_R_VOL_SFT … #define RT5645_M_DAC_R2_MONO_R … #define RT5645_M_DAC_R2_MONO_R_SFT … #define RT5645_DAC_R2_MONO_R_VOL_MASK … #define RT5645_DAC_R2_MONO_R_VOL_SFT … #define RT5645_M_DAC_L2_MONO_R … #define RT5645_M_DAC_L2_MONO_R_SFT … #define RT5645_DAC_L2_MONO_R_VOL_MASK … #define RT5645_DAC_L2_MONO_R_VOL_SFT … /* Digital Mixer Control (0x2c) */ #define RT5645_M_STO_L_DAC_L … #define RT5645_M_STO_L_DAC_L_SFT … #define RT5645_STO_L_DAC_L_VOL_MASK … #define RT5645_STO_L_DAC_L_VOL_SFT … #define RT5645_M_DAC_L2_DAC_L … #define RT5645_M_DAC_L2_DAC_L_SFT … #define RT5645_DAC_L2_DAC_L_VOL_MASK … #define RT5645_DAC_L2_DAC_L_VOL_SFT … #define RT5645_M_STO_R_DAC_R … #define RT5645_M_STO_R_DAC_R_SFT … #define RT5645_STO_R_DAC_R_VOL_MASK … #define RT5645_STO_R_DAC_R_VOL_SFT … #define RT5645_M_DAC_R2_DAC_R … #define RT5645_M_DAC_R2_DAC_R_SFT … #define RT5645_DAC_R2_DAC_R_VOL_MASK … #define RT5645_DAC_R2_DAC_R_VOL_SFT … #define RT5645_M_DAC_R2_DAC_L … #define RT5645_M_DAC_R2_DAC_L_SFT … #define RT5645_DAC_R2_DAC_L_VOL_MASK … #define RT5645_DAC_R2_DAC_L_VOL_SFT … #define RT5645_M_DAC_L2_DAC_R … #define RT5645_M_DAC_L2_DAC_R_SFT … #define RT5645_DAC_L2_DAC_R_VOL_MASK … #define RT5645_DAC_L2_DAC_R_VOL_SFT … /* Analog DAC1/2 Input Source Control (0x2d) */ #define RT5650_A_DAC1_L_IN_SFT … #define RT5650_A_DAC1_R_IN_SFT … #define RT5650_A_DAC2_L_IN_SFT … #define RT5650_A_DAC2_R_IN_SFT … /* Digital Interface Data Control (0x2f) */ #define RT5645_IF1_ADC2_IN_SEL … #define RT5645_IF1_ADC2_IN_SFT … #define RT5645_IF2_ADC_IN_MASK … #define RT5645_IF2_ADC_IN_SFT … #define RT5645_IF2_DAC_SEL_MASK … #define RT5645_IF2_DAC_SEL_SFT … #define RT5645_IF2_ADC_SEL_MASK … #define RT5645_IF2_ADC_SEL_SFT … #define RT5645_IF3_DAC_SEL_MASK … #define RT5645_IF3_DAC_SEL_SFT … #define RT5645_IF3_ADC_SEL_MASK … #define RT5645_IF3_ADC_SEL_SFT … #define RT5645_IF3_ADC_IN_MASK … #define RT5645_IF3_ADC_IN_SFT … /* PDM Output Control (0x31) */ #define RT5645_PDM1_L_MASK … #define RT5645_PDM1_L_SFT … #define RT5645_M_PDM1_L … #define RT5645_M_PDM1_L_SFT … #define RT5645_PDM1_R_MASK … #define RT5645_PDM1_R_SFT … #define RT5645_M_PDM1_R … #define RT5645_M_PDM1_R_SFT … #define RT5645_PDM2_L_MASK … #define RT5645_PDM2_L_SFT … #define RT5645_M_PDM2_L … #define RT5645_M_PDM2_L_SFT … #define RT5645_PDM2_R_MASK … #define RT5645_PDM2_R_SFT … #define RT5645_M_PDM2_R … #define RT5645_M_PDM2_R_SFT … #define RT5645_PDM2_BUSY … #define RT5645_PDM1_BUSY … #define RT5645_PDM_PATTERN … #define RT5645_PDM_GAIN … #define RT5645_PDM_DIV_MASK … /* REC Left Mixer Control 1 (0x3b) */ #define RT5645_G_HP_L_RM_L_MASK … #define RT5645_G_HP_L_RM_L_SFT … #define RT5645_G_IN_L_RM_L_MASK … #define RT5645_G_IN_L_RM_L_SFT … #define RT5645_G_BST4_RM_L_MASK … #define RT5645_G_BST4_RM_L_SFT … #define RT5645_G_BST3_RM_L_MASK … #define RT5645_G_BST3_RM_L_SFT … #define RT5645_G_BST2_RM_L_MASK … #define RT5645_G_BST2_RM_L_SFT … /* REC Left Mixer Control 2 (0x3c) */ #define RT5645_G_BST1_RM_L_MASK … #define RT5645_G_BST1_RM_L_SFT … #define RT5645_G_OM_L_RM_L_MASK … #define RT5645_G_OM_L_RM_L_SFT … #define RT5645_M_MM_L_RM_L … #define RT5645_M_MM_L_RM_L_SFT … #define RT5645_M_IN_L_RM_L … #define RT5645_M_IN_L_RM_L_SFT … #define RT5645_M_HP_L_RM_L … #define RT5645_M_HP_L_RM_L_SFT … #define RT5645_M_BST3_RM_L … #define RT5645_M_BST3_RM_L_SFT … #define RT5645_M_BST2_RM_L … #define RT5645_M_BST2_RM_L_SFT … #define RT5645_M_BST1_RM_L … #define RT5645_M_BST1_RM_L_SFT … #define RT5645_M_OM_L_RM_L … #define RT5645_M_OM_L_RM_L_SFT … /* REC Right Mixer Control 1 (0x3d) */ #define RT5645_G_HP_R_RM_R_MASK … #define RT5645_G_HP_R_RM_R_SFT … #define RT5645_G_IN_R_RM_R_MASK … #define RT5645_G_IN_R_RM_R_SFT … #define RT5645_G_BST4_RM_R_MASK … #define RT5645_G_BST4_RM_R_SFT … #define RT5645_G_BST3_RM_R_MASK … #define RT5645_G_BST3_RM_R_SFT … #define RT5645_G_BST2_RM_R_MASK … #define RT5645_G_BST2_RM_R_SFT … /* REC Right Mixer Control 2 (0x3e) */ #define RT5645_G_BST1_RM_R_MASK … #define RT5645_G_BST1_RM_R_SFT … #define RT5645_G_OM_R_RM_R_MASK … #define RT5645_G_OM_R_RM_R_SFT … #define RT5645_M_MM_R_RM_R … #define RT5645_M_MM_R_RM_R_SFT … #define RT5645_M_IN_R_RM_R … #define RT5645_M_IN_R_RM_R_SFT … #define RT5645_M_HP_R_RM_R … #define RT5645_M_HP_R_RM_R_SFT … #define RT5645_M_BST3_RM_R … #define RT5645_M_BST3_RM_R_SFT … #define RT5645_M_BST2_RM_R … #define RT5645_M_BST2_RM_R_SFT … #define RT5645_M_BST1_RM_R … #define RT5645_M_BST1_RM_R_SFT … #define RT5645_M_OM_R_RM_R … #define RT5645_M_OM_R_RM_R_SFT … /* HPOMIX Control (0x40) (0x42) */ #define RT5645_M_BST1_HV … #define RT5645_M_BST1_HV_SFT … #define RT5645_M_BST2_HV … #define RT5645_M_BST2_HV_SFT … #define RT5645_M_BST3_HV … #define RT5645_M_BST3_HV_SFT … #define RT5645_M_IN_HV … #define RT5645_M_IN_HV_SFT … #define RT5645_M_DAC2_HV … #define RT5645_M_DAC2_HV_SFT … #define RT5645_M_DAC1_HV … #define RT5645_M_DAC1_HV_SFT … /* HPMIX Control (0x45) */ #define RT5645_M_DAC1_HM … #define RT5645_M_DAC1_HM_SFT … #define RT5645_M_HPVOL_HM … #define RT5645_M_HPVOL_HM_SFT … #define RT5645_IRQ_PSV_MODE … /* SPK Left Mixer Control (0x46) */ #define RT5645_G_RM_L_SM_L_MASK … #define RT5645_G_RM_L_SM_L_SFT … #define RT5645_G_IN_L_SM_L_MASK … #define RT5645_G_IN_L_SM_L_SFT … #define RT5645_G_DAC_L1_SM_L_MASK … #define RT5645_G_DAC_L1_SM_L_SFT … #define RT5645_G_DAC_L2_SM_L_MASK … #define RT5645_G_DAC_L2_SM_L_SFT … #define RT5645_G_OM_L_SM_L_MASK … #define RT5645_G_OM_L_SM_L_SFT … #define RT5645_M_BST1_L_SM_L … #define RT5645_M_BST1_L_SM_L_SFT … #define RT5645_M_BST3_L_SM_L … #define RT5645_M_BST3_L_SM_L_SFT … #define RT5645_M_IN_L_SM_L … #define RT5645_M_IN_L_SM_L_SFT … #define RT5645_M_DAC_L2_SM_L … #define RT5645_M_DAC_L2_SM_L_SFT … #define RT5645_M_DAC_L1_SM_L … #define RT5645_M_DAC_L1_SM_L_SFT … /* SPK Right Mixer Control (0x47) */ #define RT5645_G_RM_R_SM_R_MASK … #define RT5645_G_RM_R_SM_R_SFT … #define RT5645_G_IN_R_SM_R_MASK … #define RT5645_G_IN_R_SM_R_SFT … #define RT5645_G_DAC_R1_SM_R_MASK … #define RT5645_G_DAC_R1_SM_R_SFT … #define RT5645_G_DAC_R2_SM_R_MASK … #define RT5645_G_DAC_R2_SM_R_SFT … #define RT5645_G_OM_R_SM_R_MASK … #define RT5645_G_OM_R_SM_R_SFT … #define RT5645_M_BST2_R_SM_R … #define RT5645_M_BST2_R_SM_R_SFT … #define RT5645_M_BST3_R_SM_R … #define RT5645_M_BST3_R_SM_R_SFT … #define RT5645_M_IN_R_SM_R … #define RT5645_M_IN_R_SM_R_SFT … #define RT5645_M_DAC_R2_SM_R … #define RT5645_M_DAC_R2_SM_R_SFT … #define RT5645_M_DAC_R1_SM_R … #define RT5645_M_DAC_R1_SM_R_SFT … /* SPOLMIX Control (0x48) */ #define RT5645_M_DAC_L1_SPM_L … #define RT5645_M_DAC_L1_SPM_L_SFT … #define RT5645_M_DAC_R1_SPM_L … #define RT5645_M_DAC_R1_SPM_L_SFT … #define RT5645_M_SV_L_SPM_L … #define RT5645_M_SV_L_SPM_L_SFT … #define RT5645_M_SV_R_SPM_L … #define RT5645_M_SV_R_SPM_L_SFT … #define RT5645_M_BST3_SPM_L … #define RT5645_M_BST3_SPM_L_SFT … #define RT5645_M_DAC_R1_SPM_R … #define RT5645_M_DAC_R1_SPM_R_SFT … #define RT5645_M_BST3_SPM_R … #define RT5645_M_BST3_SPM_R_SFT … #define RT5645_M_SV_R_SPM_R … #define RT5645_M_SV_R_SPM_R_SFT … /* SPOMIX Ratio Control (0x4a) */ #define RT5645_SPK_G_CLSD_MASK … #define RT5645_SPK_G_CLSD_SFT … /* Mono Output Mixer Control (0x4c) */ #define RT5645_G_MONOMIX_MASK … #define RT5645_G_MONOMIX_SFT … #define RT5645_M_OV_L_MM … #define RT5645_M_OV_L_MM_SFT … #define RT5645_M_DAC_L2_MA … #define RT5645_M_DAC_L2_MA_SFT … #define RT5645_M_BST2_MM … #define RT5645_M_BST2_MM_SFT … #define RT5645_M_DAC_R1_MM … #define RT5645_M_DAC_R1_MM_SFT … #define RT5645_M_DAC_R2_MM … #define RT5645_M_DAC_R2_MM_SFT … #define RT5645_M_DAC_L2_MM … #define RT5645_M_DAC_L2_MM_SFT … #define RT5645_M_BST3_MM … #define RT5645_M_BST3_MM_SFT … /* Output Left Mixer Control 1 (0x4d) */ #define RT5645_G_BST3_OM_L_MASK … #define RT5645_G_BST3_OM_L_SFT … #define RT5645_G_BST2_OM_L_MASK … #define RT5645_G_BST2_OM_L_SFT … #define RT5645_G_BST1_OM_L_MASK … #define RT5645_G_BST1_OM_L_SFT … #define RT5645_G_IN_L_OM_L_MASK … #define RT5645_G_IN_L_OM_L_SFT … #define RT5645_G_RM_L_OM_L_MASK … #define RT5645_G_RM_L_OM_L_SFT … /* Output Left Mixer Control 2 (0x4e) */ #define RT5645_G_DAC_R2_OM_L_MASK … #define RT5645_G_DAC_R2_OM_L_SFT … #define RT5645_G_DAC_L2_OM_L_MASK … #define RT5645_G_DAC_L2_OM_L_SFT … #define RT5645_G_DAC_L1_OM_L_MASK … #define RT5645_G_DAC_L1_OM_L_SFT … /* Output Left Mixer Control 3 (0x4f) */ #define RT5645_M_BST3_OM_L … #define RT5645_M_BST3_OM_L_SFT … #define RT5645_M_BST1_OM_L … #define RT5645_M_BST1_OM_L_SFT … #define RT5645_M_IN_L_OM_L … #define RT5645_M_IN_L_OM_L_SFT … #define RT5645_M_DAC_L2_OM_L … #define RT5645_M_DAC_L2_OM_L_SFT … #define RT5645_M_DAC_L1_OM_L … #define RT5645_M_DAC_L1_OM_L_SFT … /* Output Right Mixer Control 1 (0x50) */ #define RT5645_G_BST4_OM_R_MASK … #define RT5645_G_BST4_OM_R_SFT … #define RT5645_G_BST2_OM_R_MASK … #define RT5645_G_BST2_OM_R_SFT … #define RT5645_G_BST1_OM_R_MASK … #define RT5645_G_BST1_OM_R_SFT … #define RT5645_G_IN_R_OM_R_MASK … #define RT5645_G_IN_R_OM_R_SFT … #define RT5645_G_RM_R_OM_R_MASK … #define RT5645_G_RM_R_OM_R_SFT … /* Output Right Mixer Control 2 (0x51) */ #define RT5645_G_DAC_L2_OM_R_MASK … #define RT5645_G_DAC_L2_OM_R_SFT … #define RT5645_G_DAC_R2_OM_R_MASK … #define RT5645_G_DAC_R2_OM_R_SFT … #define RT5645_G_DAC_R1_OM_R_MASK … #define RT5645_G_DAC_R1_OM_R_SFT … /* Output Right Mixer Control 3 (0x52) */ #define RT5645_M_BST3_OM_R … #define RT5645_M_BST3_OM_R_SFT … #define RT5645_M_BST2_OM_R … #define RT5645_M_BST2_OM_R_SFT … #define RT5645_M_IN_R_OM_R … #define RT5645_M_IN_R_OM_R_SFT … #define RT5645_M_DAC_R2_OM_R … #define RT5645_M_DAC_R2_OM_R_SFT … #define RT5645_M_DAC_R1_OM_R … #define RT5645_M_DAC_R1_OM_R_SFT … /* LOUT Mixer Control (0x53) */ #define RT5645_M_DAC_L1_LM … #define RT5645_M_DAC_L1_LM_SFT … #define RT5645_M_DAC_R1_LM … #define RT5645_M_DAC_R1_LM_SFT … #define RT5645_M_OV_L_LM … #define RT5645_M_OV_L_LM_SFT … #define RT5645_M_OV_R_LM … #define RT5645_M_OV_R_LM_SFT … #define RT5645_G_LOUTMIX_MASK … #define RT5645_G_LOUTMIX_SFT … /* Power Management for Digital 1 (0x61) */ #define RT5645_PWR_I2S1 … #define RT5645_PWR_I2S1_BIT … #define RT5645_PWR_I2S2 … #define RT5645_PWR_I2S2_BIT … #define RT5645_PWR_I2S3 … #define RT5645_PWR_I2S3_BIT … #define RT5645_PWR_DAC_L1 … #define RT5645_PWR_DAC_L1_BIT … #define RT5645_PWR_DAC_R1 … #define RT5645_PWR_DAC_R1_BIT … #define RT5645_PWR_CLS_D_R … #define RT5645_PWR_CLS_D_R_BIT … #define RT5645_PWR_CLS_D_L … #define RT5645_PWR_CLS_D_L_BIT … #define RT5645_PWR_DAC_L2 … #define RT5645_PWR_DAC_L2_BIT … #define RT5645_PWR_DAC_R2 … #define RT5645_PWR_DAC_R2_BIT … #define RT5645_PWR_ADC_L … #define RT5645_PWR_ADC_L_BIT … #define RT5645_PWR_ADC_R … #define RT5645_PWR_ADC_R_BIT … #define RT5645_PWR_CLS_D … #define RT5645_PWR_CLS_D_BIT … /* Power Management for Digital 2 (0x62) */ #define RT5645_PWR_ADC_S1F … #define RT5645_PWR_ADC_S1F_BIT … #define RT5645_PWR_ADC_MF_L … #define RT5645_PWR_ADC_MF_L_BIT … #define RT5645_PWR_ADC_MF_R … #define RT5645_PWR_ADC_MF_R_BIT … #define RT5645_PWR_I2S_DSP … #define RT5645_PWR_I2S_DSP_BIT … #define RT5645_PWR_DAC_S1F … #define RT5645_PWR_DAC_S1F_BIT … #define RT5645_PWR_DAC_MF_L … #define RT5645_PWR_DAC_MF_L_BIT … #define RT5645_PWR_DAC_MF_R … #define RT5645_PWR_DAC_MF_R_BIT … #define RT5645_PWR_PDM1 … #define RT5645_PWR_PDM1_BIT … #define RT5645_PWR_PDM2 … #define RT5645_PWR_PDM2_BIT … #define RT5645_PWR_IPTV … #define RT5645_PWR_IPTV_BIT … #define RT5645_PWR_PAD … #define RT5645_PWR_PAD_BIT … /* Power Management for Analog 1 (0x63) */ #define RT5645_PWR_VREF1 … #define RT5645_PWR_VREF1_BIT … #define RT5645_PWR_FV1 … #define RT5645_PWR_FV1_BIT … #define RT5645_PWR_MB … #define RT5645_PWR_MB_BIT … #define RT5645_PWR_LM … #define RT5645_PWR_LM_BIT … #define RT5645_PWR_BG … #define RT5645_PWR_BG_BIT … #define RT5645_PWR_MA … #define RT5645_PWR_MA_BIT … #define RT5645_PWR_HP_L … #define RT5645_PWR_HP_L_BIT … #define RT5645_PWR_HP_R … #define RT5645_PWR_HP_R_BIT … #define RT5645_PWR_HA … #define RT5645_PWR_HA_BIT … #define RT5645_PWR_VREF2 … #define RT5645_PWR_VREF2_BIT … #define RT5645_PWR_FV2 … #define RT5645_PWR_FV2_BIT … #define RT5645_LDO_SEL_MASK … #define RT5645_LDO_SEL_SFT … /* Power Management for Analog 2 (0x64) */ #define RT5645_PWR_BST1 … #define RT5645_PWR_BST1_BIT … #define RT5645_PWR_BST2 … #define RT5645_PWR_BST2_BIT … #define RT5645_PWR_BST3 … #define RT5645_PWR_BST3_BIT … #define RT5645_PWR_BST4 … #define RT5645_PWR_BST4_BIT … #define RT5645_PWR_MB1 … #define RT5645_PWR_MB1_BIT … #define RT5645_PWR_MB2 … #define RT5645_PWR_MB2_BIT … #define RT5645_PWR_PLL … #define RT5645_PWR_PLL_BIT … #define RT5645_PWR_BST2_P … #define RT5645_PWR_BST2_P_BIT … #define RT5645_PWR_BST3_P … #define RT5645_PWR_BST3_P_BIT … #define RT5645_PWR_BST4_P … #define RT5645_PWR_BST4_P_BIT … #define RT5645_PWR_JD1 … #define RT5645_PWR_JD1_BIT … #define RT5645_PWR_JD … #define RT5645_PWR_JD_BIT … /* Power Management for Mixer (0x65) */ #define RT5645_PWR_OM_L … #define RT5645_PWR_OM_L_BIT … #define RT5645_PWR_OM_R … #define RT5645_PWR_OM_R_BIT … #define RT5645_PWR_SM_L … #define RT5645_PWR_SM_L_BIT … #define RT5645_PWR_SM_R … #define RT5645_PWR_SM_R_BIT … #define RT5645_PWR_RM_L … #define RT5645_PWR_RM_L_BIT … #define RT5645_PWR_RM_R … #define RT5645_PWR_RM_R_BIT … #define RT5645_PWR_MM … #define RT5645_PWR_MM_BIT … #define RT5645_PWR_HM_L … #define RT5645_PWR_HM_L_BIT … #define RT5645_PWR_HM_R … #define RT5645_PWR_HM_R_BIT … #define RT5645_PWR_LDO2 … #define RT5645_PWR_LDO2_BIT … /* Power Management for Volume (0x66) */ #define RT5645_PWR_SV_L … #define RT5645_PWR_SV_L_BIT … #define RT5645_PWR_SV_R … #define RT5645_PWR_SV_R_BIT … #define RT5645_PWR_HV_L … #define RT5645_PWR_HV_L_BIT … #define RT5645_PWR_HV_R … #define RT5645_PWR_HV_R_BIT … #define RT5645_PWR_IN_L … #define RT5645_PWR_IN_L_BIT … #define RT5645_PWR_IN_R … #define RT5645_PWR_IN_R_BIT … #define RT5645_PWR_MIC_DET … #define RT5645_PWR_MIC_DET_BIT … /* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */ #define RT5645_I2S_MS_MASK … #define RT5645_I2S_MS_SFT … #define RT5645_I2S_MS_M … #define RT5645_I2S_MS_S … #define RT5645_I2S_O_CP_MASK … #define RT5645_I2S_O_CP_SFT … #define RT5645_I2S_O_CP_OFF … #define RT5645_I2S_O_CP_U_LAW … #define RT5645_I2S_O_CP_A_LAW … #define RT5645_I2S_I_CP_MASK … #define RT5645_I2S_I_CP_SFT … #define RT5645_I2S_I_CP_OFF … #define RT5645_I2S_I_CP_U_LAW … #define RT5645_I2S_I_CP_A_LAW … #define RT5645_I2S_BP_MASK … #define RT5645_I2S_BP_SFT … #define RT5645_I2S_BP_NOR … #define RT5645_I2S_BP_INV … #define RT5645_I2S_DL_MASK … #define RT5645_I2S_DL_SFT … #define RT5645_I2S_DL_16 … #define RT5645_I2S_DL_20 … #define RT5645_I2S_DL_24 … #define RT5645_I2S_DL_8 … #define RT5645_I2S_DF_MASK … #define RT5645_I2S_DF_SFT … #define RT5645_I2S_DF_I2S … #define RT5645_I2S_DF_LEFT … #define RT5645_I2S_DF_PCM_A … #define RT5645_I2S_DF_PCM_B … /* I2S2 Audio Serial Data Port Control (0x71) */ #define RT5645_I2S2_SDI_MASK … #define RT5645_I2S2_SDI_SFT … #define RT5645_I2S2_SDI_I2S1 … #define RT5645_I2S2_SDI_I2S2 … /* ADC/DAC Clock Control 1 (0x73) */ #define RT5645_I2S_PD1_MASK … #define RT5645_I2S_PD1_SFT … #define RT5645_I2S_PD1_1 … #define RT5645_I2S_PD1_2 … #define RT5645_I2S_PD1_3 … #define RT5645_I2S_PD1_4 … #define RT5645_I2S_PD1_6 … #define RT5645_I2S_PD1_8 … #define RT5645_I2S_PD1_12 … #define RT5645_I2S_PD1_16 … #define RT5645_I2S_BCLK_MS2_MASK … #define RT5645_I2S_BCLK_MS2_SFT … #define RT5645_I2S_BCLK_MS2_32 … #define RT5645_I2S_BCLK_MS2_64 … #define RT5645_I2S_PD2_MASK … #define RT5645_I2S_PD2_SFT … #define RT5645_I2S_PD2_1 … #define RT5645_I2S_PD2_2 … #define RT5645_I2S_PD2_3 … #define RT5645_I2S_PD2_4 … #define RT5645_I2S_PD2_6 … #define RT5645_I2S_PD2_8 … #define RT5645_I2S_PD2_12 … #define RT5645_I2S_PD2_16 … #define RT5645_I2S_BCLK_MS3_MASK … #define RT5645_I2S_BCLK_MS3_SFT … #define RT5645_I2S_BCLK_MS3_32 … #define RT5645_I2S_BCLK_MS3_64 … #define RT5645_I2S_PD3_MASK … #define RT5645_I2S_PD3_SFT … #define RT5645_I2S_PD3_1 … #define RT5645_I2S_PD3_2 … #define RT5645_I2S_PD3_3 … #define RT5645_I2S_PD3_4 … #define RT5645_I2S_PD3_6 … #define RT5645_I2S_PD3_8 … #define RT5645_I2S_PD3_12 … #define RT5645_I2S_PD3_16 … #define RT5645_DAC_OSR_MASK … #define RT5645_DAC_OSR_SFT … #define RT5645_DAC_OSR_128 … #define RT5645_DAC_OSR_64 … #define RT5645_DAC_OSR_32 … #define RT5645_DAC_OSR_16 … #define RT5645_ADC_OSR_MASK … #define RT5645_ADC_OSR_SFT … #define RT5645_ADC_OSR_128 … #define RT5645_ADC_OSR_64 … #define RT5645_ADC_OSR_32 … #define RT5645_ADC_OSR_16 … /* ADC/DAC Clock Control 2 (0x74) */ #define RT5645_DAC_L_OSR_MASK … #define RT5645_DAC_L_OSR_SFT … #define RT5645_DAC_L_OSR_128 … #define RT5645_DAC_L_OSR_64 … #define RT5645_DAC_L_OSR_32 … #define RT5645_DAC_L_OSR_16 … #define RT5645_ADC_R_OSR_MASK … #define RT5645_ADC_R_OSR_SFT … #define RT5645_ADC_R_OSR_128 … #define RT5645_ADC_R_OSR_64 … #define RT5645_ADC_R_OSR_32 … #define RT5645_ADC_R_OSR_16 … #define RT5645_DAHPF_EN … #define RT5645_DAHPF_EN_SFT … #define RT5645_ADHPF_EN … #define RT5645_ADHPF_EN_SFT … /* Digital Microphone Control (0x75) */ #define RT5645_DMIC_1_EN_MASK … #define RT5645_DMIC_1_EN_SFT … #define RT5645_DMIC_1_DIS … #define RT5645_DMIC_1_EN … #define RT5645_DMIC_2_EN_MASK … #define RT5645_DMIC_2_EN_SFT … #define RT5645_DMIC_2_DIS … #define RT5645_DMIC_2_EN … #define RT5645_DMIC_1L_LH_MASK … #define RT5645_DMIC_1L_LH_SFT … #define RT5645_DMIC_1L_LH_FALLING … #define RT5645_DMIC_1L_LH_RISING … #define RT5645_DMIC_1R_LH_MASK … #define RT5645_DMIC_1R_LH_SFT … #define RT5645_DMIC_1R_LH_FALLING … #define RT5645_DMIC_1R_LH_RISING … #define RT5645_DMIC_2_DP_MASK … #define RT5645_DMIC_2_DP_SFT … #define RT5645_DMIC_2_DP_GPIO6 … #define RT5645_DMIC_2_DP_GPIO10 … #define RT5645_DMIC_2_DP_GPIO12 … #define RT5645_DMIC_2_DP_IN2P … #define RT5645_DMIC_2L_LH_MASK … #define RT5645_DMIC_2L_LH_SFT … #define RT5645_DMIC_2L_LH_FALLING … #define RT5645_DMIC_2L_LH_RISING … #define RT5645_DMIC_2R_LH_MASK … #define RT5645_DMIC_2R_LH_SFT … #define RT5645_DMIC_2R_LH_FALLING … #define RT5645_DMIC_2R_LH_RISING … #define RT5645_DMIC_CLK_MASK … #define RT5645_DMIC_CLK_SFT … #define RT5645_DMIC_3_EN_MASK … #define RT5645_DMIC_3_EN_SFT … #define RT5645_DMIC_3_DIS … #define RT5645_DMIC_3_EN … #define RT5645_DMIC_1_DP_MASK … #define RT5645_DMIC_1_DP_SFT … #define RT5645_DMIC_1_DP_GPIO5 … #define RT5645_DMIC_1_DP_IN2N … #define RT5645_DMIC_1_DP_GPIO11 … /* TDM Control 1 (0x77) */ #define RT5645_IF1_ADC_IN_MASK … #define RT5645_IF1_ADC_IN_SFT … /* Global Clock Control (0x80) */ #define RT5645_SCLK_SRC_MASK … #define RT5645_SCLK_SRC_SFT … #define RT5645_SCLK_SRC_MCLK … #define RT5645_SCLK_SRC_PLL1 … #define RT5645_SCLK_SRC_RCCLK … #define RT5645_PLL1_SRC_MASK … #define RT5645_PLL1_SRC_SFT … #define RT5645_PLL1_SRC_MCLK … #define RT5645_PLL1_SRC_BCLK1 … #define RT5645_PLL1_SRC_BCLK2 … #define RT5645_PLL1_SRC_BCLK3 … #define RT5645_PLL1_SRC_RCCLK … #define RT5645_PLL1_PD_MASK … #define RT5645_PLL1_PD_SFT … #define RT5645_PLL1_PD_1 … #define RT5645_PLL1_PD_2 … #define RT5645_PLL_INP_MAX … #define RT5645_PLL_INP_MIN … /* PLL M/N/K Code Control 1 (0x81) */ #define RT5645_PLL_N_MAX … #define RT5645_PLL_N_MASK … #define RT5645_PLL_N_SFT … #define RT5645_PLL_K_MAX … #define RT5645_PLL_K_MASK … #define RT5645_PLL_K_SFT … /* PLL M/N/K Code Control 2 (0x82) */ #define RT5645_PLL_M_MAX … #define RT5645_PLL_M_MASK … #define RT5645_PLL_M_SFT … #define RT5645_PLL_M_BP … #define RT5645_PLL_M_BP_SFT … /* ASRC Control 1 (0x83) */ #define RT5645_STO_T_MASK … #define RT5645_STO_T_SFT … #define RT5645_STO_T_SCLK … #define RT5645_STO_T_LRCK1 … #define RT5645_M1_T_MASK … #define RT5645_M1_T_SFT … #define RT5645_M1_T_I2S2 … #define RT5645_M1_T_I2S2_D3 … #define RT5645_I2S2_F_MASK … #define RT5645_I2S2_F_SFT … #define RT5645_I2S2_F_I2S2_D2 … #define RT5645_I2S2_F_I2S1_TCLK … #define RT5645_DMIC_1_M_MASK … #define RT5645_DMIC_1_M_SFT … #define RT5645_DMIC_1_M_NOR … #define RT5645_DMIC_1_M_ASYN … #define RT5645_DMIC_2_M_MASK … #define RT5645_DMIC_2_M_SFT … #define RT5645_DMIC_2_M_NOR … #define RT5645_DMIC_2_M_ASYN … /* ASRC clock source selection (0x84, 0x85) */ #define RT5645_CLK_SEL_SYS … #define RT5645_CLK_SEL_I2S1_ASRC … #define RT5645_CLK_SEL_I2S2_ASRC … #define RT5645_CLK_SEL_SYS2 … /* ASRC Control 2 (0x84) */ #define RT5645_DA_STO_CLK_SEL_MASK … #define RT5645_DA_STO_CLK_SEL_SFT … #define RT5645_DA_MONOL_CLK_SEL_MASK … #define RT5645_DA_MONOL_CLK_SEL_SFT … #define RT5645_DA_MONOR_CLK_SEL_MASK … #define RT5645_DA_MONOR_CLK_SEL_SFT … #define RT5645_AD_STO1_CLK_SEL_MASK … #define RT5645_AD_STO1_CLK_SEL_SFT … /* ASRC Control 3 (0x85) */ #define RT5645_AD_MONOL_CLK_SEL_MASK … #define RT5645_AD_MONOL_CLK_SEL_SFT … #define RT5645_AD_MONOR_CLK_SEL_MASK … #define RT5645_AD_MONOR_CLK_SEL_SFT … /* ASRC Control 4 (0x89) */ #define RT5645_I2S1_PD_MASK … #define RT5645_I2S1_PD_SFT … #define RT5645_I2S2_PD_MASK … #define RT5645_I2S2_PD_SFT … /* HPOUT Over Current Detection (0x8b) */ #define RT5645_HP_OVCD_MASK … #define RT5645_HP_OVCD_SFT … #define RT5645_HP_OVCD_DIS … #define RT5645_HP_OVCD_EN … #define RT5645_HP_OC_TH_MASK … #define RT5645_HP_OC_TH_SFT … #define RT5645_HP_OC_TH_90 … #define RT5645_HP_OC_TH_105 … #define RT5645_HP_OC_TH_120 … #define RT5645_HP_OC_TH_135 … /* Class D Over Current Control (0x8c) */ #define RT5645_CLSD_OC_MASK … #define RT5645_CLSD_OC_SFT … #define RT5645_CLSD_OC_PU … #define RT5645_CLSD_OC_PD … #define RT5645_AUTO_PD_MASK … #define RT5645_AUTO_PD_SFT … #define RT5645_AUTO_PD_DIS … #define RT5645_AUTO_PD_EN … #define RT5645_CLSD_OC_TH_MASK … #define RT5645_CLSD_OC_TH_SFT … /* Class D Output Control (0x8d) */ #define RT5645_CLSD_RATIO_MASK … #define RT5645_CLSD_RATIO_SFT … #define RT5645_CLSD_OM_MASK … #define RT5645_CLSD_OM_SFT … #define RT5645_CLSD_OM_MONO … #define RT5645_CLSD_OM_STO … #define RT5645_CLSD_SCH_MASK … #define RT5645_CLSD_SCH_SFT … #define RT5645_CLSD_SCH_L … #define RT5645_CLSD_SCH_S … /* Depop Mode Control 1 (0x8e) */ #define RT5645_SMT_TRIG_MASK … #define RT5645_SMT_TRIG_SFT … #define RT5645_SMT_TRIG_DIS … #define RT5645_SMT_TRIG_EN … #define RT5645_HP_L_SMT_MASK … #define RT5645_HP_L_SMT_SFT … #define RT5645_HP_L_SMT_DIS … #define RT5645_HP_L_SMT_EN … #define RT5645_HP_R_SMT_MASK … #define RT5645_HP_R_SMT_SFT … #define RT5645_HP_R_SMT_DIS … #define RT5645_HP_R_SMT_EN … #define RT5645_HP_CD_PD_MASK … #define RT5645_HP_CD_PD_SFT … #define RT5645_HP_CD_PD_DIS … #define RT5645_HP_CD_PD_EN … #define RT5645_RSTN_MASK … #define RT5645_RSTN_SFT … #define RT5645_RSTN_DIS … #define RT5645_RSTN_EN … #define RT5645_RSTP_MASK … #define RT5645_RSTP_SFT … #define RT5645_RSTP_DIS … #define RT5645_RSTP_EN … #define RT5645_HP_CO_MASK … #define RT5645_HP_CO_SFT … #define RT5645_HP_CO_DIS … #define RT5645_HP_CO_EN … #define RT5645_HP_CP_MASK … #define RT5645_HP_CP_SFT … #define RT5645_HP_CP_PD … #define RT5645_HP_CP_PU … #define RT5645_HP_SG_MASK … #define RT5645_HP_SG_SFT … #define RT5645_HP_SG_DIS … #define RT5645_HP_SG_EN … #define RT5645_HP_DP_MASK … #define RT5645_HP_DP_SFT … #define RT5645_HP_DP_PD … #define RT5645_HP_DP_PU … #define RT5645_HP_CB_MASK … #define RT5645_HP_CB_SFT … #define RT5645_HP_CB_PD … #define RT5645_HP_CB_PU … /* Depop Mode Control 2 (0x8f) */ #define RT5645_DEPOP_MASK … #define RT5645_DEPOP_SFT … #define RT5645_DEPOP_AUTO … #define RT5645_DEPOP_MAN … #define RT5645_RAMP_MASK … #define RT5645_RAMP_SFT … #define RT5645_RAMP_DIS … #define RT5645_RAMP_EN … #define RT5645_BPS_MASK … #define RT5645_BPS_SFT … #define RT5645_BPS_DIS … #define RT5645_BPS_EN … #define RT5645_FAST_UPDN_MASK … #define RT5645_FAST_UPDN_SFT … #define RT5645_FAST_UPDN_DIS … #define RT5645_FAST_UPDN_EN … #define RT5645_MRES_MASK … #define RT5645_MRES_SFT … #define RT5645_MRES_15MO … #define RT5645_MRES_25MO … #define RT5645_MRES_35MO … #define RT5645_MRES_45MO … #define RT5645_VLO_MASK … #define RT5645_VLO_SFT … #define RT5645_VLO_3V … #define RT5645_VLO_32V … #define RT5645_DIG_DP_MASK … #define RT5645_DIG_DP_SFT … #define RT5645_DIG_DP_DIS … #define RT5645_DIG_DP_EN … #define RT5645_DP_TH_MASK … #define RT5645_DP_TH_SFT … /* Depop Mode Control 3 (0x90) */ #define RT5645_CP_SYS_MASK … #define RT5645_CP_SYS_SFT … #define RT5645_CP_FQ1_MASK … #define RT5645_CP_FQ1_SFT … #define RT5645_CP_FQ2_MASK … #define RT5645_CP_FQ2_SFT … #define RT5645_CP_FQ3_MASK … #define RT5645_CP_FQ3_SFT … #define RT5645_CP_FQ_1_5_KHZ … #define RT5645_CP_FQ_3_KHZ … #define RT5645_CP_FQ_6_KHZ … #define RT5645_CP_FQ_12_KHZ … #define RT5645_CP_FQ_24_KHZ … #define RT5645_CP_FQ_48_KHZ … #define RT5645_CP_FQ_96_KHZ … #define RT5645_CP_FQ_192_KHZ … /* PV detection and SPK gain control (0x92) */ #define RT5645_PVDD_DET_MASK … #define RT5645_PVDD_DET_SFT … #define RT5645_PVDD_DET_DIS … #define RT5645_PVDD_DET_EN … #define RT5645_SPK_AG_MASK … #define RT5645_SPK_AG_SFT … #define RT5645_SPK_AG_DIS … #define RT5645_SPK_AG_EN … /* Micbias Control (0x93) */ #define RT5645_MIC1_BS_MASK … #define RT5645_MIC1_BS_SFT … #define RT5645_MIC1_BS_9AV … #define RT5645_MIC1_BS_75AV … #define RT5645_MIC2_BS_MASK … #define RT5645_MIC2_BS_SFT … #define RT5645_MIC2_BS_9AV … #define RT5645_MIC2_BS_75AV … #define RT5645_MIC1_CLK_MASK … #define RT5645_MIC1_CLK_SFT … #define RT5645_MIC1_CLK_DIS … #define RT5645_MIC1_CLK_EN … #define RT5645_MIC2_CLK_MASK … #define RT5645_MIC2_CLK_SFT … #define RT5645_MIC2_CLK_DIS … #define RT5645_MIC2_CLK_EN … #define RT5645_MIC1_OVCD_MASK … #define RT5645_MIC1_OVCD_SFT … #define RT5645_MIC1_OVCD_DIS … #define RT5645_MIC1_OVCD_EN … #define RT5645_MIC1_OVTH_MASK … #define RT5645_MIC1_OVTH_SFT … #define RT5645_MIC1_OVTH_600UA … #define RT5645_MIC1_OVTH_1500UA … #define RT5645_MIC1_OVTH_2000UA … #define RT5645_MIC2_OVCD_MASK … #define RT5645_MIC2_OVCD_SFT … #define RT5645_MIC2_OVCD_DIS … #define RT5645_MIC2_OVCD_EN … #define RT5645_MIC2_OVTH_MASK … #define RT5645_MIC2_OVTH_SFT … #define RT5645_MIC2_OVTH_600UA … #define RT5645_MIC2_OVTH_1500UA … #define RT5645_MIC2_OVTH_2000UA … #define RT5645_PWR_MB_MASK … #define RT5645_PWR_MB_SFT … #define RT5645_PWR_MB_PD … #define RT5645_PWR_MB_PU … #define RT5645_PWR_CLK25M_MASK … #define RT5645_PWR_CLK25M_SFT … #define RT5645_PWR_CLK25M_PD … #define RT5645_PWR_CLK25M_PU … #define RT5645_IRQ_CLK_MCLK … #define RT5645_IRQ_CLK_INT … #define RT5645_JD1_MODE_MASK … #define RT5645_JD1_MODE_0 … #define RT5645_JD1_MODE_1 … #define RT5645_JD1_MODE_2 … /* VAD Control 4 (0x9d) */ #define RT5645_VAD_SEL_MASK … #define RT5645_VAD_SEL_SFT … /* EQ Control 1 (0xb0) */ #define RT5645_EQ_SRC_MASK … #define RT5645_EQ_SRC_SFT … #define RT5645_EQ_SRC_DAC … #define RT5645_EQ_SRC_ADC … #define RT5645_EQ_UPD … #define RT5645_EQ_UPD_BIT … #define RT5645_EQ_CD_MASK … #define RT5645_EQ_CD_SFT … #define RT5645_EQ_CD_DIS … #define RT5645_EQ_CD_EN … #define RT5645_EQ_DITH_MASK … #define RT5645_EQ_DITH_SFT … #define RT5645_EQ_DITH_NOR … #define RT5645_EQ_DITH_LSB … #define RT5645_EQ_DITH_LSB_1 … #define RT5645_EQ_DITH_LSB_2 … /* EQ Control 2 (0xb1) */ #define RT5645_EQ_HPF1_M_MASK … #define RT5645_EQ_HPF1_M_SFT … #define RT5645_EQ_HPF1_M_HI … #define RT5645_EQ_HPF1_M_1ST … #define RT5645_EQ_LPF1_M_MASK … #define RT5645_EQ_LPF1_M_SFT … #define RT5645_EQ_LPF1_M_LO … #define RT5645_EQ_LPF1_M_1ST … #define RT5645_EQ_HPF2_MASK … #define RT5645_EQ_HPF2_SFT … #define RT5645_EQ_HPF2_DIS … #define RT5645_EQ_HPF2_EN … #define RT5645_EQ_HPF1_MASK … #define RT5645_EQ_HPF1_SFT … #define RT5645_EQ_HPF1_DIS … #define RT5645_EQ_HPF1_EN … #define RT5645_EQ_BPF4_MASK … #define RT5645_EQ_BPF4_SFT … #define RT5645_EQ_BPF4_DIS … #define RT5645_EQ_BPF4_EN … #define RT5645_EQ_BPF3_MASK … #define RT5645_EQ_BPF3_SFT … #define RT5645_EQ_BPF3_DIS … #define RT5645_EQ_BPF3_EN … #define RT5645_EQ_BPF2_MASK … #define RT5645_EQ_BPF2_SFT … #define RT5645_EQ_BPF2_DIS … #define RT5645_EQ_BPF2_EN … #define RT5645_EQ_BPF1_MASK … #define RT5645_EQ_BPF1_SFT … #define RT5645_EQ_BPF1_DIS … #define RT5645_EQ_BPF1_EN … #define RT5645_EQ_LPF_MASK … #define RT5645_EQ_LPF_SFT … #define RT5645_EQ_LPF_DIS … #define RT5645_EQ_LPF_EN … #define RT5645_EQ_CTRL_MASK … /* Memory Test (0xb2) */ #define RT5645_MT_MASK … #define RT5645_MT_SFT … #define RT5645_MT_DIS … #define RT5645_MT_EN … /* DRC/AGC Control 1 (0xb4) */ #define RT5645_DRC_AGC_P_MASK … #define RT5645_DRC_AGC_P_SFT … #define RT5645_DRC_AGC_P_DAC … #define RT5645_DRC_AGC_P_ADC … #define RT5645_DRC_AGC_MASK … #define RT5645_DRC_AGC_SFT … #define RT5645_DRC_AGC_DIS … #define RT5645_DRC_AGC_EN … #define RT5645_DRC_AGC_UPD … #define RT5645_DRC_AGC_UPD_BIT … #define RT5645_DRC_AGC_AR_MASK … #define RT5645_DRC_AGC_AR_SFT … #define RT5645_DRC_AGC_R_MASK … #define RT5645_DRC_AGC_R_SFT … #define RT5645_DRC_AGC_R_48K … #define RT5645_DRC_AGC_R_96K … #define RT5645_DRC_AGC_R_192K … #define RT5645_DRC_AGC_R_441K … #define RT5645_DRC_AGC_R_882K … #define RT5645_DRC_AGC_R_1764K … #define RT5645_DRC_AGC_RC_MASK … #define RT5645_DRC_AGC_RC_SFT … /* DRC/AGC Control 2 (0xb5) */ #define RT5645_DRC_AGC_POB_MASK … #define RT5645_DRC_AGC_POB_SFT … #define RT5645_DRC_AGC_CP_MASK … #define RT5645_DRC_AGC_CP_SFT … #define RT5645_DRC_AGC_CP_DIS … #define RT5645_DRC_AGC_CP_EN … #define RT5645_DRC_AGC_CPR_MASK … #define RT5645_DRC_AGC_CPR_SFT … #define RT5645_DRC_AGC_CPR_1_1 … #define RT5645_DRC_AGC_CPR_1_2 … #define RT5645_DRC_AGC_CPR_1_3 … #define RT5645_DRC_AGC_CPR_1_4 … #define RT5645_DRC_AGC_PRB_MASK … #define RT5645_DRC_AGC_PRB_SFT … /* DRC/AGC Control 3 (0xb6) */ #define RT5645_DRC_AGC_NGB_MASK … #define RT5645_DRC_AGC_NGB_SFT … #define RT5645_DRC_AGC_TAR_MASK … #define RT5645_DRC_AGC_TAR_SFT … #define RT5645_DRC_AGC_NG_MASK … #define RT5645_DRC_AGC_NG_SFT … #define RT5645_DRC_AGC_NG_DIS … #define RT5645_DRC_AGC_NG_EN … #define RT5645_DRC_AGC_NGH_MASK … #define RT5645_DRC_AGC_NGH_SFT … #define RT5645_DRC_AGC_NGH_DIS … #define RT5645_DRC_AGC_NGH_EN … #define RT5645_DRC_AGC_NGT_MASK … #define RT5645_DRC_AGC_NGT_SFT … /* ANC Control 1 (0xb8) */ #define RT5645_ANC_M_MASK … #define RT5645_ANC_M_SFT … #define RT5645_ANC_M_NOR … #define RT5645_ANC_M_REV … #define RT5645_ANC_MASK … #define RT5645_ANC_SFT … #define RT5645_ANC_DIS … #define RT5645_ANC_EN … #define RT5645_ANC_MD_MASK … #define RT5645_ANC_MD_SFT … #define RT5645_ANC_MD_DIS … #define RT5645_ANC_MD_67MS … #define RT5645_ANC_MD_267MS … #define RT5645_ANC_MD_1067MS … #define RT5645_ANC_SN_MASK … #define RT5645_ANC_SN_SFT … #define RT5645_ANC_SN_DIS … #define RT5645_ANC_SN_EN … #define RT5645_ANC_CLK_MASK … #define RT5645_ANC_CLK_SFT … #define RT5645_ANC_CLK_ANC … #define RT5645_ANC_CLK_REG … #define RT5645_ANC_ZCD_MASK … #define RT5645_ANC_ZCD_SFT … #define RT5645_ANC_ZCD_DIS … #define RT5645_ANC_ZCD_T1 … #define RT5645_ANC_ZCD_T2 … #define RT5645_ANC_ZCD_WT … #define RT5645_ANC_CS_MASK … #define RT5645_ANC_CS_SFT … #define RT5645_ANC_CS_DIS … #define RT5645_ANC_CS_EN … #define RT5645_ANC_SW_MASK … #define RT5645_ANC_SW_SFT … #define RT5645_ANC_SW_NOR … #define RT5645_ANC_SW_AUTO … #define RT5645_ANC_CO_L_MASK … #define RT5645_ANC_CO_L_SFT … /* ANC Control 2 (0xb6) */ #define RT5645_ANC_FG_R_MASK … #define RT5645_ANC_FG_R_SFT … #define RT5645_ANC_FG_L_MASK … #define RT5645_ANC_FG_L_SFT … #define RT5645_ANC_CG_R_MASK … #define RT5645_ANC_CG_R_SFT … #define RT5645_ANC_CG_L_MASK … #define RT5645_ANC_CG_L_SFT … /* ANC Control 3 (0xb6) */ #define RT5645_ANC_CD_MASK … #define RT5645_ANC_CD_SFT … #define RT5645_ANC_CD_BOTH … #define RT5645_ANC_CD_IND … #define RT5645_ANC_CO_R_MASK … #define RT5645_ANC_CO_R_SFT … /* Jack Detect Control (0xbb) */ #define RT5645_JD_MASK … #define RT5645_JD_SFT … #define RT5645_JD_DIS … #define RT5645_JD_GPIO1 … #define RT5645_JD_JD1_IN4P … #define RT5645_JD_JD2_IN4N … #define RT5645_JD_GPIO2 … #define RT5645_JD_GPIO3 … #define RT5645_JD_GPIO4 … #define RT5645_JD_HP_MASK … #define RT5645_JD_HP_SFT … #define RT5645_JD_HP_DIS … #define RT5645_JD_HP_EN … #define RT5645_JD_HP_TRG_MASK … #define RT5645_JD_HP_TRG_SFT … #define RT5645_JD_HP_TRG_LO … #define RT5645_JD_HP_TRG_HI … #define RT5645_JD_SPL_MASK … #define RT5645_JD_SPL_SFT … #define RT5645_JD_SPL_DIS … #define RT5645_JD_SPL_EN … #define RT5645_JD_SPL_TRG_MASK … #define RT5645_JD_SPL_TRG_SFT … #define RT5645_JD_SPL_TRG_LO … #define RT5645_JD_SPL_TRG_HI … #define RT5645_JD_SPR_MASK … #define RT5645_JD_SPR_SFT … #define RT5645_JD_SPR_DIS … #define RT5645_JD_SPR_EN … #define RT5645_JD_SPR_TRG_MASK … #define RT5645_JD_SPR_TRG_SFT … #define RT5645_JD_SPR_TRG_LO … #define RT5645_JD_SPR_TRG_HI … #define RT5645_JD_MO_MASK … #define RT5645_JD_MO_SFT … #define RT5645_JD_MO_DIS … #define RT5645_JD_MO_EN … #define RT5645_JD_MO_TRG_MASK … #define RT5645_JD_MO_TRG_SFT … #define RT5645_JD_MO_TRG_LO … #define RT5645_JD_MO_TRG_HI … #define RT5645_JD_LO_MASK … #define RT5645_JD_LO_SFT … #define RT5645_JD_LO_DIS … #define RT5645_JD_LO_EN … #define RT5645_JD_LO_TRG_MASK … #define RT5645_JD_LO_TRG_SFT … #define RT5645_JD_LO_TRG_LO … #define RT5645_JD_LO_TRG_HI … #define RT5645_JD1_IN4P_MASK … #define RT5645_JD1_IN4P_SFT … #define RT5645_JD1_IN4P_DIS … #define RT5645_JD1_IN4P_EN … #define RT5645_JD2_IN4N_MASK … #define RT5645_JD2_IN4N_SFT … #define RT5645_JD2_IN4N_DIS … #define RT5645_JD2_IN4N_EN … /* Jack detect for ANC (0xbc) */ #define RT5645_ANC_DET_MASK … #define RT5645_ANC_DET_SFT … #define RT5645_ANC_DET_DIS … #define RT5645_ANC_DET_MB1 … #define RT5645_ANC_DET_MB2 … #define RT5645_ANC_DET_JD … #define RT5645_AD_TRG_MASK … #define RT5645_AD_TRG_SFT … #define RT5645_AD_TRG_LO … #define RT5645_AD_TRG_HI … #define RT5645_ANCM_DET_MASK … #define RT5645_ANCM_DET_SFT … #define RT5645_ANCM_DET_DIS … #define RT5645_ANCM_DET_MB1 … #define RT5645_ANCM_DET_MB2 … #define RT5645_ANCM_DET_JD … #define RT5645_AMD_TRG_MASK … #define RT5645_AMD_TRG_SFT … #define RT5645_AMD_TRG_LO … #define RT5645_AMD_TRG_HI … /* IRQ Control 1 (0xbd) */ #define RT5645_IRQ_JD_MASK … #define RT5645_IRQ_JD_SFT … #define RT5645_IRQ_JD_BP … #define RT5645_IRQ_JD_NOR … #define RT5645_IRQ_OT_MASK … #define RT5645_IRQ_OT_SFT … #define RT5645_IRQ_OT_BP … #define RT5645_IRQ_OT_NOR … #define RT5645_JD_STKY_MASK … #define RT5645_JD_STKY_SFT … #define RT5645_JD_STKY_DIS … #define RT5645_JD_STKY_EN … #define RT5645_OT_STKY_MASK … #define RT5645_OT_STKY_SFT … #define RT5645_OT_STKY_DIS … #define RT5645_OT_STKY_EN … #define RT5645_JD_P_MASK … #define RT5645_JD_P_SFT … #define RT5645_JD_P_NOR … #define RT5645_JD_P_INV … #define RT5645_OT_P_MASK … #define RT5645_OT_P_SFT … #define RT5645_OT_P_NOR … #define RT5645_OT_P_INV … #define RT5645_IRQ_JD_1_1_EN … #define RT5645_JD_1_1_MASK … #define RT5645_JD_1_1_SFT … #define RT5645_JD_1_1_NOR … #define RT5645_JD_1_1_INV … /* IRQ Control 2 (0xbe) */ #define RT5645_IRQ_MB1_OC_MASK … #define RT5645_IRQ_MB1_OC_SFT … #define RT5645_IRQ_MB1_OC_BP … #define RT5645_IRQ_MB1_OC_NOR … #define RT5645_IRQ_MB2_OC_MASK … #define RT5645_IRQ_MB2_OC_SFT … #define RT5645_IRQ_MB2_OC_BP … #define RT5645_IRQ_MB2_OC_NOR … #define RT5645_MB1_OC_STKY_MASK … #define RT5645_MB1_OC_STKY_SFT … #define RT5645_MB1_OC_STKY_DIS … #define RT5645_MB1_OC_STKY_EN … #define RT5645_MB2_OC_STKY_MASK … #define RT5645_MB2_OC_STKY_SFT … #define RT5645_MB2_OC_STKY_DIS … #define RT5645_MB2_OC_STKY_EN … #define RT5645_MB1_OC_P_MASK … #define RT5645_MB1_OC_P_SFT … #define RT5645_MB1_OC_P_NOR … #define RT5645_MB1_OC_P_INV … #define RT5645_MB2_OC_P_MASK … #define RT5645_MB2_OC_P_SFT … #define RT5645_MB2_OC_P_NOR … #define RT5645_MB2_OC_P_INV … #define RT5645_MB1_OC_CLR … #define RT5645_MB1_OC_CLR_SFT … #define RT5645_MB2_OC_CLR … #define RT5645_MB2_OC_CLR_SFT … /* GPIO Control 1 (0xc0) */ #define RT5645_GP1_PIN_MASK … #define RT5645_GP1_PIN_SFT … #define RT5645_GP1_PIN_GPIO1 … #define RT5645_GP1_PIN_IRQ … #define RT5645_GP2_PIN_MASK … #define RT5645_GP2_PIN_SFT … #define RT5645_GP2_PIN_GPIO2 … #define RT5645_GP2_PIN_DMIC1_SCL … #define RT5645_GP3_PIN_MASK … #define RT5645_GP3_PIN_SFT … #define RT5645_GP3_PIN_GPIO3 … #define RT5645_GP3_PIN_DMIC1_SDA … #define RT5645_GP3_PIN_IRQ … #define RT5645_GP4_PIN_MASK … #define RT5645_GP4_PIN_SFT … #define RT5645_GP4_PIN_GPIO4 … #define RT5645_GP4_PIN_DMIC2_SDA … #define RT5645_DP_SIG_MASK … #define RT5645_DP_SIG_SFT … #define RT5645_DP_SIG_TEST … #define RT5645_DP_SIG_AP … #define RT5645_GPIO_M_MASK … #define RT5645_GPIO_M_SFT … #define RT5645_GPIO_M_FLT … #define RT5645_GPIO_M_PH … #define RT5645_I2S2_SEL … #define RT5645_I2S2_SEL_SFT … #define RT5645_GP5_PIN_MASK … #define RT5645_GP5_PIN_SFT … #define RT5645_GP5_PIN_GPIO5 … #define RT5645_GP5_PIN_DMIC1_SDA … #define RT5645_GP6_PIN_MASK … #define RT5645_GP6_PIN_SFT … #define RT5645_GP6_PIN_GPIO6 … #define RT5645_GP6_PIN_DMIC2_SDA … #define RT5645_I2S2_DAC_PIN_MASK … #define RT5645_I2S2_DAC_PIN_SFT … #define RT5645_I2S2_DAC_PIN_I2S … #define RT5645_I2S2_DAC_PIN_GPIO … #define RT5645_GP8_PIN_MASK … #define RT5645_GP8_PIN_SFT … #define RT5645_GP8_PIN_GPIO8 … #define RT5645_GP8_PIN_DMIC2_SDA … #define RT5645_GP12_PIN_MASK … #define RT5645_GP12_PIN_SFT … #define RT5645_GP12_PIN_GPIO12 … #define RT5645_GP12_PIN_DMIC2_SDA … #define RT5645_GP11_PIN_MASK … #define RT5645_GP11_PIN_SFT … #define RT5645_GP11_PIN_GPIO11 … #define RT5645_GP11_PIN_DMIC1_SDA … #define RT5645_GP10_PIN_MASK … #define RT5645_GP10_PIN_SFT … #define RT5645_GP10_PIN_GPIO10 … #define RT5645_GP10_PIN_DMIC2_SDA … /* GPIO Control 3 (0xc2) */ #define RT5645_GP4_PF_MASK … #define RT5645_GP4_PF_SFT … #define RT5645_GP4_PF_IN … #define RT5645_GP4_PF_OUT … #define RT5645_GP4_OUT_MASK … #define RT5645_GP4_OUT_SFT … #define RT5645_GP4_OUT_LO … #define RT5645_GP4_OUT_HI … #define RT5645_GP4_P_MASK … #define RT5645_GP4_P_SFT … #define RT5645_GP4_P_NOR … #define RT5645_GP4_P_INV … #define RT5645_GP3_PF_MASK … #define RT5645_GP3_PF_SFT … #define RT5645_GP3_PF_IN … #define RT5645_GP3_PF_OUT … #define RT5645_GP3_OUT_MASK … #define RT5645_GP3_OUT_SFT … #define RT5645_GP3_OUT_LO … #define RT5645_GP3_OUT_HI … #define RT5645_GP3_P_MASK … #define RT5645_GP3_P_SFT … #define RT5645_GP3_P_NOR … #define RT5645_GP3_P_INV … #define RT5645_GP2_PF_MASK … #define RT5645_GP2_PF_SFT … #define RT5645_GP2_PF_IN … #define RT5645_GP2_PF_OUT … #define RT5645_GP2_OUT_MASK … #define RT5645_GP2_OUT_SFT … #define RT5645_GP2_OUT_LO … #define RT5645_GP2_OUT_HI … #define RT5645_GP2_P_MASK … #define RT5645_GP2_P_SFT … #define RT5645_GP2_P_NOR … #define RT5645_GP2_P_INV … #define RT5645_GP1_PF_MASK … #define RT5645_GP1_PF_SFT … #define RT5645_GP1_PF_IN … #define RT5645_GP1_PF_OUT … #define RT5645_GP1_OUT_MASK … #define RT5645_GP1_OUT_SFT … #define RT5645_GP1_OUT_LO … #define RT5645_GP1_OUT_HI … #define RT5645_GP1_P_MASK … #define RT5645_GP1_P_SFT … #define RT5645_GP1_P_NOR … #define RT5645_GP1_P_INV … /* Programmable Register Array Control 1 (0xc8) */ #define RT5645_REG_SEQ_MASK … #define RT5645_REG_SEQ_SFT … #define RT5645_SEQ1_ST_MASK … #define RT5645_SEQ1_ST_SFT … #define RT5645_SEQ1_ST_RUN … #define RT5645_SEQ1_ST_FIN … #define RT5645_SEQ2_ST_MASK … #define RT5645_SEQ2_ST_SFT … #define RT5645_SEQ2_ST_RUN … #define RT5645_SEQ2_ST_FIN … #define RT5645_REG_LV_MASK … #define RT5645_REG_LV_SFT … #define RT5645_REG_LV_MX … #define RT5645_REG_LV_PR … #define RT5645_SEQ_2_PT_MASK … #define RT5645_SEQ_2_PT_BIT … #define RT5645_REG_IDX_MASK … #define RT5645_REG_IDX_SFT … /* Programmable Register Array Control 2 (0xc9) */ #define RT5645_REG_DAT_MASK … #define RT5645_REG_DAT_SFT … /* Programmable Register Array Control 3 (0xca) */ #define RT5645_SEQ_DLY_MASK … #define RT5645_SEQ_DLY_SFT … #define RT5645_PROG_MASK … #define RT5645_PROG_SFT … #define RT5645_PROG_DIS … #define RT5645_PROG_EN … #define RT5645_SEQ1_PT_RUN … #define RT5645_SEQ1_PT_RUN_BIT … #define RT5645_SEQ2_PT_RUN … #define RT5645_SEQ2_PT_RUN_BIT … /* Programmable Register Array Control 4 (0xcb) */ #define RT5645_SEQ1_START_MASK … #define RT5645_SEQ1_START_SFT … #define RT5645_SEQ1_END_MASK … #define RT5645_SEQ1_END_SFT … /* Programmable Register Array Control 5 (0xcc) */ #define RT5645_SEQ2_START_MASK … #define RT5645_SEQ2_START_SFT … #define RT5645_SEQ2_END_MASK … #define RT5645_SEQ2_END_SFT … /* Scramble Function (0xcd) */ #define RT5645_SCB_KEY_MASK … #define RT5645_SCB_KEY_SFT … /* Scramble Control (0xce) */ #define RT5645_SCB_SWAP_MASK … #define RT5645_SCB_SWAP_SFT … #define RT5645_SCB_SWAP_DIS … #define RT5645_SCB_SWAP_EN … #define RT5645_SCB_MASK … #define RT5645_SCB_SFT … #define RT5645_SCB_DIS … #define RT5645_SCB_EN … /* Baseback Control (0xcf) */ #define RT5645_BB_MASK … #define RT5645_BB_SFT … #define RT5645_BB_DIS … #define RT5645_BB_EN … #define RT5645_BB_CT_MASK … #define RT5645_BB_CT_SFT … #define RT5645_BB_CT_A … #define RT5645_BB_CT_B … #define RT5645_BB_CT_C … #define RT5645_BB_CT_D … #define RT5645_M_BB_L_MASK … #define RT5645_M_BB_L_SFT … #define RT5645_M_BB_R_MASK … #define RT5645_M_BB_R_SFT … #define RT5645_M_BB_HPF_L_MASK … #define RT5645_M_BB_HPF_L_SFT … #define RT5645_M_BB_HPF_R_MASK … #define RT5645_M_BB_HPF_R_SFT … #define RT5645_G_BB_BST_MASK … #define RT5645_G_BB_BST_SFT … #define RT5645_G_BB_BST_25DB … /* MP3 Plus Control 1 (0xd0) */ #define RT5645_M_MP3_L_MASK … #define RT5645_M_MP3_L_SFT … #define RT5645_M_MP3_R_MASK … #define RT5645_M_MP3_R_SFT … #define RT5645_M_MP3_MASK … #define RT5645_M_MP3_SFT … #define RT5645_M_MP3_DIS … #define RT5645_M_MP3_EN … #define RT5645_EG_MP3_MASK … #define RT5645_EG_MP3_SFT … #define RT5645_MP3_HLP_MASK … #define RT5645_MP3_HLP_SFT … #define RT5645_MP3_HLP_DIS … #define RT5645_MP3_HLP_EN … #define RT5645_M_MP3_ORG_L_MASK … #define RT5645_M_MP3_ORG_L_SFT … #define RT5645_M_MP3_ORG_R_MASK … #define RT5645_M_MP3_ORG_R_SFT … /* MP3 Plus Control 2 (0xd1) */ #define RT5645_MP3_WT_MASK … #define RT5645_MP3_WT_SFT … #define RT5645_MP3_WT_1_4 … #define RT5645_MP3_WT_1_2 … #define RT5645_OG_MP3_MASK … #define RT5645_OG_MP3_SFT … #define RT5645_HG_MP3_MASK … #define RT5645_HG_MP3_SFT … /* 3D HP Control 1 (0xd2) */ #define RT5645_3D_CF_MASK … #define RT5645_3D_CF_SFT … #define RT5645_3D_CF_DIS … #define RT5645_3D_CF_EN … #define RT5645_3D_HP_MASK … #define RT5645_3D_HP_SFT … #define RT5645_3D_HP_DIS … #define RT5645_3D_HP_EN … #define RT5645_3D_BT_MASK … #define RT5645_3D_BT_SFT … #define RT5645_3D_BT_DIS … #define RT5645_3D_BT_EN … #define RT5645_3D_1F_MIX_MASK … #define RT5645_3D_1F_MIX_SFT … #define RT5645_3D_HP_M_MASK … #define RT5645_3D_HP_M_SFT … #define RT5645_3D_HP_M_SUR … #define RT5645_3D_HP_M_FRO … #define RT5645_M_3D_HRTF_MASK … #define RT5645_M_3D_HRTF_SFT … #define RT5645_M_3D_D2H_MASK … #define RT5645_M_3D_D2H_SFT … #define RT5645_M_3D_D2R_MASK … #define RT5645_M_3D_D2R_SFT … #define RT5645_M_3D_REVB_MASK … #define RT5645_M_3D_REVB_SFT … /* Adjustable high pass filter control 1 (0xd3) */ #define RT5645_2ND_HPF_MASK … #define RT5645_2ND_HPF_SFT … #define RT5645_2ND_HPF_DIS … #define RT5645_2ND_HPF_EN … #define RT5645_HPF_CF_L_MASK … #define RT5645_HPF_CF_L_SFT … #define RT5645_1ST_HPF_MASK … #define RT5645_1ST_HPF_SFT … #define RT5645_1ST_HPF_DIS … #define RT5645_1ST_HPF_EN … #define RT5645_HPF_CF_R_MASK … #define RT5645_HPF_CF_R_SFT … #define RT5645_ZD_T_MASK … #define RT5645_ZD_T_SFT … #define RT5645_ZD_F_MASK … #define RT5645_ZD_F_SFT … #define RT5645_ZD_F_IM … #define RT5645_ZD_F_ZC_IM … #define RT5645_ZD_F_ZC_IOD … #define RT5645_ZD_F_UN … /* HP calibration control and Amp detection (0xd6) */ #define RT5645_SI_DAC_MASK … #define RT5645_SI_DAC_SFT … #define RT5645_SI_DAC_AUTO … #define RT5645_SI_DAC_TEST … #define RT5645_DC_CAL_M_MASK … #define RT5645_DC_CAL_M_SFT … #define RT5645_DC_CAL_M_CAL … #define RT5645_DC_CAL_M_NOR … #define RT5645_DC_CAL_MASK … #define RT5645_DC_CAL_SFT … #define RT5645_DC_CAL_DIS … #define RT5645_DC_CAL_EN … #define RT5645_HPD_RCV_MASK … #define RT5645_HPD_RCV_SFT … #define RT5645_HPD_PS_MASK … #define RT5645_HPD_PS_SFT … #define RT5645_HPD_PS_DIS … #define RT5645_HPD_PS_EN … #define RT5645_CAL_M_MASK … #define RT5645_CAL_M_SFT … #define RT5645_CAL_M_DEP … #define RT5645_CAL_M_CAL … #define RT5645_CAL_MASK … #define RT5645_CAL_SFT … #define RT5645_CAL_DIS … #define RT5645_CAL_EN … #define RT5645_CAL_TEST_MASK … #define RT5645_CAL_TEST_SFT … #define RT5645_CAL_TEST_DIS … #define RT5645_CAL_TEST_EN … #define RT5645_CAL_P_MASK … #define RT5645_CAL_P_SFT … #define RT5645_CAL_P_NONE … #define RT5645_CAL_P_CAL … #define RT5645_CAL_P_DAC_CAL … /* Soft volume and zero cross control 1 (0xd9) */ #define RT5645_SV_MASK … #define RT5645_SV_SFT … #define RT5645_SV_DIS … #define RT5645_SV_EN … #define RT5645_SPO_SV_MASK … #define RT5645_SPO_SV_SFT … #define RT5645_SPO_SV_DIS … #define RT5645_SPO_SV_EN … #define RT5645_OUT_SV_MASK … #define RT5645_OUT_SV_SFT … #define RT5645_OUT_SV_DIS … #define RT5645_OUT_SV_EN … #define RT5645_HP_SV_MASK … #define RT5645_HP_SV_SFT … #define RT5645_HP_SV_DIS … #define RT5645_HP_SV_EN … #define RT5645_ZCD_DIG_MASK … #define RT5645_ZCD_DIG_SFT … #define RT5645_ZCD_DIG_DIS … #define RT5645_ZCD_DIG_EN … #define RT5645_ZCD_MASK … #define RT5645_ZCD_SFT … #define RT5645_ZCD_PD … #define RT5645_ZCD_PU … #define RT5645_M_ZCD_MASK … #define RT5645_M_ZCD_SFT … #define RT5645_M_ZCD_RM_L … #define RT5645_M_ZCD_RM_R … #define RT5645_M_ZCD_SM_L … #define RT5645_M_ZCD_SM_R … #define RT5645_M_ZCD_OM_L … #define RT5645_M_ZCD_OM_R … #define RT5645_SV_DLY_MASK … #define RT5645_SV_DLY_SFT … /* Soft volume and zero cross control 2 (0xda) */ #define RT5645_ZCD_HP_MASK … #define RT5645_ZCD_HP_SFT … #define RT5645_ZCD_HP_DIS … #define RT5645_ZCD_HP_EN … /* Buttons Inline Command Function 2 (0xe0) */ #define RT5645_EN_4BTN_IL_MASK … #define RT5645_EN_4BTN_IL_EN … #define RT5645_RST_4BTN_IL_MASK … #define RT5645_RST_4BTN_IL_RST … #define RT5645_RST_4BTN_IL_NORM … /* Codec Private Register definition */ /* DAC ADC Digital Volume (0x00) */ #define RT5645_DA1_ZDET_SFT … /* 3D Speaker Control (0x63) */ #define RT5645_3D_SPK_MASK … #define RT5645_3D_SPK_SFT … #define RT5645_3D_SPK_DIS … #define RT5645_3D_SPK_EN … #define RT5645_3D_SPK_M_MASK … #define RT5645_3D_SPK_M_SFT … #define RT5645_3D_SPK_CG_MASK … #define RT5645_3D_SPK_CG_SFT … #define RT5645_3D_SPK_SG_MASK … #define RT5645_3D_SPK_SG_SFT … /* Wind Noise Detection Control 1 (0x6c) */ #define RT5645_WND_MASK … #define RT5645_WND_SFT … #define RT5645_WND_DIS … #define RT5645_WND_EN … /* Wind Noise Detection Control 2 (0x6d) */ #define RT5645_WND_FC_NW_MASK … #define RT5645_WND_FC_NW_SFT … #define RT5645_WND_FC_WK_MASK … #define RT5645_WND_FC_WK_SFT … /* Wind Noise Detection Control 3 (0x6e) */ #define RT5645_HPF_FC_MASK … #define RT5645_HPF_FC_SFT … #define RT5645_WND_FC_ST_MASK … #define RT5645_WND_FC_ST_SFT … /* Wind Noise Detection Control 4 (0x6f) */ #define RT5645_WND_TH_LO_MASK … #define RT5645_WND_TH_LO_SFT … /* Wind Noise Detection Control 5 (0x70) */ #define RT5645_WND_TH_HI_MASK … #define RT5645_WND_TH_HI_SFT … /* Wind Noise Detection Control 8 (0x73) */ #define RT5645_WND_WIND_MASK … #define RT5645_WND_WIND_SFT … #define RT5645_WND_STRONG_MASK … #define RT5645_WND_STRONG_SFT … enum { … }; /* Dipole Speaker Interface (0x75) */ #define RT5645_DP_ATT_MASK … #define RT5645_DP_ATT_SFT … #define RT5645_DP_SPK_MASK … #define RT5645_DP_SPK_SFT … #define RT5645_DP_SPK_DIS … #define RT5645_DP_SPK_EN … /* EQ Pre Volume Control (0xb3) */ #define RT5645_EQ_PRE_VOL_MASK … #define RT5645_EQ_PRE_VOL_SFT … /* EQ Post Volume Control (0xb4) */ #define RT5645_EQ_PST_VOL_MASK … #define RT5645_EQ_PST_VOL_SFT … /* Jack Detect Control 3 (0xf8) */ #define RT5645_CMP_MIC_IN_DET_MASK … #define RT5645_JD_CBJ_EN … #define RT5645_JD_CBJ_POL … #define RT5645_JD_TRI_CBJ_SEL_MASK … #define RT5645_JD_TRI_CBJ_SEL_SFT … #define RT5645_JD_TRI_HPO_SEL_MASK … #define RT5645_JD_TRI_HPO_SEL_SFT … #define RT5645_JD_F_GPIO_JD1 … #define RT5645_JD_F_JD1_1 … #define RT5645_JD_F_JD1_2 … #define RT5645_JD_F_JD2 … #define RT5645_JD_F_JD3 … #define RT5645_JD_F_GPIO_JD2 … #define RT5645_JD_F_MX0B_12 … /* Digital Misc Control (0xfa) */ #define RT5645_RST_DSP … #define RT5645_IF1_ADC1_IN1_SEL … #define RT5645_IF1_ADC1_IN1_SFT … #define RT5645_IF1_ADC1_IN2_SEL … #define RT5645_IF1_ADC1_IN2_SFT … #define RT5645_IF1_ADC2_IN1_SEL … #define RT5645_IF1_ADC2_IN1_SFT … #define RT5645_DIG_GATE_CTRL … /* General Control2 (0xfb) */ #define RT5645_RXDC_SRC_MASK … #define RT5645_RXDC_SRC_STO … #define RT5645_RXDC_SRC_MONO … #define RT5645_RXDC_SRC_SFT … #define RT5645_MICBIAS1_POW_CTRL_SEL_MASK … #define RT5645_MICBIAS1_POW_CTRL_SEL_A … #define RT5645_MICBIAS1_POW_CTRL_SEL_M … #define RT5645_MICBIAS2_POW_CTRL_SEL_MASK … #define RT5645_MICBIAS2_POW_CTRL_SEL_A … #define RT5645_MICBIAS2_POW_CTRL_SEL_M … #define RT5645_RXDP2_SEL_MASK … #define RT5645_RXDP2_SEL_IF2 … #define RT5645_RXDP2_SEL_ADC … #define RT5645_RXDP2_SEL_SFT … /* General Control3 (0xfc) */ #define RT5645_JD_PSV_MODE … #define RT5645_IRQ_CLK_GATE_CTRL … #define RT5645_DET_CLK_MASK … #define RT5645_DET_CLK_DIS … #define RT5645_DET_CLK_MODE1 … #define RT5645_DET_CLK_MODE2 … #define RT5645_MICINDET_MANU … #define RT5645_RING2_SLEEVE_GND … /* Vendor ID (0xfd) */ #define RT5645_VER_C … #define RT5645_VER_D … /* Volume Rescale */ #define RT5645_VOL_RSCL_MAX … #define RT5645_VOL_RSCL_RANGE … /* Debug String Length */ #define RT5645_REG_DISP_LEN … /* System Clock Source */ enum { … }; /* PLL1 Source */ enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; /* filter mask */ enum { … }; int rt5645_sel_asrc_clk_src(struct snd_soc_component *component, unsigned int filter_mask, unsigned int clk_src); int rt5645_set_jack_detect(struct snd_soc_component *component, struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, struct snd_soc_jack *btn_jack); const char *rt5645_components(struct device *codec_dev); #endif /* __RT5645_H__ */
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