/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt5651.h -- RT5651 ALSA SoC audio driver * * Copyright 2011 Realtek Microelectronics * Author: Johnny Hsu <[email protected]> */ #ifndef __RT5651_H__ #define __RT5651_H__ #include <dt-bindings/sound/rt5651.h> /* Info */ #define RT5651_RESET … #define RT5651_VERSION_ID … #define RT5651_VENDOR_ID … #define RT5651_DEVICE_ID … /* I/O - Output */ #define RT5651_HP_VOL … #define RT5651_LOUT_CTRL1 … #define RT5651_LOUT_CTRL2 … /* I/O - Input */ #define RT5651_IN1_IN2 … #define RT5651_IN3 … #define RT5651_INL1_INR1_VOL … #define RT5651_INL2_INR2_VOL … /* I/O - ADC/DAC/DMIC */ #define RT5651_DAC1_DIG_VOL … #define RT5651_DAC2_DIG_VOL … #define RT5651_DAC2_CTRL … #define RT5651_ADC_DIG_VOL … #define RT5651_ADC_DATA … #define RT5651_ADC_BST_VOL … /* Mixer - D-D */ #define RT5651_STO1_ADC_MIXER … #define RT5651_STO2_ADC_MIXER … #define RT5651_AD_DA_MIXER … #define RT5651_STO_DAC_MIXER … #define RT5651_DD_MIXER … #define RT5651_DIG_INF_DATA … /* PDM */ #define RT5651_PDM_CTL … #define RT5651_PDM_I2C_CTL1 … #define RT5651_PDM_I2C_CTL2 … #define RT5651_PDM_I2C_DATA_W … #define RT5651_PDM_I2C_DATA_R … /* Mixer - ADC */ #define RT5651_REC_L1_MIXER … #define RT5651_REC_L2_MIXER … #define RT5651_REC_R1_MIXER … #define RT5651_REC_R2_MIXER … /* Mixer - DAC */ #define RT5651_HPO_MIXER … #define RT5651_OUT_L1_MIXER … #define RT5651_OUT_L2_MIXER … #define RT5651_OUT_L3_MIXER … #define RT5651_OUT_R1_MIXER … #define RT5651_OUT_R2_MIXER … #define RT5651_OUT_R3_MIXER … #define RT5651_LOUT_MIXER … /* Power */ #define RT5651_PWR_DIG1 … #define RT5651_PWR_DIG2 … #define RT5651_PWR_ANLG1 … #define RT5651_PWR_ANLG2 … #define RT5651_PWR_MIXER … #define RT5651_PWR_VOL … /* Private Register Control */ #define RT5651_PRIV_INDEX … #define RT5651_PRIV_DATA … /* Format - ADC/DAC */ #define RT5651_I2S1_SDP … #define RT5651_I2S2_SDP … #define RT5651_ADDA_CLK1 … #define RT5651_ADDA_CLK2 … #define RT5651_DMIC … /* TDM Control */ #define RT5651_TDM_CTL_1 … #define RT5651_TDM_CTL_2 … #define RT5651_TDM_CTL_3 … /* Function - Analog */ #define RT5651_GLB_CLK … #define RT5651_PLL_CTRL1 … #define RT5651_PLL_CTRL2 … #define RT5651_PLL_MODE_1 … #define RT5651_PLL_MODE_2 … #define RT5651_PLL_MODE_3 … #define RT5651_PLL_MODE_4 … #define RT5651_PLL_MODE_5 … #define RT5651_PLL_MODE_6 … #define RT5651_PLL_MODE_7 … #define RT5651_DEPOP_M1 … #define RT5651_DEPOP_M2 … #define RT5651_DEPOP_M3 … #define RT5651_CHARGE_PUMP … #define RT5651_MICBIAS … #define RT5651_A_JD_CTL1 … /* Function - Digital */ #define RT5651_EQ_CTRL1 … #define RT5651_EQ_CTRL2 … #define RT5651_ALC_1 … #define RT5651_ALC_2 … #define RT5651_ALC_3 … #define RT5651_JD_CTRL1 … #define RT5651_JD_CTRL2 … #define RT5651_IRQ_CTRL1 … #define RT5651_IRQ_CTRL2 … #define RT5651_INT_IRQ_ST … #define RT5651_GPIO_CTRL1 … #define RT5651_GPIO_CTRL2 … #define RT5651_GPIO_CTRL3 … #define RT5651_PGM_REG_ARR1 … #define RT5651_PGM_REG_ARR2 … #define RT5651_PGM_REG_ARR3 … #define RT5651_PGM_REG_ARR4 … #define RT5651_PGM_REG_ARR5 … #define RT5651_SCB_FUNC … #define RT5651_SCB_CTRL … #define RT5651_BASE_BACK … #define RT5651_MP3_PLUS1 … #define RT5651_MP3_PLUS2 … #define RT5651_ADJ_HPF_CTRL1 … #define RT5651_ADJ_HPF_CTRL2 … #define RT5651_HP_CALIB_AMP_DET … #define RT5651_HP_CALIB2 … #define RT5651_SV_ZCD1 … #define RT5651_SV_ZCD2 … #define RT5651_D_MISC … /* Dummy Register */ #define RT5651_DUMMY2 … #define RT5651_DUMMY3 … /* Index of Codec Private Register definition */ #define RT5651_BIAS_CUR1 … #define RT5651_BIAS_CUR3 … #define RT5651_BIAS_CUR4 … #define RT5651_CLSD_INT_REG1 … #define RT5651_CHPUMP_INT_REG1 … #define RT5651_MAMP_INT_REG2 … #define RT5651_CHOP_DAC_ADC … #define RT5651_3D_SPK … #define RT5651_WND_1 … #define RT5651_WND_2 … #define RT5651_WND_3 … #define RT5651_WND_4 … #define RT5651_WND_5 … #define RT5651_WND_8 … #define RT5651_DIP_SPK_INF … #define RT5651_HP_DCC_INT1 … #define RT5651_EQ_BW_LOP … #define RT5651_EQ_GN_LOP … #define RT5651_EQ_FC_BP1 … #define RT5651_EQ_BW_BP1 … #define RT5651_EQ_GN_BP1 … #define RT5651_EQ_FC_BP2 … #define RT5651_EQ_BW_BP2 … #define RT5651_EQ_GN_BP2 … #define RT5651_EQ_FC_BP3 … #define RT5651_EQ_BW_BP3 … #define RT5651_EQ_GN_BP3 … #define RT5651_EQ_FC_BP4 … #define RT5651_EQ_BW_BP4 … #define RT5651_EQ_GN_BP4 … #define RT5651_EQ_FC_HIP1 … #define RT5651_EQ_GN_HIP1 … #define RT5651_EQ_FC_HIP2 … #define RT5651_EQ_BW_HIP2 … #define RT5651_EQ_GN_HIP2 … #define RT5651_EQ_PRE_VOL … #define RT5651_EQ_PST_VOL … /* global definition */ #define RT5651_L_MUTE … #define RT5651_L_MUTE_SFT … #define RT5651_VOL_L_MUTE … #define RT5651_VOL_L_SFT … #define RT5651_R_MUTE … #define RT5651_R_MUTE_SFT … #define RT5651_VOL_R_MUTE … #define RT5651_VOL_R_SFT … #define RT5651_L_VOL_MASK … #define RT5651_L_VOL_SFT … #define RT5651_R_VOL_MASK … #define RT5651_R_VOL_SFT … /* LOUT Control 2(0x05) */ #define RT5651_EN_DFO … /* IN1 and IN2 Control (0x0d) */ /* IN3 and IN4 Control (0x0e) */ #define RT5651_BST_MASK1 … #define RT5651_BST_SFT1 … #define RT5651_BST_MASK2 … #define RT5651_BST_SFT2 … #define RT5651_IN_DF1 … #define RT5651_IN_SFT1 … #define RT5651_IN_DF2 … #define RT5651_IN_SFT2 … /* INL1 and INR1 Volume Control (0x0f) */ /* INL2 and INR2 Volume Control (0x10) */ #define RT5651_INL_SEL_MASK … #define RT5651_INL_SEL_SFT … #define RT5651_INL_SEL_IN4P … #define RT5651_INL_SEL_MONOP … #define RT5651_INL_VOL_MASK … #define RT5651_INL_VOL_SFT … #define RT5651_INR_SEL_MASK … #define RT5651_INR_SEL_SFT … #define RT5651_INR_SEL_IN4N … #define RT5651_INR_SEL_MONON … #define RT5651_INR_VOL_MASK … #define RT5651_INR_VOL_SFT … /* DAC1 Digital Volume (0x19) */ #define RT5651_DAC_L1_VOL_MASK … #define RT5651_DAC_L1_VOL_SFT … #define RT5651_DAC_R1_VOL_MASK … #define RT5651_DAC_R1_VOL_SFT … /* DAC2 Digital Volume (0x1a) */ #define RT5651_DAC_L2_VOL_MASK … #define RT5651_DAC_L2_VOL_SFT … #define RT5651_DAC_R2_VOL_MASK … #define RT5651_DAC_R2_VOL_SFT … /* DAC2 Control (0x1b) */ #define RT5651_M_DAC_L2_VOL … #define RT5651_M_DAC_L2_VOL_SFT … #define RT5651_M_DAC_R2_VOL … #define RT5651_M_DAC_R2_VOL_SFT … #define RT5651_SEL_DAC_L2 … #define RT5651_IF2_DAC_L2 … #define RT5651_IF1_DAC_L2 … #define RT5651_SEL_DAC_L2_SFT … #define RT5651_SEL_DAC_R2 … #define RT5651_IF2_DAC_R2 … #define RT5651_IF1_DAC_R2 … #define RT5651_SEL_DAC_R2_SFT … /* ADC Digital Volume Control (0x1c) */ #define RT5651_ADC_L_VOL_MASK … #define RT5651_ADC_L_VOL_SFT … #define RT5651_ADC_R_VOL_MASK … #define RT5651_ADC_R_VOL_SFT … /* Mono ADC Digital Volume Control (0x1d) */ #define RT5651_M_MONO_ADC_L … #define RT5651_M_MONO_ADC_L_SFT … #define RT5651_MONO_ADC_L_VOL_MASK … #define RT5651_MONO_ADC_L_VOL_SFT … #define RT5651_M_MONO_ADC_R … #define RT5651_M_MONO_ADC_R_SFT … #define RT5651_MONO_ADC_R_VOL_MASK … #define RT5651_MONO_ADC_R_VOL_SFT … /* ADC Boost Volume Control (0x1e) */ #define RT5651_ADC_L_BST_MASK … #define RT5651_ADC_L_BST_SFT … #define RT5651_ADC_R_BST_MASK … #define RT5651_ADC_R_BST_SFT … #define RT5651_ADC_COMP_MASK … #define RT5651_ADC_COMP_SFT … /* Stereo ADC1 Mixer Control (0x27) */ #define RT5651_M_STO1_ADC_L1 … #define RT5651_M_STO1_ADC_L1_SFT … #define RT5651_M_STO1_ADC_L2 … #define RT5651_M_STO1_ADC_L2_SFT … #define RT5651_STO1_ADC_1_SRC_MASK … #define RT5651_STO1_ADC_1_SRC_SFT … #define RT5651_STO1_ADC_1_SRC_ADC … #define RT5651_STO1_ADC_1_SRC_DACMIX … #define RT5651_STO1_ADC_2_SRC_MASK … #define RT5651_STO1_ADC_2_SRC_SFT … #define RT5651_STO1_ADC_2_SRC_DMIC … #define RT5651_STO1_ADC_2_SRC_DACMIXR … #define RT5651_M_STO1_ADC_R1 … #define RT5651_M_STO1_ADC_R1_SFT … #define RT5651_M_STO1_ADC_R2 … #define RT5651_M_STO1_ADC_R2_SFT … /* Stereo ADC2 Mixer Control (0x28) */ #define RT5651_M_STO2_ADC_L1 … #define RT5651_M_STO2_ADC_L1_SFT … #define RT5651_M_STO2_ADC_L2 … #define RT5651_M_STO2_ADC_L2_SFT … #define RT5651_STO2_ADC_L1_SRC_MASK … #define RT5651_STO2_ADC_L1_SRC_SFT … #define RT5651_STO2_ADC_L1_SRC_DACMIXL … #define RT5651_STO2_ADC_L1_SRC_ADCL … #define RT5651_STO2_ADC_L2_SRC_MASK … #define RT5651_STO2_ADC_L2_SRC_SFT … #define RT5651_STO2_ADC_L2_SRC_DMIC … #define RT5651_STO2_ADC_L2_SRC_DACMIXR … #define RT5651_M_STO2_ADC_R1 … #define RT5651_M_STO2_ADC_R1_SFT … #define RT5651_M_STO2_ADC_R2 … #define RT5651_M_STO2_ADC_R2_SFT … #define RT5651_STO2_ADC_R1_SRC_MASK … #define RT5651_STO2_ADC_R1_SRC_SFT … #define RT5651_STO2_ADC_R1_SRC_ADCR … #define RT5651_STO2_ADC_R1_SRC_DACMIXR … #define RT5651_STO2_ADC_R2_SRC_MASK … #define RT5651_STO2_ADC_R2_SRC_SFT … #define RT5651_STO2_ADC_R2_SRC_DMIC … #define RT5651_STO2_ADC_R2_SRC_DACMIXR … /* ADC Mixer to DAC Mixer Control (0x29) */ #define RT5651_M_ADCMIX_L … #define RT5651_M_ADCMIX_L_SFT … #define RT5651_M_IF1_DAC_L … #define RT5651_M_IF1_DAC_L_SFT … #define RT5651_M_ADCMIX_R … #define RT5651_M_ADCMIX_R_SFT … #define RT5651_M_IF1_DAC_R … #define RT5651_M_IF1_DAC_R_SFT … /* Stereo DAC Mixer Control (0x2a) */ #define RT5651_M_DAC_L1_MIXL … #define RT5651_M_DAC_L1_MIXL_SFT … #define RT5651_DAC_L1_STO_L_VOL_MASK … #define RT5651_DAC_L1_STO_L_VOL_SFT … #define RT5651_M_DAC_L2_MIXL … #define RT5651_M_DAC_L2_MIXL_SFT … #define RT5651_DAC_L2_STO_L_VOL_MASK … #define RT5651_DAC_L2_STO_L_VOL_SFT … #define RT5651_M_DAC_R1_MIXL … #define RT5651_M_DAC_R1_MIXL_SFT … #define RT5651_DAC_R1_STO_L_VOL_MASK … #define RT5651_DAC_R1_STO_L_VOL_SFT … #define RT5651_M_DAC_R1_MIXR … #define RT5651_M_DAC_R1_MIXR_SFT … #define RT5651_DAC_R1_STO_R_VOL_MASK … #define RT5651_DAC_R1_STO_R_VOL_SFT … #define RT5651_M_DAC_R2_MIXR … #define RT5651_M_DAC_R2_MIXR_SFT … #define RT5651_DAC_R2_STO_R_VOL_MASK … #define RT5651_DAC_R2_STO_R_VOL_SFT … #define RT5651_M_DAC_L1_MIXR … #define RT5651_M_DAC_L1_MIXR_SFT … #define RT5651_DAC_L1_STO_R_VOL_MASK … #define RT5651_DAC_L1_STO_R_VOL_SFT … /* DD Mixer Control (0x2b) */ #define RT5651_M_STO_DD_L1 … #define RT5651_M_STO_DD_L1_SFT … #define RT5651_STO_DD_L1_VOL_MASK … #define RT5651_DAC_DD_L1_VOL_SFT … #define RT5651_M_STO_DD_L2 … #define RT5651_M_STO_DD_L2_SFT … #define RT5651_STO_DD_L2_VOL_MASK … #define RT5651_STO_DD_L2_VOL_SFT … #define RT5651_M_STO_DD_R2_L … #define RT5651_M_STO_DD_R2_L_SFT … #define RT5651_STO_DD_R2_L_VOL_MASK … #define RT5651_STO_DD_R2_L_VOL_SFT … #define RT5651_M_STO_DD_R1 … #define RT5651_M_STO_DD_R1_SFT … #define RT5651_STO_DD_R1_VOL_MASK … #define RT5651_STO_DD_R1_VOL_SFT … #define RT5651_M_STO_DD_R2 … #define RT5651_M_STO_DD_R2_SFT … #define RT5651_STO_DD_R2_VOL_MASK … #define RT5651_STO_DD_R2_VOL_SFT … #define RT5651_M_STO_DD_L2_R … #define RT5651_M_STO_DD_L2_R_SFT … #define RT5651_STO_DD_L2_R_VOL_MASK … #define RT5651_STO_DD_L2_R_VOL_SFT … /* Digital Mixer Control (0x2c) */ #define RT5651_M_STO_L_DAC_L … #define RT5651_M_STO_L_DAC_L_SFT … #define RT5651_STO_L_DAC_L_VOL_MASK … #define RT5651_STO_L_DAC_L_VOL_SFT … #define RT5651_M_DAC_L2_DAC_L … #define RT5651_M_DAC_L2_DAC_L_SFT … #define RT5651_DAC_L2_DAC_L_VOL_MASK … #define RT5651_DAC_L2_DAC_L_VOL_SFT … #define RT5651_M_STO_R_DAC_R … #define RT5651_M_STO_R_DAC_R_SFT … #define RT5651_STO_R_DAC_R_VOL_MASK … #define RT5651_STO_R_DAC_R_VOL_SFT … #define RT5651_M_DAC_R2_DAC_R … #define RT5651_M_DAC_R2_DAC_R_SFT … #define RT5651_DAC_R2_DAC_R_VOL_MASK … #define RT5651_DAC_R2_DAC_R_VOL_SFT … /* DSP Path Control 1 (0x2d) */ #define RT5651_RXDP_SRC_MASK … #define RT5651_RXDP_SRC_SFT … #define RT5651_RXDP_SRC_NOR … #define RT5651_RXDP_SRC_DIV3 … #define RT5651_TXDP_SRC_MASK … #define RT5651_TXDP_SRC_SFT … #define RT5651_TXDP_SRC_NOR … #define RT5651_TXDP_SRC_DIV3 … /* DSP Path Control 2 (0x2e) */ #define RT5651_DAC_L2_SEL_MASK … #define RT5651_DAC_L2_SEL_SFT … #define RT5651_DAC_L2_SEL_IF2 … #define RT5651_DAC_L2_SEL_IF3 … #define RT5651_DAC_L2_SEL_TXDC … #define RT5651_DAC_L2_SEL_BASS … #define RT5651_DAC_R2_SEL_MASK … #define RT5651_DAC_R2_SEL_SFT … #define RT5651_DAC_R2_SEL_IF2 … #define RT5651_DAC_R2_SEL_IF3 … #define RT5651_DAC_R2_SEL_TXDC … #define RT5651_IF2_ADC_L_SEL_MASK … #define RT5651_IF2_ADC_L_SEL_SFT … #define RT5651_IF2_ADC_L_SEL_TXDP … #define RT5651_IF2_ADC_L_SEL_PASS … #define RT5651_IF2_ADC_R_SEL_MASK … #define RT5651_IF2_ADC_R_SEL_SFT … #define RT5651_IF2_ADC_R_SEL_TXDP … #define RT5651_IF2_ADC_R_SEL_PASS … #define RT5651_RXDC_SEL_MASK … #define RT5651_RXDC_SEL_SFT … #define RT5651_RXDC_SEL_NOR … #define RT5651_RXDC_SEL_L2R … #define RT5651_RXDC_SEL_R2L … #define RT5651_RXDC_SEL_SWAP … #define RT5651_RXDP_SEL_MASK … #define RT5651_RXDP_SEL_SFT … #define RT5651_RXDP_SEL_NOR … #define RT5651_RXDP_SEL_L2R … #define RT5651_RXDP_SEL_R2L … #define RT5651_RXDP_SEL_SWAP … #define RT5651_TXDC_SEL_MASK … #define RT5651_TXDC_SEL_SFT … #define RT5651_TXDC_SEL_NOR … #define RT5651_TXDC_SEL_L2R … #define RT5651_TXDC_SEL_R2L … #define RT5651_TXDC_SEL_SWAP … #define RT5651_TXDP_SEL_MASK … #define RT5651_TXDP_SEL_SFT … #define RT5651_TXDP_SEL_NOR … #define RT5651_TXDP_SEL_L2R … #define RT5651_TXDP_SEL_R2L … #define RT5651_TRXDP_SEL_SWAP … /* Digital Interface Data Control (0x2f) */ #define RT5651_IF2_DAC_SEL_MASK … #define RT5651_IF2_DAC_SEL_SFT … #define RT5651_IF2_DAC_SEL_NOR … #define RT5651_IF2_DAC_SEL_SWAP … #define RT5651_IF2_DAC_SEL_L2R … #define RT5651_IF2_DAC_SEL_R2L … #define RT5651_IF2_ADC_SEL_MASK … #define RT5651_IF2_ADC_SEL_SFT … #define RT5651_IF2_ADC_SEL_NOR … #define RT5651_IF2_ADC_SEL_SWAP … #define RT5651_IF2_ADC_SEL_L2R … #define RT5651_IF2_ADC_SEL_R2L … #define RT5651_IF2_ADC_SRC_MASK … #define RT5651_IF2_ADC_SRC_SFT … #define RT5651_IF1_ADC1 … #define RT5651_IF1_ADC2 … /* PDM Output Control (0x30) */ #define RT5651_PDM_L_SEL_MASK … #define RT5651_PDM_L_SEL_SFT … #define RT5651_PDM_L_SEL_DD_L … #define RT5651_PDM_L_SEL_STO_L … #define RT5651_M_PDM_L … #define RT5651_M_PDM_L_SFT … #define RT5651_PDM_R_SEL_MASK … #define RT5651_PDM_R_SEL_SFT … #define RT5651_PDM_R_SEL_DD_L … #define RT5651_PDM_R_SEL_STO_L … #define RT5651_M_PDM_R … #define RT5651_M_PDM_R_SFT … #define RT5651_PDM_BUSY … #define RT5651_PDM_BUSY_SFT … #define RT5651_PDM_PATTERN_SEL_MASK … #define RT5651_PDM_PATTERN_SEL_64 … #define RT5651_PDM_PATTERN_SEL_128 … #define RT5651_PDM_VOL_MASK … #define RT5651_PDM_VOL_SFT … #define RT5651_PDM_DIV_MASK … #define RT5651_PDM_DIV_SFT … #define RT5651_PDM_DIV_1 … #define RT5651_PDM_DIV_2 … #define RT5651_PDM_DIV_3 … #define RT5651_PDM_DIV_4 … /* PDM I2C/Data Control 1 (0x31) */ #define RT5651_PDM_I2C_ID_MASK … #define PT5631_PDM_CMD_EXE … #define RT5651_PDM_I2C_CMD_MASK … #define RT5651_PDM_I2C_CMD_R … #define RT5651_PDM_I2C_CMD_W … #define RT5651_PDM_I2C_CMD_EXE … #define RT5651_PDM_I2C_NORMAL … #define RT5651_PDM_I2C_BUSY … /* PDM I2C/Data Control 2 (0x32) */ #define RT5651_PDM_I2C_ADDR … #define RT5651_PDM_I2C_CMD_PATTERN … /* REC Left Mixer Control 1 (0x3b) */ #define RT5651_G_LN_L2_RM_L_MASK … #define RT5651_G_IN_L2_RM_L_SFT … #define RT5651_G_LN_L1_RM_L_MASK … #define RT5651_G_IN_L1_RM_L_SFT … #define RT5651_G_BST3_RM_L_MASK … #define RT5651_G_BST3_RM_L_SFT … #define RT5651_G_BST2_RM_L_MASK … #define RT5651_G_BST2_RM_L_SFT … /* REC Left Mixer Control 2 (0x3c) */ #define RT5651_G_BST1_RM_L_MASK … #define RT5651_G_BST1_RM_L_SFT … #define RT5651_G_OM_L_RM_L_MASK … #define RT5651_G_OM_L_RM_L_SFT … #define RT5651_M_IN2_L_RM_L … #define RT5651_M_IN2_L_RM_L_SFT … #define RT5651_M_IN1_L_RM_L … #define RT5651_M_IN1_L_RM_L_SFT … #define RT5651_M_BST3_RM_L … #define RT5651_M_BST3_RM_L_SFT … #define RT5651_M_BST2_RM_L … #define RT5651_M_BST2_RM_L_SFT … #define RT5651_M_BST1_RM_L … #define RT5651_M_BST1_RM_L_SFT … #define RT5651_M_OM_L_RM_L … #define RT5651_M_OM_L_RM_L_SFT … /* REC Right Mixer Control 1 (0x3d) */ #define RT5651_G_IN2_R_RM_R_MASK … #define RT5651_G_IN2_R_RM_R_SFT … #define RT5651_G_IN1_R_RM_R_MASK … #define RT5651_G_IN1_R_RM_R_SFT … #define RT5651_G_BST3_RM_R_MASK … #define RT5651_G_BST3_RM_R_SFT … #define RT5651_G_BST2_RM_R_MASK … #define RT5651_G_BST2_RM_R_SFT … /* REC Right Mixer Control 2 (0x3e) */ #define RT5651_G_BST1_RM_R_MASK … #define RT5651_G_BST1_RM_R_SFT … #define RT5651_G_OM_R_RM_R_MASK … #define RT5651_G_OM_R_RM_R_SFT … #define RT5651_M_IN2_R_RM_R … #define RT5651_M_IN2_R_RM_R_SFT … #define RT5651_M_IN1_R_RM_R … #define RT5651_M_IN1_R_RM_R_SFT … #define RT5651_M_BST3_RM_R … #define RT5651_M_BST3_RM_R_SFT … #define RT5651_M_BST2_RM_R … #define RT5651_M_BST2_RM_R_SFT … #define RT5651_M_BST1_RM_R … #define RT5651_M_BST1_RM_R_SFT … #define RT5651_M_OM_R_RM_R … #define RT5651_M_OM_R_RM_R_SFT … /* HPMIX Control (0x45) */ #define RT5651_M_DAC1_HM … #define RT5651_M_DAC1_HM_SFT … #define RT5651_M_HPVOL_HM … #define RT5651_M_HPVOL_HM_SFT … #define RT5651_G_HPOMIX_MASK … #define RT5651_G_HPOMIX_SFT … /* SPK Left Mixer Control (0x46) */ #define RT5651_G_RM_L_SM_L_MASK … #define RT5651_G_RM_L_SM_L_SFT … #define RT5651_G_IN_L_SM_L_MASK … #define RT5651_G_IN_L_SM_L_SFT … #define RT5651_G_DAC_L1_SM_L_MASK … #define RT5651_G_DAC_L1_SM_L_SFT … #define RT5651_G_DAC_L2_SM_L_MASK … #define RT5651_G_DAC_L2_SM_L_SFT … #define RT5651_G_OM_L_SM_L_MASK … #define RT5651_G_OM_L_SM_L_SFT … #define RT5651_M_RM_L_SM_L … #define RT5651_M_RM_L_SM_L_SFT … #define RT5651_M_IN_L_SM_L … #define RT5651_M_IN_L_SM_L_SFT … #define RT5651_M_DAC_L1_SM_L … #define RT5651_M_DAC_L1_SM_L_SFT … #define RT5651_M_DAC_L2_SM_L … #define RT5651_M_DAC_L2_SM_L_SFT … #define RT5651_M_OM_L_SM_L … #define RT5651_M_OM_L_SM_L_SFT … /* SPK Right Mixer Control (0x47) */ #define RT5651_G_RM_R_SM_R_MASK … #define RT5651_G_RM_R_SM_R_SFT … #define RT5651_G_IN_R_SM_R_MASK … #define RT5651_G_IN_R_SM_R_SFT … #define RT5651_G_DAC_R1_SM_R_MASK … #define RT5651_G_DAC_R1_SM_R_SFT … #define RT5651_G_DAC_R2_SM_R_MASK … #define RT5651_G_DAC_R2_SM_R_SFT … #define RT5651_G_OM_R_SM_R_MASK … #define RT5651_G_OM_R_SM_R_SFT … #define RT5651_M_RM_R_SM_R … #define RT5651_M_RM_R_SM_R_SFT … #define RT5651_M_IN_R_SM_R … #define RT5651_M_IN_R_SM_R_SFT … #define RT5651_M_DAC_R1_SM_R … #define RT5651_M_DAC_R1_SM_R_SFT … #define RT5651_M_DAC_R2_SM_R … #define RT5651_M_DAC_R2_SM_R_SFT … #define RT5651_M_OM_R_SM_R … #define RT5651_M_OM_R_SM_R_SFT … /* SPOLMIX Control (0x48) */ #define RT5651_M_DAC_R1_SPM_L … #define RT5651_M_DAC_R1_SPM_L_SFT … #define RT5651_M_DAC_L1_SPM_L … #define RT5651_M_DAC_L1_SPM_L_SFT … #define RT5651_M_SV_R_SPM_L … #define RT5651_M_SV_R_SPM_L_SFT … #define RT5651_M_SV_L_SPM_L … #define RT5651_M_SV_L_SPM_L_SFT … #define RT5651_M_BST1_SPM_L … #define RT5651_M_BST1_SPM_L_SFT … /* SPORMIX Control (0x49) */ #define RT5651_M_DAC_R1_SPM_R … #define RT5651_M_DAC_R1_SPM_R_SFT … #define RT5651_M_SV_R_SPM_R … #define RT5651_M_SV_R_SPM_R_SFT … #define RT5651_M_BST1_SPM_R … #define RT5651_M_BST1_SPM_R_SFT … /* SPOLMIX / SPORMIX Ratio Control (0x4a) */ #define RT5651_SPO_CLSD_RATIO_MASK … #define RT5651_SPO_CLSD_RATIO_SFT … /* Mono Output Mixer Control (0x4c) */ #define RT5651_M_DAC_R2_MM … #define RT5651_M_DAC_R2_MM_SFT … #define RT5651_M_DAC_L2_MM … #define RT5651_M_DAC_L2_MM_SFT … #define RT5651_M_OV_R_MM … #define RT5651_M_OV_R_MM_SFT … #define RT5651_M_OV_L_MM … #define RT5651_M_OV_L_MM_SFT … #define RT5651_M_BST1_MM … #define RT5651_M_BST1_MM_SFT … #define RT5651_G_MONOMIX_MASK … #define RT5651_G_MONOMIX_SFT … /* Output Left Mixer Control 1 (0x4d) */ #define RT5651_G_BST2_OM_L_MASK … #define RT5651_G_BST2_OM_L_SFT … #define RT5651_G_BST1_OM_L_MASK … #define RT5651_G_BST1_OM_L_SFT … #define RT5651_G_IN1_L_OM_L_MASK … #define RT5651_G_IN1_L_OM_L_SFT … #define RT5651_G_RM_L_OM_L_MASK … #define RT5651_G_RM_L_OM_L_SFT … /* Output Left Mixer Control 2 (0x4e) */ #define RT5651_G_DAC_L1_OM_L_MASK … #define RT5651_G_DAC_L1_OM_L_SFT … #define RT5651_G_IN2_L_OM_L_MASK … #define RT5651_G_IN2_L_OM_L_SFT … /* Output Left Mixer Control 3 (0x4f) */ #define RT5651_M_IN2_L_OM_L … #define RT5651_M_IN2_L_OM_L_SFT … #define RT5651_M_BST2_OM_L … #define RT5651_M_BST2_OM_L_SFT … #define RT5651_M_BST1_OM_L … #define RT5651_M_BST1_OM_L_SFT … #define RT5651_M_IN1_L_OM_L … #define RT5651_M_IN1_L_OM_L_SFT … #define RT5651_M_RM_L_OM_L … #define RT5651_M_RM_L_OM_L_SFT … #define RT5651_M_DAC_L1_OM_L … #define RT5651_M_DAC_L1_OM_L_SFT … /* Output Right Mixer Control 1 (0x50) */ #define RT5651_G_BST2_OM_R_MASK … #define RT5651_G_BST2_OM_R_SFT … #define RT5651_G_BST1_OM_R_MASK … #define RT5651_G_BST1_OM_R_SFT … #define RT5651_G_IN1_R_OM_R_MASK … #define RT5651_G_IN1_R_OM_R_SFT … #define RT5651_G_RM_R_OM_R_MASK … #define RT5651_G_RM_R_OM_R_SFT … /* Output Right Mixer Control 2 (0x51) */ #define RT5651_G_DAC_R1_OM_R_MASK … #define RT5651_G_DAC_R1_OM_R_SFT … #define RT5651_G_IN2_R_OM_R_MASK … #define RT5651_G_IN2_R_OM_R_SFT … /* Output Right Mixer Control 3 (0x52) */ #define RT5651_M_IN2_R_OM_R … #define RT5651_M_IN2_R_OM_R_SFT … #define RT5651_M_BST2_OM_R … #define RT5651_M_BST2_OM_R_SFT … #define RT5651_M_BST1_OM_R … #define RT5651_M_BST1_OM_R_SFT … #define RT5651_M_IN1_R_OM_R … #define RT5651_M_IN1_R_OM_R_SFT … #define RT5651_M_RM_R_OM_R … #define RT5651_M_RM_R_OM_R_SFT … #define RT5651_M_DAC_R1_OM_R … #define RT5651_M_DAC_R1_OM_R_SFT … /* LOUT Mixer Control (0x53) */ #define RT5651_M_DAC_L1_LM … #define RT5651_M_DAC_L1_LM_SFT … #define RT5651_M_DAC_R1_LM … #define RT5651_M_DAC_R1_LM_SFT … #define RT5651_M_OV_L_LM … #define RT5651_M_OV_L_LM_SFT … #define RT5651_M_OV_R_LM … #define RT5651_M_OV_R_LM_SFT … #define RT5651_G_LOUTMIX_MASK … #define RT5651_G_LOUTMIX_SFT … /* Power Management for Digital 1 (0x61) */ #define RT5651_PWR_I2S1 … #define RT5651_PWR_I2S1_BIT … #define RT5651_PWR_I2S2 … #define RT5651_PWR_I2S2_BIT … #define RT5651_PWR_DAC_L1 … #define RT5651_PWR_DAC_L1_BIT … #define RT5651_PWR_DAC_R1 … #define RT5651_PWR_DAC_R1_BIT … #define RT5651_PWR_ADC_L … #define RT5651_PWR_ADC_L_BIT … #define RT5651_PWR_ADC_R … #define RT5651_PWR_ADC_R_BIT … /* Power Management for Digital 2 (0x62) */ #define RT5651_PWR_ADC_STO1_F … #define RT5651_PWR_ADC_STO1_F_BIT … #define RT5651_PWR_ADC_STO2_F … #define RT5651_PWR_ADC_STO2_F_BIT … #define RT5651_PWR_DAC_STO1_F … #define RT5651_PWR_DAC_STO1_F_BIT … #define RT5651_PWR_DAC_STO2_F … #define RT5651_PWR_DAC_STO2_F_BIT … #define RT5651_PWR_PDM … #define RT5651_PWR_PDM_BIT … /* Power Management for Analog 1 (0x63) */ #define RT5651_PWR_VREF1 … #define RT5651_PWR_VREF1_BIT … #define RT5651_PWR_FV1 … #define RT5651_PWR_FV1_BIT … #define RT5651_PWR_MB … #define RT5651_PWR_MB_BIT … #define RT5651_PWR_LM … #define RT5651_PWR_LM_BIT … #define RT5651_PWR_BG … #define RT5651_PWR_BG_BIT … #define RT5651_PWR_HP_L … #define RT5651_PWR_HP_L_BIT … #define RT5651_PWR_HP_R … #define RT5651_PWR_HP_R_BIT … #define RT5651_PWR_HA … #define RT5651_PWR_HA_BIT … #define RT5651_PWR_VREF2 … #define RT5651_PWR_VREF2_BIT … #define RT5651_PWR_FV2 … #define RT5651_PWR_FV2_BIT … #define RT5651_PWR_LDO … #define RT5651_PWR_LDO_BIT … #define RT5651_PWR_LDO_DVO_MASK … #define RT5651_PWR_LDO_DVO_1_0V … #define RT5651_PWR_LDO_DVO_1_1V … #define RT5651_PWR_LDO_DVO_1_2V … #define RT5651_PWR_LDO_DVO_1_3V … /* Power Management for Analog 2 (0x64) */ #define RT5651_PWR_BST1 … #define RT5651_PWR_BST1_BIT … #define RT5651_PWR_BST2 … #define RT5651_PWR_BST2_BIT … #define RT5651_PWR_BST3 … #define RT5651_PWR_BST3_BIT … #define RT5651_PWR_MB1 … #define RT5651_PWR_MB1_BIT … #define RT5651_PWR_PLL … #define RT5651_PWR_PLL_BIT … #define RT5651_PWR_BST1_OP2 … #define RT5651_PWR_BST1_OP2_BIT … #define RT5651_PWR_BST2_OP2 … #define RT5651_PWR_BST2_OP2_BIT … #define RT5651_PWR_BST3_OP2 … #define RT5651_PWR_BST3_OP2_BIT … #define RT5651_PWR_JD_M … #define RT5651_PWM_JD_M_BIT … #define RT5651_PWR_JD2 … #define RT5651_PWM_JD2_BIT … #define RT5651_PWR_JD3 … #define RT5651_PWM_JD3_BIT … /* Power Management for Mixer (0x65) */ #define RT5651_PWR_OM_L … #define RT5651_PWR_OM_L_BIT … #define RT5651_PWR_OM_R … #define RT5651_PWR_OM_R_BIT … #define RT5651_PWR_RM_L … #define RT5651_PWR_RM_L_BIT … #define RT5651_PWR_RM_R … #define RT5651_PWR_RM_R_BIT … /* Power Management for Volume (0x66) */ #define RT5651_PWR_OV_L … #define RT5651_PWR_OV_L_BIT … #define RT5651_PWR_OV_R … #define RT5651_PWR_OV_R_BIT … #define RT5651_PWR_HV_L … #define RT5651_PWR_HV_L_BIT … #define RT5651_PWR_HV_R … #define RT5651_PWR_HV_R_BIT … #define RT5651_PWR_IN1_L … #define RT5651_PWR_IN1_L_BIT … #define RT5651_PWR_IN1_R … #define RT5651_PWR_IN1_R_BIT … #define RT5651_PWR_IN2_L … #define RT5651_PWR_IN2_L_BIT … #define RT5651_PWR_IN2_R … #define RT5651_PWR_IN2_R_BIT … /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */ #define RT5651_I2S_MS_MASK … #define RT5651_I2S_MS_SFT … #define RT5651_I2S_MS_M … #define RT5651_I2S_MS_S … #define RT5651_I2S_O_CP_MASK … #define RT5651_I2S_O_CP_SFT … #define RT5651_I2S_O_CP_OFF … #define RT5651_I2S_O_CP_U_LAW … #define RT5651_I2S_O_CP_A_LAW … #define RT5651_I2S_I_CP_MASK … #define RT5651_I2S_I_CP_SFT … #define RT5651_I2S_I_CP_OFF … #define RT5651_I2S_I_CP_U_LAW … #define RT5651_I2S_I_CP_A_LAW … #define RT5651_I2S_BP_MASK … #define RT5651_I2S_BP_SFT … #define RT5651_I2S_BP_NOR … #define RT5651_I2S_BP_INV … #define RT5651_I2S_DL_MASK … #define RT5651_I2S_DL_SFT … #define RT5651_I2S_DL_16 … #define RT5651_I2S_DL_20 … #define RT5651_I2S_DL_24 … #define RT5651_I2S_DL_8 … #define RT5651_I2S_DF_MASK … #define RT5651_I2S_DF_SFT … #define RT5651_I2S_DF_I2S … #define RT5651_I2S_DF_LEFT … #define RT5651_I2S_DF_PCM_A … #define RT5651_I2S_DF_PCM_B … /* ADC/DAC Clock Control 1 (0x73) */ #define RT5651_I2S_PD1_MASK … #define RT5651_I2S_PD1_SFT … #define RT5651_I2S_PD1_1 … #define RT5651_I2S_PD1_2 … #define RT5651_I2S_PD1_3 … #define RT5651_I2S_PD1_4 … #define RT5651_I2S_PD1_6 … #define RT5651_I2S_PD1_8 … #define RT5651_I2S_PD1_12 … #define RT5651_I2S_PD1_16 … #define RT5651_I2S_BCLK_MS2_MASK … #define RT5651_I2S_BCLK_MS2_SFT … #define RT5651_I2S_BCLK_MS2_32 … #define RT5651_I2S_BCLK_MS2_64 … #define RT5651_I2S_PD2_MASK … #define RT5651_I2S_PD2_SFT … #define RT5651_I2S_PD2_1 … #define RT5651_I2S_PD2_2 … #define RT5651_I2S_PD2_3 … #define RT5651_I2S_PD2_4 … #define RT5651_I2S_PD2_6 … #define RT5651_I2S_PD2_8 … #define RT5651_I2S_PD2_12 … #define RT5651_I2S_PD2_16 … #define RT5651_DAC_OSR_MASK … #define RT5651_DAC_OSR_SFT … #define RT5651_DAC_OSR_128 … #define RT5651_DAC_OSR_64 … #define RT5651_DAC_OSR_32 … #define RT5651_DAC_OSR_128_3 … #define RT5651_ADC_OSR_MASK … #define RT5651_ADC_OSR_SFT … #define RT5651_ADC_OSR_128 … #define RT5651_ADC_OSR_64 … #define RT5651_ADC_OSR_32 … #define RT5651_ADC_OSR_128_3 … /* ADC/DAC Clock Control 2 (0x74) */ #define RT5651_DAHPF_EN … #define RT5651_DAHPF_EN_SFT … #define RT5651_ADHPF_EN … #define RT5651_ADHPF_EN_SFT … /* Digital Microphone Control (0x75) */ #define RT5651_DMIC_1_EN_MASK … #define RT5651_DMIC_1_EN_SFT … #define RT5651_DMIC_1_DIS … #define RT5651_DMIC_1_EN … #define RT5651_DMIC_1L_LH_MASK … #define RT5651_DMIC_1L_LH_SFT … #define RT5651_DMIC_1L_LH_FALLING … #define RT5651_DMIC_1L_LH_RISING … #define RT5651_DMIC_1R_LH_MASK … #define RT5651_DMIC_1R_LH_SFT … #define RT5651_DMIC_1R_LH_FALLING … #define RT5651_DMIC_1R_LH_RISING … #define RT5651_DMIC_1_DP_MASK … #define RT5651_DMIC_1_DP_SFT … #define RT5651_DMIC_1_DP_GPIO6 … #define RT5651_DMIC_1_DP_IN1P … #define RT5651_DMIC_2_DP_GPIO8 … #define RT5651_DMIC_CLK_MASK … #define RT5651_DMIC_CLK_SFT … /* TDM Control 1 (0x77) */ #define RT5651_TDM_INTEL_SEL_MASK … #define RT5651_TDM_INTEL_SEL_SFT … #define RT5651_TDM_INTEL_SEL_64 … #define RT5651_TDM_INTEL_SEL_50 … #define RT5651_TDM_MODE_SEL_MASK … #define RT5651_TDM_MODE_SEL_SFT … #define RT5651_TDM_MODE_SEL_NOR … #define RT5651_TDM_MODE_SEL_TDM … #define RT5651_TDM_CH_NUM_SEL_MASK … #define RT5651_TDM_CH_NUM_SEL_SFT … #define RT5651_TDM_CH_NUM_SEL_2 … #define RT5651_TDM_CH_NUM_SEL_4 … #define RT5651_TDM_CH_NUM_SEL_6 … #define RT5651_TDM_CH_NUM_SEL_8 … #define RT5651_TDM_CH_LEN_SEL_MASK … #define RT5651_TDM_CH_LEN_SEL_SFT … #define RT5651_TDM_CH_LEN_SEL_16 … #define RT5651_TDM_CH_LEN_SEL_20 … #define RT5651_TDM_CH_LEN_SEL_24 … #define RT5651_TDM_CH_LEN_SEL_32 … #define RT5651_TDM_ADC_SEL_MASK … #define RT5651_TDM_ADC_SEL_SFT … #define RT5651_TDM_ADC_SEL_NOR … #define RT5651_TDM_ADC_SEL_SWAP … #define RT5651_TDM_ADC_START_SEL_MASK … #define RT5651_TDM_ADC_START_SEL_SFT … #define RT5651_TDM_ADC_START_SEL_SL0 … #define RT5651_TDM_ADC_START_SEL_SL4 … #define RT5651_TDM_I2S_CH2_SEL_MASK … #define RT5651_TDM_I2S_CH2_SEL_SFT … #define RT5651_TDM_I2S_CH2_SEL_LR … #define RT5651_TDM_I2S_CH2_SEL_RL … #define RT5651_TDM_I2S_CH2_SEL_LL … #define RT5651_TDM_I2S_CH2_SEL_RR … #define RT5651_TDM_I2S_CH4_SEL_MASK … #define RT5651_TDM_I2S_CH4_SEL_SFT … #define RT5651_TDM_I2S_CH4_SEL_LR … #define RT5651_TDM_I2S_CH4_SEL_RL … #define RT5651_TDM_I2S_CH4_SEL_LL … #define RT5651_TDM_I2S_CH4_SEL_RR … #define RT5651_TDM_I2S_CH6_SEL_MASK … #define RT5651_TDM_I2S_CH6_SEL_SFT … #define RT5651_TDM_I2S_CH6_SEL_LR … #define RT5651_TDM_I2S_CH6_SEL_RL … #define RT5651_TDM_I2S_CH6_SEL_LL … #define RT5651_TDM_I2S_CH6_SEL_RR … #define RT5651_TDM_I2S_CH8_SEL_MASK … #define RT5651_TDM_I2S_CH8_SEL_SFT … #define RT5651_TDM_I2S_CH8_SEL_LR … #define RT5651_TDM_I2S_CH8_SEL_RL … #define RT5651_TDM_I2S_CH8_SEL_LL … #define RT5651_TDM_I2S_CH8_SEL_RR … /* TDM Control 2 (0x78) */ #define RT5651_TDM_LRCK_POL_SEL_MASK … #define RT5651_TDM_LRCK_POL_SEL_SFT … #define RT5651_TDM_LRCK_POL_SEL_NOR … #define RT5651_TDM_LRCK_POL_SEL_INV … #define RT5651_TDM_CH_VAL_SEL_MASK … #define RT5651_TDM_CH_VAL_SEL_SFT … #define RT5651_TDM_CH_VAL_SEL_CH01 … #define RT5651_TDM_CH_VAL_SEL_CH0123 … #define RT5651_TDM_CH_VAL_EN … #define RT5651_TDM_CH_VAL_SFT … #define RT5651_TDM_LPBK_EN … #define RT5651_TDM_LPBK_SFT … #define RT5651_TDM_LRCK_PULSE_SEL_MASK … #define RT5651_TDM_LRCK_PULSE_SEL_SFT … #define RT5651_TDM_LRCK_PULSE_SEL_BCLK … #define RT5651_TDM_LRCK_PULSE_SEL_CH … #define RT5651_TDM_END_EDGE_SEL_MASK … #define RT5651_TDM_END_EDGE_SEL_SFT … #define RT5651_TDM_END_EDGE_SEL_POS … #define RT5651_TDM_END_EDGE_SEL_NEG … #define RT5651_TDM_END_EDGE_EN … #define RT5651_TDM_END_EDGE_EN_SFT … #define RT5651_TDM_TRAN_EDGE_SEL_MASK … #define RT5651_TDM_TRAN_EDGE_SEL_SFT … #define RT5651_TDM_TRAN_EDGE_SEL_POS … #define RT5651_TDM_TRAN_EDGE_SEL_NEG … #define RT5651_M_TDM2_L … #define RT5651_M_TDM2_L_SFT … #define RT5651_M_TDM2_R … #define RT5651_M_TDM2_R_SFT … #define RT5651_M_TDM4_L … #define RT5651_M_TDM4_L_SFT … #define RT5651_M_TDM4_R … #define RT5651_M_TDM4_R_SFT … /* TDM Control 3 (0x79) */ #define RT5651_CH2_L_SEL_MASK … #define RT5651_CH2_L_SEL_SFT … #define RT5651_CH2_L_SEL_SL0 … #define RT5651_CH2_L_SEL_SL1 … #define RT5651_CH2_L_SEL_SL2 … #define RT5651_CH2_L_SEL_SL3 … #define RT5651_CH2_L_SEL_SL4 … #define RT5651_CH2_L_SEL_SL5 … #define RT5651_CH2_L_SEL_SL6 … #define RT5651_CH2_L_SEL_SL7 … #define RT5651_CH2_R_SEL_MASK … #define RT5651_CH2_R_SEL_SFT … #define RT5651_CH2_R_SEL_SL0 … #define RT5651_CH2_R_SEL_SL1 … #define RT5651_CH2_R_SEL_SL2 … #define RT5651_CH2_R_SEL_SL3 … #define RT5651_CH2_R_SEL_SL4 … #define RT5651_CH2_R_SEL_SL5 … #define RT5651_CH2_R_SEL_SL6 … #define RT5651_CH2_R_SEL_SL7 … #define RT5651_CH4_L_SEL_MASK … #define RT5651_CH4_L_SEL_SFT … #define RT5651_CH4_L_SEL_SL0 … #define RT5651_CH4_L_SEL_SL1 … #define RT5651_CH4_L_SEL_SL2 … #define RT5651_CH4_L_SEL_SL3 … #define RT5651_CH4_L_SEL_SL4 … #define RT5651_CH4_L_SEL_SL5 … #define RT5651_CH4_L_SEL_SL6 … #define RT5651_CH4_L_SEL_SL7 … #define RT5651_CH4_R_SEL_MASK … #define RT5651_CH4_R_SEL_SFT … #define RT5651_CH4_R_SEL_SL0 … #define RT5651_CH4_R_SEL_SL1 … #define RT5651_CH4_R_SEL_SL2 … #define RT5651_CH4_R_SEL_SL3 … #define RT5651_CH4_R_SEL_SL4 … #define RT5651_CH4_R_SEL_SL5 … #define RT5651_CH4_R_SEL_SL6 … #define RT5651_CH4_R_SEL_SL7 … /* Global Clock Control (0x80) */ #define RT5651_SCLK_SRC_MASK … #define RT5651_SCLK_SRC_SFT … #define RT5651_SCLK_SRC_MCLK … #define RT5651_SCLK_SRC_PLL1 … #define RT5651_SCLK_SRC_RCCLK … #define RT5651_PLL1_SRC_MASK … #define RT5651_PLL1_SRC_SFT … #define RT5651_PLL1_SRC_MCLK … #define RT5651_PLL1_SRC_BCLK1 … #define RT5651_PLL1_SRC_BCLK2 … #define RT5651_PLL1_PD_MASK … #define RT5651_PLL1_PD_SFT … #define RT5651_PLL1_PD_1 … #define RT5651_PLL1_PD_2 … #define RT5651_PLL_INP_MAX … #define RT5651_PLL_INP_MIN … /* PLL M/N/K Code Control 1 (0x81) */ #define RT5651_PLL_N_MAX … #define RT5651_PLL_N_MASK … #define RT5651_PLL_N_SFT … #define RT5651_PLL_K_MAX … #define RT5651_PLL_K_MASK … #define RT5651_PLL_K_SFT … /* PLL M/N/K Code Control 2 (0x82) */ #define RT5651_PLL_M_MAX … #define RT5651_PLL_M_MASK … #define RT5651_PLL_M_SFT … #define RT5651_PLL_M_BP … #define RT5651_PLL_M_BP_SFT … /* PLL tracking mode 1 (0x83) */ #define RT5651_STO1_T_MASK … #define RT5651_STO1_T_SFT … #define RT5651_STO1_T_SCLK … #define RT5651_STO1_T_LRCK1 … #define RT5651_STO2_T_MASK … #define RT5651_STO2_T_SFT … #define RT5651_STO2_T_I2S2 … #define RT5651_STO2_T_LRCK2 … #define RT5651_ASRC2_REF_MASK … #define RT5651_ASRC2_REF_SFT … #define RT5651_ASRC2_REF_LRCK2 … #define RT5651_ASRC2_REF_LRCK1 … #define RT5651_DMIC_1_M_MASK … #define RT5651_DMIC_1_M_SFT … #define RT5651_DMIC_1_M_NOR … #define RT5651_DMIC_1_M_ASYN … /* PLL tracking mode 2 (0x84) */ #define RT5651_STO1_ASRC_EN … #define RT5651_STO1_ASRC_EN_SFT … #define RT5651_STO2_ASRC_EN … #define RT5651_STO2_ASRC_EN_SFT … #define RT5651_STO1_DAC_M_MASK … #define RT5651_STO1_DAC_M_SFT … #define RT5651_STO1_DAC_M_NOR … #define RT5651_STO1_DAC_M_ASRC … #define RT5651_STO2_DAC_M_MASK … #define RT5651_STO2_DAC_M_SFT … #define RT5651_STO2_DAC_M_NOR … #define RT5651_STO2_DAC_M_ASRC … #define RT5651_ADC_M_MASK … #define RT5651_ADC_M_SFT … #define RT5651_ADC_M_NOR … #define RT5651_ADC_M_ASRC … #define RT5651_I2S1_R_D_MASK … #define RT5651_I2S1_R_D_SFT … #define RT5651_I2S1_R_D_DIS … #define RT5651_I2S1_R_D_EN … #define RT5651_I2S2_R_D_MASK … #define RT5651_I2S2_R_D_SFT … #define RT5651_I2S2_R_D_DIS … #define RT5651_I2S2_R_D_EN … #define RT5651_PRE_SCLK_MASK … #define RT5651_PRE_SCLK_SFT … #define RT5651_PRE_SCLK_512 … #define RT5651_PRE_SCLK_1024 … #define RT5651_PRE_SCLK_2048 … /* PLL tracking mode 3 (0x85) */ #define RT5651_I2S1_RATE_MASK … #define RT5651_I2S1_RATE_SFT … #define RT5651_I2S2_RATE_MASK … #define RT5651_I2S2_RATE_SFT … #define RT5651_G_ASRC_LP_MASK … #define RT5651_G_ASRC_LP_SFT … #define RT5651_ASRC_LP_F_M … #define RT5651_ASRC_LP_F_SFT … #define RT5651_ASRC_LP_F_NOR … #define RT5651_ASRC_LP_F_SB … #define RT5651_FTK_PH_DET_MASK … #define RT5651_FTK_PH_DET_SFT … #define RT5651_FTK_PH_DET_DIV1 … #define RT5651_FTK_PH_DET_DIV2 … #define RT5651_FTK_PH_DET_DIV4 … #define RT5651_FTK_PH_DET_DIV8 … /*PLL tracking mode 6 (0x89) */ #define RT5651_I2S1_PD_MASK … #define RT5651_I2S1_PD_SFT … #define RT5651_I2S2_PD_MASK … #define RT5651_I2S2_PD_SFT … /*PLL tracking mode 7 (0x8a) */ #define RT5651_FSI1_RATE_MASK … #define RT5651_FSI1_RATE_SFT … #define RT5651_FSI2_RATE_MASK … #define RT5651_FSI2_RATE_SFT … /* HPOUT Over Current Detection (0x8b) */ #define RT5651_HP_OVCD_MASK … #define RT5651_HP_OVCD_SFT … #define RT5651_HP_OVCD_DIS … #define RT5651_HP_OVCD_EN … #define RT5651_HP_OC_TH_MASK … #define RT5651_HP_OC_TH_SFT … #define RT5651_HP_OC_TH_90 … #define RT5651_HP_OC_TH_105 … #define RT5651_HP_OC_TH_120 … #define RT5651_HP_OC_TH_135 … /* Depop Mode Control 1 (0x8e) */ #define RT5651_SMT_TRIG_MASK … #define RT5651_SMT_TRIG_SFT … #define RT5651_SMT_TRIG_DIS … #define RT5651_SMT_TRIG_EN … #define RT5651_HP_L_SMT_MASK … #define RT5651_HP_L_SMT_SFT … #define RT5651_HP_L_SMT_DIS … #define RT5651_HP_L_SMT_EN … #define RT5651_HP_R_SMT_MASK … #define RT5651_HP_R_SMT_SFT … #define RT5651_HP_R_SMT_DIS … #define RT5651_HP_R_SMT_EN … #define RT5651_HP_CD_PD_MASK … #define RT5651_HP_CD_PD_SFT … #define RT5651_HP_CD_PD_DIS … #define RT5651_HP_CD_PD_EN … #define RT5651_RSTN_MASK … #define RT5651_RSTN_SFT … #define RT5651_RSTN_DIS … #define RT5651_RSTN_EN … #define RT5651_RSTP_MASK … #define RT5651_RSTP_SFT … #define RT5651_RSTP_DIS … #define RT5651_RSTP_EN … #define RT5651_HP_CO_MASK … #define RT5651_HP_CO_SFT … #define RT5651_HP_CO_DIS … #define RT5651_HP_CO_EN … #define RT5651_HP_CP_MASK … #define RT5651_HP_CP_SFT … #define RT5651_HP_CP_PD … #define RT5651_HP_CP_PU … #define RT5651_HP_SG_MASK … #define RT5651_HP_SG_SFT … #define RT5651_HP_SG_DIS … #define RT5651_HP_SG_EN … #define RT5651_HP_DP_MASK … #define RT5651_HP_DP_SFT … #define RT5651_HP_DP_PD … #define RT5651_HP_DP_PU … #define RT5651_HP_CB_MASK … #define RT5651_HP_CB_SFT … #define RT5651_HP_CB_PD … #define RT5651_HP_CB_PU … /* Depop Mode Control 2 (0x8f) */ #define RT5651_DEPOP_MASK … #define RT5651_DEPOP_SFT … #define RT5651_DEPOP_AUTO … #define RT5651_DEPOP_MAN … #define RT5651_RAMP_MASK … #define RT5651_RAMP_SFT … #define RT5651_RAMP_DIS … #define RT5651_RAMP_EN … #define RT5651_BPS_MASK … #define RT5651_BPS_SFT … #define RT5651_BPS_DIS … #define RT5651_BPS_EN … #define RT5651_FAST_UPDN_MASK … #define RT5651_FAST_UPDN_SFT … #define RT5651_FAST_UPDN_DIS … #define RT5651_FAST_UPDN_EN … #define RT5651_MRES_MASK … #define RT5651_MRES_SFT … #define RT5651_MRES_15MO … #define RT5651_MRES_25MO … #define RT5651_MRES_35MO … #define RT5651_MRES_45MO … #define RT5651_VLO_MASK … #define RT5651_VLO_SFT … #define RT5651_VLO_3V … #define RT5651_VLO_32V … #define RT5651_DIG_DP_MASK … #define RT5651_DIG_DP_SFT … #define RT5651_DIG_DP_DIS … #define RT5651_DIG_DP_EN … #define RT5651_DP_TH_MASK … #define RT5651_DP_TH_SFT … /* Depop Mode Control 3 (0x90) */ #define RT5651_CP_SYS_MASK … #define RT5651_CP_SYS_SFT … #define RT5651_CP_FQ1_MASK … #define RT5651_CP_FQ1_SFT … #define RT5651_CP_FQ2_MASK … #define RT5651_CP_FQ2_SFT … #define RT5651_CP_FQ3_MASK … #define RT5651_CP_FQ3_SFT … #define RT5651_CP_FQ_1_5_KHZ … #define RT5651_CP_FQ_3_KHZ … #define RT5651_CP_FQ_6_KHZ … #define RT5651_CP_FQ_12_KHZ … #define RT5651_CP_FQ_24_KHZ … #define RT5651_CP_FQ_48_KHZ … #define RT5651_CP_FQ_96_KHZ … #define RT5651_CP_FQ_192_KHZ … /* HPOUT charge pump (0x91) */ #define RT5651_OSW_L_MASK … #define RT5651_OSW_L_SFT … #define RT5651_OSW_L_DIS … #define RT5651_OSW_L_EN … #define RT5651_OSW_R_MASK … #define RT5651_OSW_R_SFT … #define RT5651_OSW_R_DIS … #define RT5651_OSW_R_EN … #define RT5651_PM_HP_MASK … #define RT5651_PM_HP_SFT … #define RT5651_PM_HP_LV … #define RT5651_PM_HP_MV … #define RT5651_PM_HP_HV … #define RT5651_IB_HP_MASK … #define RT5651_IB_HP_SFT … #define RT5651_IB_HP_125IL … #define RT5651_IB_HP_25IL … #define RT5651_IB_HP_5IL … #define RT5651_IB_HP_1IL … /* Micbias Control (0x93) */ #define RT5651_MIC1_BS_MASK … #define RT5651_MIC1_BS_SFT … #define RT5651_MIC1_BS_9AV … #define RT5651_MIC1_BS_75AV … #define RT5651_MIC1_CLK_MASK … #define RT5651_MIC1_CLK_SFT … #define RT5651_MIC1_CLK_DIS … #define RT5651_MIC1_CLK_EN … #define RT5651_MIC1_OVCD_MASK … #define RT5651_MIC1_OVCD_SFT … #define RT5651_MIC1_OVCD_DIS … #define RT5651_MIC1_OVCD_EN … #define RT5651_MIC1_OVTH_MASK … #define RT5651_MIC1_OVTH_SFT … #define RT5651_MIC1_OVTH_600UA … #define RT5651_MIC1_OVTH_1500UA … #define RT5651_MIC1_OVTH_2000UA … #define RT5651_PWR_MB_MASK … #define RT5651_PWR_MB_SFT … #define RT5651_PWR_MB_PD … #define RT5651_PWR_MB_PU … #define RT5651_PWR_CLK12M_MASK … #define RT5651_PWR_CLK12M_SFT … #define RT5651_PWR_CLK12M_PD … #define RT5651_PWR_CLK12M_PU … /* Analog JD Control 1 (0x94) */ #define RT5651_JD2_CMP_MASK … #define RT5651_JD2_CMP_SFT … #define RT5651_JD_PU … #define RT5651_JD_PU_SFT … #define RT5651_JD_PD … #define RT5651_JD_PD_SFT … #define RT5651_JD_MODE_SEL_MASK … #define RT5651_JD_MODE_SEL_SFT … #define RT5651_JD_MODE_SEL_M0 … #define RT5651_JD_MODE_SEL_M1 … #define RT5651_JD_MODE_SEL_M2 … #define RT5651_JD_M_CMP … #define RT5651_JD_M_CMP_SFT … #define RT5651_JD_M_PU … #define RT5651_JD_M_PU_SFT … #define RT5651_JD_M_PD … #define RT5651_JD_M_PD_SFT … #define RT5651_JD_M_MODE_SEL_MASK … #define RT5651_JD_M_MODE_SEL_SFT … #define RT5651_JD_M_MODE_SEL_M0 … #define RT5651_JD_M_MODE_SEL_M1 … #define RT5651_JD_M_MODE_SEL_M2 … /* Analog JD Control 2 (0x95) */ #define RT5651_JD3_CMP_MASK … #define RT5651_JD3_CMP_SFT … /* EQ Control 1 (0xb0) */ #define RT5651_EQ_SRC_MASK … #define RT5651_EQ_SRC_SFT … #define RT5651_EQ_SRC_DAC … #define RT5651_EQ_SRC_ADC … #define RT5651_EQ_UPD … #define RT5651_EQ_UPD_BIT … #define RT5651_EQ_CD_MASK … #define RT5651_EQ_CD_SFT … #define RT5651_EQ_CD_DIS … #define RT5651_EQ_CD_EN … #define RT5651_EQ_DITH_MASK … #define RT5651_EQ_DITH_SFT … #define RT5651_EQ_DITH_NOR … #define RT5651_EQ_DITH_LSB … #define RT5651_EQ_DITH_LSB_1 … #define RT5651_EQ_DITH_LSB_2 … #define RT5651_EQ_CD_F … #define RT5651_EQ_CD_F_BIT … #define RT5651_EQ_STA_HP2 … #define RT5651_EQ_STA_HP2_BIT … #define RT5651_EQ_STA_HP1 … #define RT5651_EQ_STA_HP1_BIT … #define RT5651_EQ_STA_BP4 … #define RT5651_EQ_STA_BP4_BIT … #define RT5651_EQ_STA_BP3 … #define RT5651_EQ_STA_BP3_BIT … #define RT5651_EQ_STA_BP2 … #define RT5651_EQ_STA_BP2_BIT … #define RT5651_EQ_STA_BP1 … #define RT5651_EQ_STA_BP1_BIT … #define RT5651_EQ_STA_LP … #define RT5651_EQ_STA_LP_BIT … /* EQ Control 2 (0xb1) */ #define RT5651_EQ_HPF1_M_MASK … #define RT5651_EQ_HPF1_M_SFT … #define RT5651_EQ_HPF1_M_HI … #define RT5651_EQ_HPF1_M_1ST … #define RT5651_EQ_LPF1_M_MASK … #define RT5651_EQ_LPF1_M_SFT … #define RT5651_EQ_LPF1_M_LO … #define RT5651_EQ_LPF1_M_1ST … #define RT5651_EQ_HPF2_MASK … #define RT5651_EQ_HPF2_SFT … #define RT5651_EQ_HPF2_DIS … #define RT5651_EQ_HPF2_EN … #define RT5651_EQ_HPF1_MASK … #define RT5651_EQ_HPF1_SFT … #define RT5651_EQ_HPF1_DIS … #define RT5651_EQ_HPF1_EN … #define RT5651_EQ_BPF4_MASK … #define RT5651_EQ_BPF4_SFT … #define RT5651_EQ_BPF4_DIS … #define RT5651_EQ_BPF4_EN … #define RT5651_EQ_BPF3_MASK … #define RT5651_EQ_BPF3_SFT … #define RT5651_EQ_BPF3_DIS … #define RT5651_EQ_BPF3_EN … #define RT5651_EQ_BPF2_MASK … #define RT5651_EQ_BPF2_SFT … #define RT5651_EQ_BPF2_DIS … #define RT5651_EQ_BPF2_EN … #define RT5651_EQ_BPF1_MASK … #define RT5651_EQ_BPF1_SFT … #define RT5651_EQ_BPF1_DIS … #define RT5651_EQ_BPF1_EN … #define RT5651_EQ_LPF_MASK … #define RT5651_EQ_LPF_SFT … #define RT5651_EQ_LPF_DIS … #define RT5651_EQ_LPF_EN … #define RT5651_EQ_CTRL_MASK … /* Memory Test (0xb2) */ #define RT5651_MT_MASK … #define RT5651_MT_SFT … #define RT5651_MT_DIS … #define RT5651_MT_EN … /* ALC Control 1 (0xb4) */ #define RT5651_ALC_P_MASK … #define RT5651_ALC_P_SFT … #define RT5651_ALC_P_DAC … #define RT5651_ALC_P_ADC … #define RT5651_ALC_MASK … #define RT5651_ALC_SFT … #define RT5651_ALC_DIS … #define RT5651_ALC_EN … #define RT5651_ALC_UPD … #define RT5651_ALC_UPD_BIT … #define RT5651_ALC_AR_MASK … #define RT5651_ALC_AR_SFT … #define RT5651_ALC_R_MASK … #define RT5651_ALC_R_SFT … #define RT5651_ALC_R_48K … #define RT5651_ALC_R_96K … #define RT5651_ALC_R_192K … #define RT5651_ALC_R_441K … #define RT5651_ALC_R_882K … #define RT5651_ALC_R_1764K … #define RT5651_ALC_RC_MASK … #define RT5651_ALC_RC_SFT … /* ALC Control 2 (0xb5) */ #define RT5651_ALC_POB_MASK … #define RT5651_ALC_POB_SFT … #define RT5651_ALC_DRC_MASK … #define RT5651_ALC_DRC_SFT … #define RT5651_ALC_DRC_DIS … #define RT5651_ALC_DRC_EN … #define RT5651_ALC_CPR_MASK … #define RT5651_ALC_CPR_SFT … #define RT5651_ALC_CPR_1_1 … #define RT5651_ALC_CPR_1_2 … #define RT5651_ALC_CPR_1_4 … #define RT5651_ALC_CPR_1_8 … #define RT5651_ALC_PRB_MASK … #define RT5651_ALC_PRB_SFT … /* ALC Control 3 (0xb6) */ #define RT5651_ALC_NGB_MASK … #define RT5651_ALC_NGB_SFT … #define RT5651_ALC_TAR_MASK … #define RT5651_ALC_TAR_SFT … #define RT5651_ALC_NG_MASK … #define RT5651_ALC_NG_SFT … #define RT5651_ALC_NG_DIS … #define RT5651_ALC_NG_EN … #define RT5651_ALC_NGH_MASK … #define RT5651_ALC_NGH_SFT … #define RT5651_ALC_NGH_DIS … #define RT5651_ALC_NGH_EN … #define RT5651_ALC_NGT_MASK … #define RT5651_ALC_NGT_SFT … /* Jack Detect Control 1 (0xbb) */ #define RT5651_JD_MASK … #define RT5651_JD_SFT … #define RT5651_JD_DIS … #define RT5651_JD_GPIO1 … #define RT5651_JD_GPIO2 … #define RT5651_JD_GPIO3 … #define RT5651_JD_GPIO4 … #define RT5651_JD_GPIO5 … #define RT5651_JD_GPIO6 … #define RT5651_JD_HP_MASK … #define RT5651_JD_HP_SFT … #define RT5651_JD_HP_DIS … #define RT5651_JD_HP_EN … #define RT5651_JD_HP_TRG_MASK … #define RT5651_JD_HP_TRG_SFT … #define RT5651_JD_HP_TRG_LO … #define RT5651_JD_HP_TRG_HI … #define RT5651_JD_SPL_MASK … #define RT5651_JD_SPL_SFT … #define RT5651_JD_SPL_DIS … #define RT5651_JD_SPL_EN … #define RT5651_JD_SPL_TRG_MASK … #define RT5651_JD_SPL_TRG_SFT … #define RT5651_JD_SPL_TRG_LO … #define RT5651_JD_SPL_TRG_HI … #define RT5651_JD_SPR_MASK … #define RT5651_JD_SPR_SFT … #define RT5651_JD_SPR_DIS … #define RT5651_JD_SPR_EN … #define RT5651_JD_SPR_TRG_MASK … #define RT5651_JD_SPR_TRG_SFT … #define RT5651_JD_SPR_TRG_LO … #define RT5651_JD_SPR_TRG_HI … #define RT5651_JD_LO_MASK … #define RT5651_JD_LO_SFT … #define RT5651_JD_LO_DIS … #define RT5651_JD_LO_EN … #define RT5651_JD_LO_TRG_MASK … #define RT5651_JD_LO_TRG_SFT … #define RT5651_JD_LO_TRG_LO … #define RT5651_JD_LO_TRG_HI … /* Jack Detect Control 2 (0xbc) */ #define RT5651_JD_TRG_SEL_MASK … #define RT5651_JD_TRG_SEL_SFT … #define RT5651_JD_TRG_SEL_GPIO … #define RT5651_JD_TRG_SEL_JD1_1 … #define RT5651_JD_TRG_SEL_JD1_2 … #define RT5651_JD_TRG_SEL_JD2 … #define RT5651_JD_TRG_SEL_JD3 … #define RT5651_JD3_IRQ_EN … #define RT5651_JD3_IRQ_EN_SFT … #define RT5651_JD3_EN_STKY … #define RT5651_JD3_EN_STKY_SFT … #define RT5651_JD3_INV … #define RT5651_JD3_INV_SFT … /* IRQ Control 1 (0xbd) */ #define RT5651_IRQ_JD_MASK … #define RT5651_IRQ_JD_SFT … #define RT5651_IRQ_JD_BP … #define RT5651_IRQ_JD_NOR … #define RT5651_JD_STKY_MASK … #define RT5651_JD_STKY_SFT … #define RT5651_JD_STKY_DIS … #define RT5651_JD_STKY_EN … #define RT5651_JD_P_MASK … #define RT5651_JD_P_SFT … #define RT5651_JD_P_NOR … #define RT5651_JD_P_INV … #define RT5651_JD1_1_IRQ_EN … #define RT5651_JD1_1_IRQ_EN_SFT … #define RT5651_JD1_1_EN_STKY … #define RT5651_JD1_1_EN_STKY_SFT … #define RT5651_JD1_1_INV … #define RT5651_JD1_1_INV_SFT … #define RT5651_JD1_2_IRQ_EN … #define RT5651_JD1_2_IRQ_EN_SFT … #define RT5651_JD1_2_EN_STKY … #define RT5651_JD1_2_EN_STKY_SFT … #define RT5651_JD1_2_INV … #define RT5651_JD1_2_INV_SFT … #define RT5651_JD2_IRQ_EN … #define RT5651_JD2_IRQ_EN_SFT … #define RT5651_JD2_EN_STKY … #define RT5651_JD2_EN_STKY_SFT … #define RT5651_JD2_INV … #define RT5651_JD2_INV_SFT … /* IRQ Control 2 (0xbe) */ #define RT5651_IRQ_MB1_OC_MASK … #define RT5651_IRQ_MB1_OC_SFT … #define RT5651_IRQ_MB1_OC_BP … #define RT5651_IRQ_MB1_OC_NOR … #define RT5651_MB1_OC_STKY_MASK … #define RT5651_MB1_OC_STKY_SFT … #define RT5651_MB1_OC_STKY_DIS … #define RT5651_MB1_OC_STKY_EN … #define RT5651_MB1_OC_P_MASK … #define RT5651_MB1_OC_P_SFT … #define RT5651_MB1_OC_P_NOR … #define RT5651_MB1_OC_P_INV … #define RT5651_MB2_OC_P_MASK … #define RT5651_MB1_OC_CLR … #define RT5651_MB1_OC_CLR_SFT … #define RT5651_STA_GPIO8 … #define RT5651_STA_GPIO8_BIT … /* Internal Status and GPIO status (0xbf) */ #define RT5651_STA_JD3 … #define RT5651_STA_JD3_BIT … #define RT5651_STA_JD2 … #define RT5651_STA_JD2_BIT … #define RT5651_STA_JD1_2 … #define RT5651_STA_JD1_2_BIT … #define RT5651_STA_JD1_1 … #define RT5651_STA_JD1_1_BIT … #define RT5651_STA_GP7 … #define RT5651_STA_GP7_BIT … #define RT5651_STA_GP6 … #define RT5651_STA_GP6_BIT … #define RT5651_STA_GP5 … #define RT5651_STA_GP5_BIT … #define RT5651_STA_GP1 … #define RT5651_STA_GP1_BIT … #define RT5651_STA_GP2 … #define RT5651_STA_GP2_BIT … #define RT5651_STA_GP3 … #define RT5651_STA_GP3_BIT … #define RT5651_STA_GP4 … #define RT5651_STA_GP4_BIT … #define RT5651_STA_GP_JD … #define RT5651_STA_GP_JD_BIT … /* GPIO Control 1 (0xc0) */ #define RT5651_GP1_PIN_MASK … #define RT5651_GP1_PIN_SFT … #define RT5651_GP1_PIN_GPIO1 … #define RT5651_GP1_PIN_IRQ … #define RT5651_GP2_PIN_MASK … #define RT5651_GP2_PIN_SFT … #define RT5651_GP2_PIN_GPIO2 … #define RT5651_GP2_PIN_DMIC1_SCL … #define RT5651_GPIO_M_MASK … #define RT5651_GPIO_M_SFT … #define RT5651_GPIO_M_FLT … #define RT5651_GPIO_M_PH … #define RT5651_I2S2_SEL_MASK … #define RT5651_I2S2_SEL_SFT … #define RT5651_I2S2_SEL_I2S … #define RT5651_I2S2_SEL_GPIO … #define RT5651_GP5_PIN_MASK … #define RT5651_GP5_PIN_SFT … #define RT5651_GP5_PIN_GPIO5 … #define RT5651_GP5_PIN_IRQ … #define RT5651_GP6_PIN_MASK … #define RT5651_GP6_PIN_SFT … #define RT5651_GP6_PIN_GPIO6 … #define RT5651_GP6_PIN_DMIC_SDA … #define RT5651_GP7_PIN_MASK … #define RT5651_GP7_PIN_SFT … #define RT5651_GP7_PIN_GPIO7 … #define RT5651_GP7_PIN_IRQ … #define RT5651_GP8_PIN_MASK … #define RT5651_GP8_PIN_SFT … #define RT5651_GP8_PIN_GPIO8 … #define RT5651_GP8_PIN_DMIC_SDA … #define RT5651_GPIO_PDM_SEL_MASK … #define RT5651_GPIO_PDM_SEL_SFT … #define RT5651_GPIO_PDM_SEL_GPIO … #define RT5651_GPIO_PDM_SEL_PDM … /* GPIO Control 2 (0xc1) */ #define RT5651_GP5_DR_MASK … #define RT5651_GP5_DR_SFT … #define RT5651_GP5_DR_IN … #define RT5651_GP5_DR_OUT … #define RT5651_GP5_OUT_MASK … #define RT5651_GP5_OUT_SFT … #define RT5651_GP5_OUT_LO … #define RT5651_GP5_OUT_HI … #define RT5651_GP5_P_MASK … #define RT5651_GP5_P_SFT … #define RT5651_GP5_P_NOR … #define RT5651_GP5_P_INV … #define RT5651_GP4_DR_MASK … #define RT5651_GP4_DR_SFT … #define RT5651_GP4_DR_IN … #define RT5651_GP4_DR_OUT … #define RT5651_GP4_OUT_MASK … #define RT5651_GP4_OUT_SFT … #define RT5651_GP4_OUT_LO … #define RT5651_GP4_OUT_HI … #define RT5651_GP4_P_MASK … #define RT5651_GP4_P_SFT … #define RT5651_GP4_P_NOR … #define RT5651_GP4_P_INV … #define RT5651_GP3_DR_MASK … #define RT5651_GP3_DR_SFT … #define RT5651_GP3_DR_IN … #define RT5651_GP3_DR_OUT … #define RT5651_GP3_OUT_MASK … #define RT5651_GP3_OUT_SFT … #define RT5651_GP3_OUT_LO … #define RT5651_GP3_OUT_HI … #define RT5651_GP3_P_MASK … #define RT5651_GP3_P_SFT … #define RT5651_GP3_P_NOR … #define RT5651_GP3_P_INV … #define RT5651_GP2_DR_MASK … #define RT5651_GP2_DR_SFT … #define RT5651_GP2_DR_IN … #define RT5651_GP2_DR_OUT … #define RT5651_GP2_OUT_MASK … #define RT5651_GP2_OUT_SFT … #define RT5651_GP2_OUT_LO … #define RT5651_GP2_OUT_HI … #define RT5651_GP2_P_MASK … #define RT5651_GP2_P_SFT … #define RT5651_GP2_P_NOR … #define RT5651_GP2_P_INV … #define RT5651_GP1_DR_MASK … #define RT5651_GP1_DR_SFT … #define RT5651_GP1_DR_IN … #define RT5651_GP1_DR_OUT … #define RT5651_GP1_OUT_MASK … #define RT5651_GP1_OUT_SFT … #define RT5651_GP1_OUT_LO … #define RT5651_GP1_OUT_HI … #define RT5651_GP1_P_MASK … #define RT5651_GP1_P_SFT … #define RT5651_GP1_P_NOR … #define RT5651_GP1_P_INV … /* GPIO Control 3 (0xc2) */ #define RT5651_GP8_DR_MASK … #define RT5651_GP8_DR_SFT … #define RT5651_GP8_DR_IN … #define RT5651_GP8_DR_OUT … #define RT5651_GP8_OUT_MASK … #define RT5651_GP8_OUT_SFT … #define RT5651_GP8_OUT_LO … #define RT5651_GP8_OUT_HI … #define RT5651_GP8_P_MASK … #define RT5651_GP8_P_SFT … #define RT5651_GP8_P_NOR … #define RT5651_GP8_P_INV … #define RT5651_GP7_DR_MASK … #define RT5651_GP7_DR_SFT … #define RT5651_GP7_DR_IN … #define RT5651_GP7_DR_OUT … #define RT5651_GP7_OUT_MASK … #define RT5651_GP7_OUT_SFT … #define RT5651_GP7_OUT_LO … #define RT5651_GP7_OUT_HI … #define RT5651_GP7_P_MASK … #define RT5651_GP7_P_SFT … #define RT5651_GP7_P_NOR … #define RT5651_GP7_P_INV … #define RT5651_GP6_DR_MASK … #define RT5651_GP6_DR_SFT … #define RT5651_GP6_DR_IN … #define RT5651_GP6_DR_OUT … #define RT5651_GP6_OUT_MASK … #define RT5651_GP6_OUT_SFT … #define RT5651_GP6_OUT_LO … #define RT5651_GP6_OUT_HI … #define RT5651_GP6_P_MASK … #define RT5651_GP6_P_SFT … #define RT5651_GP6_P_NOR … #define RT5651_GP6_P_INV … /* Scramble Control (0xce) */ #define RT5651_SCB_SWAP_MASK … #define RT5651_SCB_SWAP_SFT … #define RT5651_SCB_SWAP_DIS … #define RT5651_SCB_SWAP_EN … #define RT5651_SCB_MASK … #define RT5651_SCB_SFT … #define RT5651_SCB_DIS … #define RT5651_SCB_EN … /* Baseback Control (0xcf) */ #define RT5651_BB_MASK … #define RT5651_BB_SFT … #define RT5651_BB_DIS … #define RT5651_BB_EN … #define RT5651_BB_CT_MASK … #define RT5651_BB_CT_SFT … #define RT5651_BB_CT_A … #define RT5651_BB_CT_B … #define RT5651_BB_CT_C … #define RT5651_BB_CT_D … #define RT5651_M_BB_L_MASK … #define RT5651_M_BB_L_SFT … #define RT5651_M_BB_R_MASK … #define RT5651_M_BB_R_SFT … #define RT5651_M_BB_HPF_L_MASK … #define RT5651_M_BB_HPF_L_SFT … #define RT5651_M_BB_HPF_R_MASK … #define RT5651_M_BB_HPF_R_SFT … #define RT5651_G_BB_BST_MASK … #define RT5651_G_BB_BST_SFT … /* MP3 Plus Control 1 (0xd0) */ #define RT5651_M_MP3_L_MASK … #define RT5651_M_MP3_L_SFT … #define RT5651_M_MP3_R_MASK … #define RT5651_M_MP3_R_SFT … #define RT5651_M_MP3_MASK … #define RT5651_M_MP3_SFT … #define RT5651_M_MP3_DIS … #define RT5651_M_MP3_EN … #define RT5651_EG_MP3_MASK … #define RT5651_EG_MP3_SFT … #define RT5651_MP3_HLP_MASK … #define RT5651_MP3_HLP_SFT … #define RT5651_MP3_HLP_DIS … #define RT5651_MP3_HLP_EN … #define RT5651_M_MP3_ORG_L_MASK … #define RT5651_M_MP3_ORG_L_SFT … #define RT5651_M_MP3_ORG_R_MASK … #define RT5651_M_MP3_ORG_R_SFT … /* MP3 Plus Control 2 (0xd1) */ #define RT5651_MP3_WT_MASK … #define RT5651_MP3_WT_SFT … #define RT5651_MP3_WT_1_4 … #define RT5651_MP3_WT_1_2 … #define RT5651_OG_MP3_MASK … #define RT5651_OG_MP3_SFT … #define RT5651_HG_MP3_MASK … #define RT5651_HG_MP3_SFT … /* 3D HP Control 1 (0xd2) */ #define RT5651_3D_CF_MASK … #define RT5651_3D_CF_SFT … #define RT5651_3D_CF_DIS … #define RT5651_3D_CF_EN … #define RT5651_3D_HP_MASK … #define RT5651_3D_HP_SFT … #define RT5651_3D_HP_DIS … #define RT5651_3D_HP_EN … #define RT5651_3D_BT_MASK … #define RT5651_3D_BT_SFT … #define RT5651_3D_BT_DIS … #define RT5651_3D_BT_EN … #define RT5651_3D_1F_MIX_MASK … #define RT5651_3D_1F_MIX_SFT … #define RT5651_3D_HP_M_MASK … #define RT5651_3D_HP_M_SFT … #define RT5651_3D_HP_M_SUR … #define RT5651_3D_HP_M_FRO … #define RT5651_M_3D_HRTF_MASK … #define RT5651_M_3D_HRTF_SFT … #define RT5651_M_3D_D2H_MASK … #define RT5651_M_3D_D2H_SFT … #define RT5651_M_3D_D2R_MASK … #define RT5651_M_3D_D2R_SFT … #define RT5651_M_3D_REVB_MASK … #define RT5651_M_3D_REVB_SFT … /* Adjustable high pass filter control 1 (0xd3) */ #define RT5651_2ND_HPF_MASK … #define RT5651_2ND_HPF_SFT … #define RT5651_2ND_HPF_DIS … #define RT5651_2ND_HPF_EN … #define RT5651_HPF_CF_L_MASK … #define RT5651_HPF_CF_L_SFT … #define RT5651_HPF_CF_R_MASK … #define RT5651_HPF_CF_R_SFT … #define RT5651_ZD_T_MASK … #define RT5651_ZD_T_SFT … #define RT5651_ZD_F_MASK … #define RT5651_ZD_F_SFT … #define RT5651_ZD_F_IM … #define RT5651_ZD_F_ZC_IM … #define RT5651_ZD_F_ZC_IOD … #define RT5651_ZD_F_UN … /* Adjustable high pass filter control 2 (0xd4) */ #define RT5651_HPF_CF_L_NUM_MASK … #define RT5651_HPF_CF_L_NUM_SFT … #define RT5651_HPF_CF_R_NUM_MASK … #define RT5651_HPF_CF_R_NUM_SFT … /* HP calibration control and Amp detection (0xd6) */ #define RT5651_SI_DAC_MASK … #define RT5651_SI_DAC_SFT … #define RT5651_SI_DAC_AUTO … #define RT5651_SI_DAC_TEST … #define RT5651_DC_CAL_M_MASK … #define RT5651_DC_CAL_M_SFT … #define RT5651_DC_CAL_M_NOR … #define RT5651_DC_CAL_M_CAL … #define RT5651_DC_CAL_MASK … #define RT5651_DC_CAL_SFT … #define RT5651_DC_CAL_DIS … #define RT5651_DC_CAL_EN … #define RT5651_HPD_RCV_MASK … #define RT5651_HPD_RCV_SFT … #define RT5651_HPD_PS_MASK … #define RT5651_HPD_PS_SFT … #define RT5651_HPD_PS_DIS … #define RT5651_HPD_PS_EN … #define RT5651_CAL_M_MASK … #define RT5651_CAL_M_SFT … #define RT5651_CAL_M_DEP … #define RT5651_CAL_M_CAL … #define RT5651_CAL_MASK … #define RT5651_CAL_SFT … #define RT5651_CAL_DIS … #define RT5651_CAL_EN … #define RT5651_CAL_TEST_MASK … #define RT5651_CAL_TEST_SFT … #define RT5651_CAL_TEST_DIS … #define RT5651_CAL_TEST_EN … #define RT5651_CAL_P_MASK … #define RT5651_CAL_P_SFT … #define RT5651_CAL_P_NONE … #define RT5651_CAL_P_CAL … #define RT5651_CAL_P_DAC_CAL … /* Soft volume and zero cross control 1 (0xd9) */ #define RT5651_SV_MASK … #define RT5651_SV_SFT … #define RT5651_SV_DIS … #define RT5651_SV_EN … #define RT5651_OUT_SV_MASK … #define RT5651_OUT_SV_SFT … #define RT5651_OUT_SV_DIS … #define RT5651_OUT_SV_EN … #define RT5651_HP_SV_MASK … #define RT5651_HP_SV_SFT … #define RT5651_HP_SV_DIS … #define RT5651_HP_SV_EN … #define RT5651_ZCD_DIG_MASK … #define RT5651_ZCD_DIG_SFT … #define RT5651_ZCD_DIG_DIS … #define RT5651_ZCD_DIG_EN … #define RT5651_ZCD_MASK … #define RT5651_ZCD_SFT … #define RT5651_ZCD_PD … #define RT5651_ZCD_PU … #define RT5651_M_ZCD_MASK … #define RT5651_M_ZCD_SFT … #define RT5651_M_ZCD_OM_L … #define RT5651_M_ZCD_OM_R … #define RT5651_M_ZCD_RM_L … #define RT5651_M_ZCD_RM_R … #define RT5651_SV_DLY_MASK … #define RT5651_SV_DLY_SFT … /* Soft volume and zero cross control 2 (0xda) */ #define RT5651_ZCD_HP_MASK … #define RT5651_ZCD_HP_SFT … #define RT5651_ZCD_HP_DIS … #define RT5651_ZCD_HP_EN … /* Digital Misc Control (0xfa) */ #define RT5651_I2S2_MS_SP_MASK … #define RT5651_I2S2_MS_SP_SEL … #define RT5651_I2S2_MS_SP_64 … #define RT5651_I2S2_MS_SP_50 … #define RT5651_CLK_DET_EN … #define RT5651_CLK_DET_EN_SFT … #define RT5651_AMP_DET_EN … #define RT5651_AMP_DET_EN_SFT … #define RT5651_D_GATE_EN … #define RT5651_D_GATE_EN_SFT … /* Codec Private Register definition */ /* MIC Over current threshold scale factor (0x15) */ #define RT5651_MIC_OVCD_SF_MASK … #define RT5651_MIC_OVCD_SF_SFT … #define RT5651_MIC_OVCD_SF_0P5 … #define RT5651_MIC_OVCD_SF_0P75 … #define RT5651_MIC_OVCD_SF_1P0 … #define RT5651_MIC_OVCD_SF_1P5 … /* 3D Speaker Control (0x63) */ #define RT5651_3D_SPK_MASK … #define RT5651_3D_SPK_SFT … #define RT5651_3D_SPK_DIS … #define RT5651_3D_SPK_EN … #define RT5651_3D_SPK_M_MASK … #define RT5651_3D_SPK_M_SFT … #define RT5651_3D_SPK_CG_MASK … #define RT5651_3D_SPK_CG_SFT … #define RT5651_3D_SPK_SG_MASK … #define RT5651_3D_SPK_SG_SFT … /* Wind Noise Detection Control 1 (0x6c) */ #define RT5651_WND_MASK … #define RT5651_WND_SFT … #define RT5651_WND_DIS … #define RT5651_WND_EN … /* Wind Noise Detection Control 2 (0x6d) */ #define RT5651_WND_FC_NW_MASK … #define RT5651_WND_FC_NW_SFT … #define RT5651_WND_FC_WK_MASK … #define RT5651_WND_FC_WK_SFT … /* Wind Noise Detection Control 3 (0x6e) */ #define RT5651_HPF_FC_MASK … #define RT5651_HPF_FC_SFT … #define RT5651_WND_FC_ST_MASK … #define RT5651_WND_FC_ST_SFT … /* Wind Noise Detection Control 4 (0x6f) */ #define RT5651_WND_TH_LO_MASK … #define RT5651_WND_TH_LO_SFT … /* Wind Noise Detection Control 5 (0x70) */ #define RT5651_WND_TH_HI_MASK … #define RT5651_WND_TH_HI_SFT … /* Wind Noise Detection Control 8 (0x73) */ #define RT5651_WND_WIND_MASK … #define RT5651_WND_WIND_SFT … #define RT5651_WND_STRONG_MASK … #define RT5651_WND_STRONG_SFT … enum { … }; /* Dipole Speaker Interface (0x75) */ #define RT5651_DP_ATT_MASK … #define RT5651_DP_ATT_SFT … #define RT5651_DP_SPK_MASK … #define RT5651_DP_SPK_SFT … #define RT5651_DP_SPK_DIS … #define RT5651_DP_SPK_EN … /* EQ Pre Volume Control (0xb3) */ #define RT5651_EQ_PRE_VOL_MASK … #define RT5651_EQ_PRE_VOL_SFT … /* EQ Post Volume Control (0xb4) */ #define RT5651_EQ_PST_VOL_MASK … #define RT5651_EQ_PST_VOL_SFT … /* System Clock Source */ enum { … }; /* PLL1 Source */ enum { … }; enum { … }; struct rt5651_pll_code { … }; struct rt5651_priv { … }; #endif /* __RT5651_H__ */
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