/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver * * Copyright 2016 Realtek Microelectronics * Author: Bard Liao <[email protected]> */ #ifndef __RT5665_H__ #define __RT5665_H__ #include <sound/rt5665.h> #define DEVICE_ID … /* Info */ #define RT5665_RESET … #define RT5665_VENDOR_ID … #define RT5665_VENDOR_ID_1 … #define RT5665_DEVICE_ID … /* I/O - Output */ #define RT5665_LOUT … #define RT5665_HP_CTRL_1 … #define RT5665_HP_CTRL_2 … #define RT5665_MONO_OUT … #define RT5665_HPL_GAIN … #define RT5665_HPR_GAIN … #define RT5665_MONO_GAIN … /* I/O - Input */ #define RT5665_CAL_BST_CTRL … #define RT5665_CBJ_BST_CTRL … #define RT5665_IN1_IN2 … #define RT5665_IN3_IN4 … #define RT5665_INL1_INR1_VOL … /* I/O - Speaker */ #define RT5665_EJD_CTRL_1 … #define RT5665_EJD_CTRL_2 … #define RT5665_EJD_CTRL_3 … #define RT5665_EJD_CTRL_4 … #define RT5665_EJD_CTRL_5 … #define RT5665_EJD_CTRL_6 … #define RT5665_EJD_CTRL_7 … /* I/O - ADC/DAC/DMIC */ #define RT5665_DAC2_CTRL … #define RT5665_DAC2_DIG_VOL … #define RT5665_DAC1_DIG_VOL … #define RT5665_DAC3_DIG_VOL … #define RT5665_DAC3_CTRL … #define RT5665_STO1_ADC_DIG_VOL … #define RT5665_MONO_ADC_DIG_VOL … #define RT5665_STO2_ADC_DIG_VOL … #define RT5665_STO1_ADC_BOOST … #define RT5665_MONO_ADC_BOOST … #define RT5665_STO2_ADC_BOOST … #define RT5665_HP_IMP_GAIN_1 … #define RT5665_HP_IMP_GAIN_2 … /* Mixer - D-D */ #define RT5665_STO1_ADC_MIXER … #define RT5665_MONO_ADC_MIXER … #define RT5665_STO2_ADC_MIXER … #define RT5665_AD_DA_MIXER … #define RT5665_STO1_DAC_MIXER … #define RT5665_MONO_DAC_MIXER … #define RT5665_STO2_DAC_MIXER … #define RT5665_A_DAC1_MUX … #define RT5665_A_DAC2_MUX … #define RT5665_DIG_INF2_DATA … #define RT5665_DIG_INF3_DATA … /* Mixer - PDM */ #define RT5665_PDM_OUT_CTRL … #define RT5665_PDM_DATA_CTRL_1 … #define RT5665_PDM_DATA_CTRL_2 … #define RT5665_PDM_DATA_CTRL_3 … #define RT5665_PDM_DATA_CTRL_4 … /* Mixer - ADC */ #define RT5665_REC1_GAIN … #define RT5665_REC1_L1_MIXER … #define RT5665_REC1_L2_MIXER … #define RT5665_REC1_R1_MIXER … #define RT5665_REC1_R2_MIXER … #define RT5665_REC2_GAIN … #define RT5665_REC2_L1_MIXER … #define RT5665_REC2_L2_MIXER … #define RT5665_REC2_R1_MIXER … #define RT5665_REC2_R2_MIXER … #define RT5665_CAL_REC … /* Mixer - DAC */ #define RT5665_ALC_BACK_GAIN … #define RT5665_MONOMIX_GAIN … #define RT5665_MONOMIX_IN_GAIN … #define RT5665_OUT_L_GAIN … #define RT5665_OUT_L_MIXER … #define RT5665_OUT_R_GAIN … #define RT5665_OUT_R_MIXER … #define RT5665_LOUT_MIXER … /* Power */ #define RT5665_PWR_DIG_1 … #define RT5665_PWR_DIG_2 … #define RT5665_PWR_ANLG_1 … #define RT5665_PWR_ANLG_2 … #define RT5665_PWR_ANLG_3 … #define RT5665_PWR_MIXER … #define RT5665_PWR_VOL … /* Clock Detect */ #define RT5665_CLK_DET … /* Filter */ #define RT5665_HPF_CTRL1 … /* DMIC */ #define RT5665_DMIC_CTRL_1 … #define RT5665_DMIC_CTRL_2 … /* Format - ADC/DAC */ #define RT5665_I2S1_SDP … #define RT5665_I2S2_SDP … #define RT5665_I2S3_SDP … #define RT5665_ADDA_CLK_1 … #define RT5665_ADDA_CLK_2 … #define RT5665_I2S1_F_DIV_CTRL_1 … #define RT5665_I2S1_F_DIV_CTRL_2 … /* Format - TDM Control */ #define RT5665_TDM_CTRL_1 … #define RT5665_TDM_CTRL_2 … #define RT5665_TDM_CTRL_3 … #define RT5665_TDM_CTRL_4 … #define RT5665_TDM_CTRL_5 … #define RT5665_TDM_CTRL_6 … #define RT5665_TDM_CTRL_7 … #define RT5665_TDM_CTRL_8 … /* Function - Analog */ #define RT5665_GLB_CLK … #define RT5665_PLL_CTRL_1 … #define RT5665_PLL_CTRL_2 … #define RT5665_ASRC_1 … #define RT5665_ASRC_2 … #define RT5665_ASRC_3 … #define RT5665_ASRC_4 … #define RT5665_ASRC_5 … #define RT5665_ASRC_6 … #define RT5665_ASRC_7 … #define RT5665_ASRC_8 … #define RT5665_ASRC_9 … #define RT5665_ASRC_10 … #define RT5665_DEPOP_1 … #define RT5665_DEPOP_2 … #define RT5665_HP_CHARGE_PUMP_1 … #define RT5665_HP_CHARGE_PUMP_2 … #define RT5665_MICBIAS_1 … #define RT5665_MICBIAS_2 … #define RT5665_ASRC_12 … #define RT5665_ASRC_13 … #define RT5665_ASRC_14 … #define RT5665_RC_CLK_CTRL … #define RT5665_I2S_M_CLK_CTRL_1 … #define RT5665_I2S2_F_DIV_CTRL_1 … #define RT5665_I2S2_F_DIV_CTRL_2 … #define RT5665_I2S3_F_DIV_CTRL_1 … #define RT5665_I2S3_F_DIV_CTRL_2 … /* Function - Digital */ #define RT5665_EQ_CTRL_1 … #define RT5665_EQ_CTRL_2 … #define RT5665_IRQ_CTRL_1 … #define RT5665_IRQ_CTRL_2 … #define RT5665_IRQ_CTRL_3 … #define RT5665_IRQ_CTRL_4 … #define RT5665_IRQ_CTRL_5 … #define RT5665_IRQ_CTRL_6 … #define RT5665_INT_ST_1 … #define RT5665_GPIO_CTRL_1 … #define RT5665_GPIO_CTRL_2 … #define RT5665_GPIO_CTRL_3 … #define RT5665_GPIO_CTRL_4 … #define RT5665_GPIO_STA … #define RT5665_HP_AMP_DET_CTRL_1 … #define RT5665_HP_AMP_DET_CTRL_2 … #define RT5665_MID_HP_AMP_DET … #define RT5665_LOW_HP_AMP_DET … #define RT5665_SV_ZCD_1 … #define RT5665_SV_ZCD_2 … #define RT5665_IL_CMD_1 … #define RT5665_IL_CMD_2 … #define RT5665_IL_CMD_3 … #define RT5665_IL_CMD_4 … #define RT5665_4BTN_IL_CMD_1 … #define RT5665_4BTN_IL_CMD_2 … #define RT5665_4BTN_IL_CMD_3 … #define RT5665_PSV_IL_CMD_1 … #define RT5665_ADC_STO1_HP_CTRL_1 … #define RT5665_ADC_STO1_HP_CTRL_2 … #define RT5665_ADC_MONO_HP_CTRL_1 … #define RT5665_ADC_MONO_HP_CTRL_2 … #define RT5665_ADC_STO2_HP_CTRL_1 … #define RT5665_ADC_STO2_HP_CTRL_2 … #define RT5665_AJD1_CTRL … #define RT5665_JD1_THD … #define RT5665_JD2_THD … #define RT5665_JD_CTRL_1 … #define RT5665_JD_CTRL_2 … #define RT5665_JD_CTRL_3 … /* General Control */ #define RT5665_DIG_MISC … #define RT5665_DUMMY_2 … #define RT5665_DUMMY_3 … #define RT5665_DAC_ADC_DIG_VOL1 … #define RT5665_DAC_ADC_DIG_VOL2 … #define RT5665_BIAS_CUR_CTRL_1 … #define RT5665_BIAS_CUR_CTRL_2 … #define RT5665_BIAS_CUR_CTRL_3 … #define RT5665_BIAS_CUR_CTRL_4 … #define RT5665_BIAS_CUR_CTRL_5 … #define RT5665_BIAS_CUR_CTRL_6 … #define RT5665_BIAS_CUR_CTRL_7 … #define RT5665_BIAS_CUR_CTRL_8 … #define RT5665_BIAS_CUR_CTRL_9 … #define RT5665_BIAS_CUR_CTRL_10 … #define RT5665_VREF_REC_OP_FB_CAP_CTRL … #define RT5665_CHARGE_PUMP_1 … #define RT5665_DIG_IN_CTRL_1 … #define RT5665_DIG_IN_CTRL_2 … #define RT5665_PAD_DRIVING_CTRL … #define RT5665_SOFT_RAMP_DEPOP … #define RT5665_PLL … #define RT5665_CHOP_DAC … #define RT5665_CHOP_ADC … #define RT5665_CALIB_ADC_CTRL … #define RT5665_VOL_TEST … #define RT5665_TEST_MODE_CTRL_1 … #define RT5665_TEST_MODE_CTRL_2 … #define RT5665_TEST_MODE_CTRL_3 … #define RT5665_TEST_MODE_CTRL_4 … #define RT5665_BASSBACK_CTRL … #define RT5665_STO_NG2_CTRL_1 … #define RT5665_STO_NG2_CTRL_2 … #define RT5665_STO_NG2_CTRL_3 … #define RT5665_STO_NG2_CTRL_4 … #define RT5665_STO_NG2_CTRL_5 … #define RT5665_STO_NG2_CTRL_6 … #define RT5665_STO_NG2_CTRL_7 … #define RT5665_STO_NG2_CTRL_8 … #define RT5665_MONO_NG2_CTRL_1 … #define RT5665_MONO_NG2_CTRL_2 … #define RT5665_MONO_NG2_CTRL_3 … #define RT5665_MONO_NG2_CTRL_4 … #define RT5665_MONO_NG2_CTRL_5 … #define RT5665_MONO_NG2_CTRL_6 … #define RT5665_STO1_DAC_SIL_DET … #define RT5665_MONOL_DAC_SIL_DET … #define RT5665_MONOR_DAC_SIL_DET … #define RT5665_STO2_DAC_SIL_DET … #define RT5665_SIL_PSV_CTRL1 … #define RT5665_SIL_PSV_CTRL2 … #define RT5665_SIL_PSV_CTRL3 … #define RT5665_SIL_PSV_CTRL4 … #define RT5665_SIL_PSV_CTRL5 … #define RT5665_SIL_PSV_CTRL6 … #define RT5665_MONO_AMP_CALIB_CTRL_1 … #define RT5665_MONO_AMP_CALIB_CTRL_2 … #define RT5665_MONO_AMP_CALIB_CTRL_3 … #define RT5665_MONO_AMP_CALIB_CTRL_4 … #define RT5665_MONO_AMP_CALIB_CTRL_5 … #define RT5665_MONO_AMP_CALIB_CTRL_6 … #define RT5665_MONO_AMP_CALIB_CTRL_7 … #define RT5665_MONO_AMP_CALIB_STA1 … #define RT5665_MONO_AMP_CALIB_STA2 … #define RT5665_MONO_AMP_CALIB_STA3 … #define RT5665_MONO_AMP_CALIB_STA4 … #define RT5665_MONO_AMP_CALIB_STA6 … #define RT5665_HP_IMP_SENS_CTRL_01 … #define RT5665_HP_IMP_SENS_CTRL_02 … #define RT5665_HP_IMP_SENS_CTRL_03 … #define RT5665_HP_IMP_SENS_CTRL_04 … #define RT5665_HP_IMP_SENS_CTRL_05 … #define RT5665_HP_IMP_SENS_CTRL_06 … #define RT5665_HP_IMP_SENS_CTRL_07 … #define RT5665_HP_IMP_SENS_CTRL_08 … #define RT5665_HP_IMP_SENS_CTRL_09 … #define RT5665_HP_IMP_SENS_CTRL_10 … #define RT5665_HP_IMP_SENS_CTRL_11 … #define RT5665_HP_IMP_SENS_CTRL_12 … #define RT5665_HP_IMP_SENS_CTRL_13 … #define RT5665_HP_IMP_SENS_CTRL_14 … #define RT5665_HP_IMP_SENS_CTRL_15 … #define RT5665_HP_IMP_SENS_CTRL_16 … #define RT5665_HP_IMP_SENS_CTRL_17 … #define RT5665_HP_IMP_SENS_CTRL_18 … #define RT5665_HP_IMP_SENS_CTRL_19 … #define RT5665_HP_IMP_SENS_CTRL_20 … #define RT5665_HP_IMP_SENS_CTRL_21 … #define RT5665_HP_IMP_SENS_CTRL_22 … #define RT5665_HP_IMP_SENS_CTRL_23 … #define RT5665_HP_IMP_SENS_CTRL_24 … #define RT5665_HP_IMP_SENS_CTRL_25 … #define RT5665_HP_IMP_SENS_CTRL_26 … #define RT5665_HP_IMP_SENS_CTRL_27 … #define RT5665_HP_IMP_SENS_CTRL_28 … #define RT5665_HP_IMP_SENS_CTRL_29 … #define RT5665_HP_IMP_SENS_CTRL_30 … #define RT5665_HP_IMP_SENS_CTRL_31 … #define RT5665_HP_IMP_SENS_CTRL_32 … #define RT5665_HP_IMP_SENS_CTRL_33 … #define RT5665_HP_IMP_SENS_CTRL_34 … #define RT5665_HP_LOGIC_CTRL_1 … #define RT5665_HP_LOGIC_CTRL_2 … #define RT5665_HP_LOGIC_CTRL_3 … #define RT5665_HP_CALIB_CTRL_1 … #define RT5665_HP_CALIB_CTRL_2 … #define RT5665_HP_CALIB_CTRL_3 … #define RT5665_HP_CALIB_CTRL_4 … #define RT5665_HP_CALIB_CTRL_5 … #define RT5665_HP_CALIB_CTRL_6 … #define RT5665_HP_CALIB_CTRL_7 … #define RT5665_HP_CALIB_CTRL_9 … #define RT5665_HP_CALIB_CTRL_10 … #define RT5665_HP_CALIB_CTRL_11 … #define RT5665_HP_CALIB_STA_1 … #define RT5665_HP_CALIB_STA_2 … #define RT5665_HP_CALIB_STA_3 … #define RT5665_HP_CALIB_STA_4 … #define RT5665_HP_CALIB_STA_5 … #define RT5665_HP_CALIB_STA_6 … #define RT5665_HP_CALIB_STA_7 … #define RT5665_HP_CALIB_STA_8 … #define RT5665_HP_CALIB_STA_9 … #define RT5665_HP_CALIB_STA_10 … #define RT5665_HP_CALIB_STA_11 … #define RT5665_PGM_TAB_CTRL1 … #define RT5665_PGM_TAB_CTRL2 … #define RT5665_PGM_TAB_CTRL3 … #define RT5665_PGM_TAB_CTRL4 … #define RT5665_PGM_TAB_CTRL5 … #define RT5665_PGM_TAB_CTRL6 … #define RT5665_PGM_TAB_CTRL7 … #define RT5665_PGM_TAB_CTRL8 … #define RT5665_PGM_TAB_CTRL9 … #define RT5665_SAR_IL_CMD_1 … #define RT5665_SAR_IL_CMD_2 … #define RT5665_SAR_IL_CMD_3 … #define RT5665_SAR_IL_CMD_4 … #define RT5665_SAR_IL_CMD_5 … #define RT5665_SAR_IL_CMD_6 … #define RT5665_SAR_IL_CMD_7 … #define RT5665_SAR_IL_CMD_8 … #define RT5665_SAR_IL_CMD_9 … #define RT5665_SAR_IL_CMD_10 … #define RT5665_SAR_IL_CMD_11 … #define RT5665_SAR_IL_CMD_12 … #define RT5665_DRC1_CTRL_0 … #define RT5665_DRC1_CTRL_1 … #define RT5665_DRC1_CTRL_2 … #define RT5665_DRC1_CTRL_3 … #define RT5665_DRC1_CTRL_4 … #define RT5665_DRC1_CTRL_5 … #define RT5665_DRC1_CTRL_6 … #define RT5665_DRC1_HARD_LMT_CTRL_1 … #define RT5665_DRC1_HARD_LMT_CTRL_2 … #define RT5665_DRC1_PRIV_1 … #define RT5665_DRC1_PRIV_2 … #define RT5665_DRC1_PRIV_3 … #define RT5665_DRC1_PRIV_4 … #define RT5665_DRC1_PRIV_5 … #define RT5665_DRC1_PRIV_6 … #define RT5665_DRC1_PRIV_7 … #define RT5665_DRC1_PRIV_8 … #define RT5665_ALC_PGA_CTRL_1 … #define RT5665_ALC_PGA_CTRL_2 … #define RT5665_ALC_PGA_CTRL_3 … #define RT5665_ALC_PGA_CTRL_4 … #define RT5665_ALC_PGA_CTRL_5 … #define RT5665_ALC_PGA_CTRL_6 … #define RT5665_ALC_PGA_CTRL_7 … #define RT5665_ALC_PGA_CTRL_8 … #define RT5665_ALC_PGA_STA_1 … #define RT5665_ALC_PGA_STA_2 … #define RT5665_ALC_PGA_STA_3 … #define RT5665_EQ_AUTO_RCV_CTRL1 … #define RT5665_EQ_AUTO_RCV_CTRL2 … #define RT5665_EQ_AUTO_RCV_CTRL3 … #define RT5665_EQ_AUTO_RCV_CTRL4 … #define RT5665_EQ_AUTO_RCV_CTRL5 … #define RT5665_EQ_AUTO_RCV_CTRL6 … #define RT5665_EQ_AUTO_RCV_CTRL7 … #define RT5665_EQ_AUTO_RCV_CTRL8 … #define RT5665_EQ_AUTO_RCV_CTRL9 … #define RT5665_EQ_AUTO_RCV_CTRL10 … #define RT5665_EQ_AUTO_RCV_CTRL11 … #define RT5665_EQ_AUTO_RCV_CTRL12 … #define RT5665_EQ_AUTO_RCV_CTRL13 … #define RT5665_ADC_L_EQ_LPF1_A1 … #define RT5665_R_EQ_LPF1_A1 … #define RT5665_L_EQ_LPF1_H0 … #define RT5665_R_EQ_LPF1_H0 … #define RT5665_L_EQ_BPF1_A1 … #define RT5665_R_EQ_BPF1_A1 … #define RT5665_L_EQ_BPF1_A2 … #define RT5665_R_EQ_BPF1_A2 … #define RT5665_L_EQ_BPF1_H0 … #define RT5665_R_EQ_BPF1_H0 … #define RT5665_L_EQ_BPF2_A1 … #define RT5665_R_EQ_BPF2_A1 … #define RT5665_L_EQ_BPF2_A2 … #define RT5665_R_EQ_BPF2_A2 … #define RT5665_L_EQ_BPF2_H0 … #define RT5665_R_EQ_BPF2_H0 … #define RT5665_L_EQ_BPF3_A1 … #define RT5665_R_EQ_BPF3_A1 … #define RT5665_L_EQ_BPF3_A2 … #define RT5665_R_EQ_BPF3_A2 … #define RT5665_L_EQ_BPF3_H0 … #define RT5665_R_EQ_BPF3_H0 … #define RT5665_L_EQ_BPF4_A1 … #define RT5665_R_EQ_BPF4_A1 … #define RT5665_L_EQ_BPF4_A2 … #define RT5665_R_EQ_BPF4_A2 … #define RT5665_L_EQ_BPF4_H0 … #define RT5665_R_EQ_BPF4_H0 … #define RT5665_L_EQ_HPF1_A1 … #define RT5665_R_EQ_HPF1_A1 … #define RT5665_L_EQ_HPF1_H0 … #define RT5665_R_EQ_HPF1_H0 … #define RT5665_L_EQ_PRE_VOL … #define RT5665_R_EQ_PRE_VOL … #define RT5665_L_EQ_POST_VOL … #define RT5665_R_EQ_POST_VOL … #define RT5665_SCAN_MODE_CTRL … #define RT5665_I2C_MODE … /* global definition */ #define RT5665_L_MUTE … #define RT5665_L_MUTE_SFT … #define RT5665_VOL_L_MUTE … #define RT5665_VOL_L_SFT … #define RT5665_R_MUTE … #define RT5665_R_MUTE_SFT … #define RT5665_VOL_R_MUTE … #define RT5665_VOL_R_SFT … #define RT5665_L_VOL_MASK … #define RT5665_L_VOL_SFT … #define RT5665_R_VOL_MASK … #define RT5665_R_VOL_SFT … /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ #define RT5665_G_HP … #define RT5665_G_HP_SFT … #define RT5665_G_STO_DA_DMIX … #define RT5665_G_STO_DA_SFT … /* CBJ Control (0x000b) */ #define RT5665_BST_CBJ_MASK … #define RT5665_BST_CBJ_SFT … /* IN1/IN2 Control (0x000c) */ #define RT5665_IN1_DF_MASK … #define RT5665_IN1_DF … #define RT5665_BST1_MASK … #define RT5665_BST1_SFT … #define RT5665_IN2_DF_MASK … #define RT5665_IN2_DF … #define RT5665_BST2_MASK … #define RT5665_BST2_SFT … /* IN3/IN4 Control (0x000d) */ #define RT5665_IN3_DF_MASK … #define RT5665_IN3_DF … #define RT5665_BST3_MASK … #define RT5665_BST3_SFT … #define RT5665_IN4_DF_MASK … #define RT5665_IN4_DF … #define RT5665_BST4_MASK … #define RT5665_BST4_SFT … /* INL and INR Volume Control (0x000f) */ #define RT5665_INL_VOL_MASK … #define RT5665_INL_VOL_SFT … #define RT5665_INR_VOL_MASK … #define RT5665_INR_VOL_SFT … /* Embeeded Jack and Type Detection Control 1 (0x0010) */ #define RT5665_EMB_JD_EN … #define RT5665_EMB_JD_EN_SFT … #define RT5665_JD_MODE … #define RT5665_JD_MODE_SFT … #define RT5665_POLA_EXT_JD_MASK … #define RT5665_POLA_EXT_JD_LOW … #define RT5665_POLA_EXT_JD_HIGH … #define RT5665_EXT_JD_DIG … #define RT5665_POL_FAST_OFF_MASK … #define RT5665_POL_FAST_OFF_HIGH … #define RT5665_POL_FAST_OFF_LOW … #define RT5665_VREF_POW_MASK … #define RT5665_VREF_POW_FSM … #define RT5665_VREF_POW_REG … #define RT5665_MB1_PATH_MASK … #define RT5665_CTRL_MB1_REG … #define RT5665_CTRL_MB1_FSM … #define RT5665_MB2_PATH_MASK … #define RT5665_CTRL_MB2_REG … #define RT5665_CTRL_MB2_FSM … #define RT5665_TRIG_JD_MASK … #define RT5665_TRIG_JD_HIGH … #define RT5665_TRIG_JD_LOW … /* Embeeded Jack and Type Detection Control 2 (0x0011) */ #define RT5665_EXT_JD_SRC … #define RT5665_EXT_JD_SRC_SFT … #define RT5665_EXT_JD_SRC_GPIO_JD1 … #define RT5665_EXT_JD_SRC_GPIO_JD2 … #define RT5665_EXT_JD_SRC_JD1_1 … #define RT5665_EXT_JD_SRC_JD1_2 … #define RT5665_EXT_JD_SRC_JD2 … #define RT5665_EXT_JD_SRC_JD3 … #define RT5665_EXT_JD_SRC_MANUAL … /* Combo Jack and Type Detection Control 4 (0x0013) */ #define RT5665_SEL_SHT_MID_TON_MASK … #define RT5665_SEL_SHT_MID_TON_2 … #define RT5665_SEL_SHT_MID_TON_3 … #define RT5665_CBJ_JD_TEST_MASK … #define RT5665_CBJ_JD_TEST_NORM … #define RT5665_CBJ_JD_TEST_MODE … /* Slience Detection Control (0x0015) */ #define RT5665_SIL_DET_MASK … #define RT5665_SIL_DET_DIS … #define RT5665_SIL_DET_EN … /* DAC2 Control (0x0017) */ #define RT5665_M_DAC2_L_VOL … #define RT5665_M_DAC2_L_VOL_SFT … #define RT5665_M_DAC2_R_VOL … #define RT5665_M_DAC2_R_VOL_SFT … #define RT5665_DAC_L2_SEL_MASK … #define RT5665_DAC_L2_SEL_SFT … #define RT5665_DAC_R2_SEL_MASK … #define RT5665_DAC_R2_SEL_SFT … /* Sidetone Control (0x0018) */ #define RT5665_ST_SEL_MASK … #define RT5665_ST_SEL_SFT … #define RT5665_ST_EN … #define RT5665_ST_EN_SFT … /* DAC1 Digital Volume (0x0019) */ #define RT5665_DAC_L1_VOL_MASK … #define RT5665_DAC_L1_VOL_SFT … #define RT5665_DAC_R1_VOL_MASK … #define RT5665_DAC_R1_VOL_SFT … /* DAC2 Digital Volume (0x001a) */ #define RT5665_DAC_L2_VOL_MASK … #define RT5665_DAC_L2_VOL_SFT … #define RT5665_DAC_R2_VOL_MASK … #define RT5665_DAC_R2_VOL_SFT … /* DAC3 Control (0x001b) */ #define RT5665_M_DAC3_L_VOL … #define RT5665_M_DAC3_L_VOL_SFT … #define RT5665_M_DAC3_R_VOL … #define RT5665_M_DAC3_R_VOL_SFT … #define RT5665_DAC_L3_SEL_MASK … #define RT5665_DAC_L3_SEL_SFT … #define RT5665_DAC_R3_SEL_MASK … #define RT5665_DAC_R3_SEL_SFT … /* ADC Digital Volume Control (0x001c) */ #define RT5665_ADC_L_VOL_MASK … #define RT5665_ADC_L_VOL_SFT … #define RT5665_ADC_R_VOL_MASK … #define RT5665_ADC_R_VOL_SFT … /* Mono ADC Digital Volume Control (0x001d) */ #define RT5665_MONO_ADC_L_VOL_MASK … #define RT5665_MONO_ADC_L_VOL_SFT … #define RT5665_MONO_ADC_R_VOL_MASK … #define RT5665_MONO_ADC_R_VOL_SFT … /* Stereo1 ADC Boost Gain Control (0x001f) */ #define RT5665_STO1_ADC_L_BST_MASK … #define RT5665_STO1_ADC_L_BST_SFT … #define RT5665_STO1_ADC_R_BST_MASK … #define RT5665_STO1_ADC_R_BST_SFT … /* Mono ADC Boost Gain Control (0x0020) */ #define RT5665_MONO_ADC_L_BST_MASK … #define RT5665_MONO_ADC_L_BST_SFT … #define RT5665_MONO_ADC_R_BST_MASK … #define RT5665_MONO_ADC_R_BST_SFT … /* Stereo1 ADC Boost Gain Control (0x001f) */ #define RT5665_STO2_ADC_L_BST_MASK … #define RT5665_STO2_ADC_L_BST_SFT … #define RT5665_STO2_ADC_R_BST_MASK … #define RT5665_STO2_ADC_R_BST_SFT … /* Stereo1 ADC Mixer Control (0x0026) */ #define RT5665_M_STO1_ADC_L1 … #define RT5665_M_STO1_ADC_L1_SFT … #define RT5665_M_STO1_ADC_L2 … #define RT5665_M_STO1_ADC_L2_SFT … #define RT5665_STO1_ADC1L_SRC_MASK … #define RT5665_STO1_ADC1L_SRC_SFT … #define RT5665_STO1_ADC1_SRC_ADC … #define RT5665_STO1_ADC1_SRC_DACMIX … #define RT5665_STO1_ADC2L_SRC_MASK … #define RT5665_STO1_ADC2L_SRC_SFT … #define RT5665_STO1_ADCL_SRC_MASK … #define RT5665_STO1_ADCL_SRC_SFT … #define RT5665_STO1_DD_L_SRC_MASK … #define RT5665_STO1_DD_L_SRC_SFT … #define RT5665_STO1_DMIC_SRC_MASK … #define RT5665_STO1_DMIC_SRC_SFT … #define RT5665_STO1_DMIC_SRC_DMIC2 … #define RT5665_STO1_DMIC_SRC_DMIC1 … #define RT5665_M_STO1_ADC_R1 … #define RT5665_M_STO1_ADC_R1_SFT … #define RT5665_M_STO1_ADC_R2 … #define RT5665_M_STO1_ADC_R2_SFT … #define RT5665_STO1_ADC1R_SRC_MASK … #define RT5665_STO1_ADC1R_SRC_SFT … #define RT5665_STO1_ADC2R_SRC_MASK … #define RT5665_STO1_ADC2R_SRC_SFT … #define RT5665_STO1_ADCR_SRC_MASK … #define RT5665_STO1_ADCR_SRC_SFT … #define RT5665_STO1_DD_R_SRC_MASK … #define RT5665_STO1_DD_R_SRC_SFT … /* Mono1 ADC Mixer control (0x0027) */ #define RT5665_M_MONO_ADC_L1 … #define RT5665_M_MONO_ADC_L1_SFT … #define RT5665_M_MONO_ADC_L2 … #define RT5665_M_MONO_ADC_L2_SFT … #define RT5665_MONO_ADC_L1_SRC_MASK … #define RT5665_MONO_ADC_L1_SRC_SFT … #define RT5665_MONO_ADC_L2_SRC_MASK … #define RT5665_MONO_ADC_L2_SRC_SFT … #define RT5665_MONO_ADC_L_SRC_MASK … #define RT5665_MONO_ADC_L_SRC_SFT … #define RT5665_MONO_DD_L_SRC_MASK … #define RT5665_MONO_DD_L_SRC_SFT … #define RT5665_MONO_DMIC_L_SRC_MASK … #define RT5665_MONO_DMIC_L_SRC_SFT … #define RT5665_M_MONO_ADC_R1 … #define RT5665_M_MONO_ADC_R1_SFT … #define RT5665_M_MONO_ADC_R2 … #define RT5665_M_MONO_ADC_R2_SFT … #define RT5665_MONO_ADC_R1_SRC_MASK … #define RT5665_MONO_ADC_R1_SRC_SFT … #define RT5665_MONO_ADC_R2_SRC_MASK … #define RT5665_MONO_ADC_R2_SRC_SFT … #define RT5665_MONO_ADC_R_SRC_MASK … #define RT5665_MONO_ADC_R_SRC_SFT … #define RT5665_MONO_DD_R_SRC_MASK … #define RT5665_MONO_DD_R_SRC_SFT … #define RT5665_MONO_DMIC_R_SRC_MASK … #define RT5665_MONO_DMIC_R_SRC_SFT … /* Stereo2 ADC Mixer Control (0x0028) */ #define RT5665_M_STO2_ADC_L1 … #define RT5665_M_STO2_ADC_L1_UN … #define RT5665_M_STO2_ADC_L1_SFT … #define RT5665_M_STO2_ADC_L2 … #define RT5665_M_STO2_ADC_L2_SFT … #define RT5665_STO2_ADC1L_SRC_MASK … #define RT5665_STO2_ADC1L_SRC_SFT … #define RT5665_STO2_ADC1_SRC_ADC … #define RT5665_STO2_ADC1_SRC_DACMIX … #define RT5665_STO2_ADC2L_SRC_MASK … #define RT5665_STO2_ADC2L_SRC_SFT … #define RT5665_STO2_ADCL_SRC_MASK … #define RT5665_STO2_ADCL_SRC_SFT … #define RT5665_STO2_DD_L_SRC_MASK … #define RT5665_STO2_DD_L_SRC_SFT … #define RT5665_STO2_DMIC_SRC_MASK … #define RT5665_STO2_DMIC_SRC_SFT … #define RT5665_STO2_DMIC_SRC_DMIC2 … #define RT5665_STO2_DMIC_SRC_DMIC1 … #define RT5665_M_STO2_ADC_R1 … #define RT5665_M_STO2_ADC_R1_UN … #define RT5665_M_STO2_ADC_R1_SFT … #define RT5665_M_STO2_ADC_R2 … #define RT5665_M_STO2_ADC_R2_SFT … #define RT5665_STO2_ADC1R_SRC_MASK … #define RT5665_STO2_ADC1R_SRC_SFT … #define RT5665_STO2_ADC2R_SRC_MASK … #define RT5665_STO2_ADC2R_SRC_SFT … #define RT5665_STO2_ADCR_SRC_MASK … #define RT5665_STO2_ADCR_SRC_SFT … #define RT5665_STO2_DD_R_SRC_MASK … #define RT5665_STO2_DD_R_SRC_SFT … /* ADC Mixer to DAC Mixer Control (0x0029) */ #define RT5665_M_ADCMIX_L … #define RT5665_M_ADCMIX_L_SFT … #define RT5665_M_DAC1_L … #define RT5665_M_DAC1_L_SFT … #define RT5665_DAC1_R_SEL_MASK … #define RT5665_DAC1_R_SEL_SFT … #define RT5665_DAC1_L_SEL_MASK … #define RT5665_DAC1_L_SEL_SFT … #define RT5665_M_ADCMIX_R … #define RT5665_M_ADCMIX_R_SFT … #define RT5665_M_DAC1_R … #define RT5665_M_DAC1_R_SFT … /* Stereo1 DAC Mixer Control (0x002a) */ #define RT5665_M_DAC_L1_STO_L … #define RT5665_M_DAC_L1_STO_L_SFT … #define RT5665_G_DAC_L1_STO_L_MASK … #define RT5665_G_DAC_L1_STO_L_SFT … #define RT5665_M_DAC_R1_STO_L … #define RT5665_M_DAC_R1_STO_L_SFT … #define RT5665_G_DAC_R1_STO_L_MASK … #define RT5665_G_DAC_R1_STO_L_SFT … #define RT5665_M_DAC_L2_STO_L … #define RT5665_M_DAC_L2_STO_L_SFT … #define RT5665_G_DAC_L2_STO_L_MASK … #define RT5665_G_DAC_L2_STO_L_SFT … #define RT5665_M_DAC_R2_STO_L … #define RT5665_M_DAC_R2_STO_L_SFT … #define RT5665_G_DAC_R2_STO_L_MASK … #define RT5665_G_DAC_R2_STO_L_SFT … #define RT5665_M_DAC_L1_STO_R … #define RT5665_M_DAC_L1_STO_R_SFT … #define RT5665_G_DAC_L1_STO_R_MASK … #define RT5665_G_DAC_L1_STO_R_SFT … #define RT5665_M_DAC_R1_STO_R … #define RT5665_M_DAC_R1_STO_R_SFT … #define RT5665_G_DAC_R1_STO_R_MASK … #define RT5665_G_DAC_R1_STO_R_SFT … #define RT5665_M_DAC_L2_STO_R … #define RT5665_M_DAC_L2_STO_R_SFT … #define RT5665_G_DAC_L2_STO_R_MASK … #define RT5665_G_DAC_L2_STO_R_SFT … #define RT5665_M_DAC_R2_STO_R … #define RT5665_M_DAC_R2_STO_R_SFT … #define RT5665_G_DAC_R2_STO_R_MASK … #define RT5665_G_DAC_R2_STO_R_SFT … /* Mono DAC Mixer Control (0x002b) */ #define RT5665_M_DAC_L1_MONO_L … #define RT5665_M_DAC_L1_MONO_L_SFT … #define RT5665_G_DAC_L1_MONO_L_MASK … #define RT5665_G_DAC_L1_MONO_L_SFT … #define RT5665_M_DAC_R1_MONO_L … #define RT5665_M_DAC_R1_MONO_L_SFT … #define RT5665_G_DAC_R1_MONO_L_MASK … #define RT5665_G_DAC_R1_MONO_L_SFT … #define RT5665_M_DAC_L2_MONO_L … #define RT5665_M_DAC_L2_MONO_L_SFT … #define RT5665_G_DAC_L2_MONO_L_MASK … #define RT5665_G_DAC_L2_MONO_L_SFT … #define RT5665_M_DAC_R2_MONO_L … #define RT5665_M_DAC_R2_MONO_L_SFT … #define RT5665_G_DAC_R2_MONO_L_MASK … #define RT5665_G_DAC_R2_MONO_L_SFT … #define RT5665_M_DAC_L1_MONO_R … #define RT5665_M_DAC_L1_MONO_R_SFT … #define RT5665_G_DAC_L1_MONO_R_MASK … #define RT5665_G_DAC_L1_MONO_R_SFT … #define RT5665_M_DAC_R1_MONO_R … #define RT5665_M_DAC_R1_MONO_R_SFT … #define RT5665_G_DAC_R1_MONO_R_MASK … #define RT5665_G_DAC_R1_MONO_R_SFT … #define RT5665_M_DAC_L2_MONO_R … #define RT5665_M_DAC_L2_MONO_R_SFT … #define RT5665_G_DAC_L2_MONO_R_MASK … #define RT5665_G_DAC_L2_MONO_R_SFT … #define RT5665_M_DAC_R2_MONO_R … #define RT5665_M_DAC_R2_MONO_R_SFT … #define RT5665_G_DAC_R2_MONO_R_MASK … #define RT5665_G_DAC_R2_MONO_R_SFT … /* Stereo2 DAC Mixer Control (0x002c) */ #define RT5665_M_DAC_L1_STO2_L … #define RT5665_M_DAC_L1_STO2_L_SFT … #define RT5665_G_DAC_L1_STO2_L_MASK … #define RT5665_G_DAC_L1_STO2_L_SFT … #define RT5665_M_DAC_L2_STO2_L … #define RT5665_M_DAC_L2_STO2_L_SFT … #define RT5665_G_DAC_L2_STO2_L_MASK … #define RT5665_G_DAC_L2_STO2_L_SFT … #define RT5665_M_DAC_L3_STO2_L … #define RT5665_M_DAC_L3_STO2_L_SFT … #define RT5665_G_DAC_L3_STO2_L_MASK … #define RT5665_G_DAC_L3_STO2_L_SFT … #define RT5665_M_ST_DAC_L1 … #define RT5665_M_ST_DAC_L1_SFT … #define RT5665_M_ST_DAC_R1 … #define RT5665_M_ST_DAC_R1_SFT … #define RT5665_M_DAC_R1_STO2_R … #define RT5665_M_DAC_R1_STO2_R_SFT … #define RT5665_G_DAC_R1_STO2_R_MASK … #define RT5665_G_DAC_R1_STO2_R_SFT … #define RT5665_M_DAC_R2_STO2_R … #define RT5665_M_DAC_R2_STO2_R_SFT … #define RT5665_G_DAC_R2_STO2_R_MASK … #define RT5665_G_DAC_R2_STO2_R_SFT … #define RT5665_M_DAC_R3_STO2_R … #define RT5665_M_DAC_R3_STO2_R_SFT … #define RT5665_G_DAC_R3_STO2_R_MASK … #define RT5665_G_DAC_R3_STO2_R_SFT … /* Analog DAC1 Input Source Control (0x002d) */ #define RT5665_DAC_MIX_L_MASK … #define RT5665_DAC_MIX_L_SFT … #define RT5665_DAC_MIX_R_MASK … #define RT5665_DAC_MIX_R_SFT … #define RT5665_DAC_L1_SRC_MASK … #define RT5665_A_DACL1_SFT … #define RT5665_DAC_R1_SRC_MASK … #define RT5665_A_DACR1_SFT … /* Analog DAC Input Source Control (0x002e) */ #define RT5665_A_DACL2_SEL … #define RT5665_A_DACL2_SFT … #define RT5665_A_DACR2_SEL … #define RT5665_A_DACR2_SFT … /* Digital Interface Data Control (0x002f) */ #define RT5665_IF2_1_ADC_IN_MASK … #define RT5665_IF2_1_ADC_IN_SFT … #define RT5665_IF2_1_DAC_SEL_MASK … #define RT5665_IF2_1_DAC_SEL_SFT … #define RT5665_IF2_1_ADC_SEL_MASK … #define RT5665_IF2_1_ADC_SEL_SFT … #define RT5665_IF2_2_ADC_IN_MASK … #define RT5665_IF2_2_ADC_IN_SFT … #define RT5665_IF2_2_DAC_SEL_MASK … #define RT5665_IF2_2_DAC_SEL_SFT … #define RT5665_IF2_2_ADC_SEL_MASK … #define RT5665_IF2_2_ADC_SEL_SFT … /* Digital Interface Data Control (0x0030) */ #define RT5665_IF3_ADC_IN_MASK … #define RT5665_IF3_ADC_IN_SFT … #define RT5665_IF3_DAC_SEL_MASK … #define RT5665_IF3_DAC_SEL_SFT … #define RT5665_IF3_ADC_SEL_MASK … #define RT5665_IF3_ADC_SEL_SFT … /* PDM Output Control (0x0031) */ #define RT5665_M_PDM1_L … #define RT5665_M_PDM1_L_SFT … #define RT5665_M_PDM1_R … #define RT5665_M_PDM1_R_SFT … #define RT5665_PDM1_L_MASK … #define RT5665_PDM1_L_SFT … #define RT5665_PDM1_R_MASK … #define RT5665_PDM1_R_SFT … #define RT5665_PDM1_BUSY … #define RT5665_PDM_PATTERN … #define RT5665_PDM_GAIN … #define RT5665_LRCK_PDM_PI2C … #define RT5665_PDM_DIV_MASK … /*S/PDIF Output Control (0x0036) */ #define RT5665_SPDIF_SEL_MASK … #define RT5665_SPDIF_SEL_SFT … /* REC Left Mixer Control 2 (0x003c) */ #define RT5665_M_CBJ_RM1_L … #define RT5665_M_CBJ_RM1_L_SFT … #define RT5665_M_BST1_RM1_L … #define RT5665_M_BST1_RM1_L_SFT … #define RT5665_M_BST2_RM1_L … #define RT5665_M_BST2_RM1_L_SFT … #define RT5665_M_BST3_RM1_L … #define RT5665_M_BST3_RM1_L_SFT … #define RT5665_M_BST4_RM1_L … #define RT5665_M_BST4_RM1_L_SFT … #define RT5665_M_INL_RM1_L … #define RT5665_M_INL_RM1_L_SFT … #define RT5665_M_INR_RM1_L … #define RT5665_M_INR_RM1_L_SFT … /* REC Right Mixer Control 2 (0x003e) */ #define RT5665_M_AEC_REF_RM1_R … #define RT5665_M_AEC_REF_RM1_R_SFT … #define RT5665_M_BST1_RM1_R … #define RT5665_M_BST1_RM1_R_SFT … #define RT5665_M_BST2_RM1_R … #define RT5665_M_BST2_RM1_R_SFT … #define RT5665_M_BST3_RM1_R … #define RT5665_M_BST3_RM1_R_SFT … #define RT5665_M_BST4_RM1_R … #define RT5665_M_BST4_RM1_R_SFT … #define RT5665_M_INR_RM1_R … #define RT5665_M_INR_RM1_R_SFT … #define RT5665_M_MONOVOL_RM1_R … #define RT5665_M_MONOVOL_RM1_R_SFT … /* REC Mixer 2 Left Control 2 (0x0041) */ #define RT5665_M_CBJ_RM2_L … #define RT5665_M_CBJ_RM2_L_SFT … #define RT5665_M_BST1_RM2_L … #define RT5665_M_BST1_RM2_L_SFT … #define RT5665_M_BST2_RM2_L … #define RT5665_M_BST2_RM2_L_SFT … #define RT5665_M_BST3_RM2_L … #define RT5665_M_BST3_RM2_L_SFT … #define RT5665_M_BST4_RM2_L … #define RT5665_M_BST4_RM2_L_SFT … #define RT5665_M_INL_RM2_L … #define RT5665_M_INL_RM2_L_SFT … #define RT5665_M_INR_RM2_L … #define RT5665_M_INR_RM2_L_SFT … /* REC Mixer 2 Right Control 2 (0x0043) */ #define RT5665_M_MONOVOL_RM2_R … #define RT5665_M_MONOVOL_RM2_R_SFT … #define RT5665_M_BST1_RM2_R … #define RT5665_M_BST1_RM2_R_SFT … #define RT5665_M_BST2_RM2_R … #define RT5665_M_BST2_RM2_R_SFT … #define RT5665_M_BST3_RM2_R … #define RT5665_M_BST3_RM2_R_SFT … #define RT5665_M_BST4_RM2_R … #define RT5665_M_BST4_RM2_R_SFT … #define RT5665_M_INL_RM2_R … #define RT5665_M_INL_RM2_R_SFT … #define RT5665_M_INR_RM2_R … #define RT5665_M_INR_RM2_R_SFT … /* SPK Left Mixer Control (0x0046) */ #define RT5665_M_BST3_SM_L … #define RT5665_M_BST3_SM_L_SFT … #define RT5665_M_IN_R_SM_L … #define RT5665_M_IN_R_SM_L_SFT … #define RT5665_M_IN_L_SM_L … #define RT5665_M_IN_L_SM_L_SFT … #define RT5665_M_BST1_SM_L … #define RT5665_M_BST1_SM_L_SFT … #define RT5665_M_DAC_L2_SM_L … #define RT5665_M_DAC_L2_SM_L_SFT … /* SPK Right Mixer Control (0x0047) */ #define RT5665_M_BST3_SM_R … #define RT5665_M_BST3_SM_R_SFT … #define RT5665_M_IN_R_SM_R … #define RT5665_M_IN_R_SM_R_SFT … #define RT5665_M_IN_L_SM_R … #define RT5665_M_IN_L_SM_R_SFT … #define RT5665_M_BST4_SM_R … #define RT5665_M_BST4_SM_R_SFT … #define RT5665_M_DAC_R2_SM_R … #define RT5665_M_DAC_R2_SM_R_SFT … /* SPO Amp Input and Gain Control (0x0048) */ #define RT5665_M_DAC_L2_SPKOMIX … #define RT5665_M_DAC_L2_SPKOMIX_SFT … #define RT5665_M_SPKVOLL_SPKOMIX … #define RT5665_M_SPKVOLL_SPKOMIX_SFT … #define RT5665_M_DAC_R2_SPKOMIX … #define RT5665_M_DAC_R2_SPKOMIX_SFT … #define RT5665_M_SPKVOLR_SPKOMIX … #define RT5665_M_SPKVOLR_SPKOMIX_SFT … /* MONOMIX Input and Gain Control (0x004b) */ #define RT5665_G_MONOVOL_MA … #define RT5665_G_MONOVOL_MA_SFT … #define RT5665_M_MONOVOL_MA … #define RT5665_M_MONOVOL_MA_SFT … #define RT5665_M_DAC_L2_MA … #define RT5665_M_DAC_L2_MA_SFT … #define RT5665_M_BST3_MM … #define RT5665_M_BST3_MM_SFT … #define RT5665_M_BST2_MM … #define RT5665_M_BST2_MM_SFT … #define RT5665_M_BST1_MM … #define RT5665_M_BST1_MM_SFT … #define RT5665_M_RECMIC2L_MM … #define RT5665_M_RECMIC2L_MM_SFT … #define RT5665_M_DAC_L2_MM … #define RT5665_M_DAC_L2_MM_SFT … /* Output Left Mixer Control 1 (0x004d) */ #define RT5665_G_BST3_OM_L_MASK … #define RT5665_G_BST3_OM_L_SFT … #define RT5665_G_BST2_OM_L_MASK … #define RT5665_G_BST2_OM_L_SFT … #define RT5665_G_BST1_OM_L_MASK … #define RT5665_G_BST1_OM_L_SFT … #define RT5665_G_IN_L_OM_L_MASK … #define RT5665_G_IN_L_OM_L_SFT … #define RT5665_G_DAC_L2_OM_L_MASK … #define RT5665_G_DAC_L2_OM_L_SFT … /* Output Left Mixer Input Control (0x004e) */ #define RT5665_M_BST3_OM_L … #define RT5665_M_BST3_OM_L_SFT … #define RT5665_M_BST2_OM_L … #define RT5665_M_BST2_OM_L_SFT … #define RT5665_M_BST1_OM_L … #define RT5665_M_BST1_OM_L_SFT … #define RT5665_M_IN_L_OM_L … #define RT5665_M_IN_L_OM_L_SFT … #define RT5665_M_DAC_L2_OM_L … #define RT5665_M_DAC_L2_OM_L_SFT … /* Output Right Mixer Input Control (0x0050) */ #define RT5665_M_BST4_OM_R … #define RT5665_M_BST4_OM_R_SFT … #define RT5665_M_BST3_OM_R … #define RT5665_M_BST3_OM_R_SFT … #define RT5665_M_BST2_OM_R … #define RT5665_M_BST2_OM_R_SFT … #define RT5665_M_IN_R_OM_R … #define RT5665_M_IN_R_OM_R_SFT … #define RT5665_M_DAC_R2_OM_R … #define RT5665_M_DAC_R2_OM_R_SFT … /* LOUT Mixer Control (0x0052) */ #define RT5665_M_DAC_L2_LM … #define RT5665_M_DAC_L2_LM_SFT … #define RT5665_M_DAC_R2_LM … #define RT5665_M_DAC_R2_LM_SFT … #define RT5665_M_OV_L_LM … #define RT5665_M_OV_L_LM_SFT … #define RT5665_M_OV_R_LM … #define RT5665_M_OV_R_LM_SFT … #define RT5665_LOUT_BST_SFT … #define RT5665_LOUT_DF … #define RT5665_LOUT_DF_SFT … /* Power Management for Digital 1 (0x0061) */ #define RT5665_PWR_I2S1_1 … #define RT5665_PWR_I2S1_1_BIT … #define RT5665_PWR_I2S1_2 … #define RT5665_PWR_I2S1_2_BIT … #define RT5665_PWR_I2S2_1 … #define RT5665_PWR_I2S2_1_BIT … #define RT5665_PWR_I2S2_2 … #define RT5665_PWR_I2S2_2_BIT … #define RT5665_PWR_DAC_L1 … #define RT5665_PWR_DAC_L1_BIT … #define RT5665_PWR_DAC_R1 … #define RT5665_PWR_DAC_R1_BIT … #define RT5665_PWR_I2S3 … #define RT5665_PWR_I2S3_BIT … #define RT5665_PWR_LDO … #define RT5665_PWR_LDO_BIT … #define RT5665_PWR_DAC_L2 … #define RT5665_PWR_DAC_L2_BIT … #define RT5665_PWR_DAC_R2 … #define RT5665_PWR_DAC_R2_BIT … #define RT5665_PWR_ADC_L1 … #define RT5665_PWR_ADC_L1_BIT … #define RT5665_PWR_ADC_R1 … #define RT5665_PWR_ADC_R1_BIT … #define RT5665_PWR_ADC_L2 … #define RT5665_PWR_ADC_L2_BIT … #define RT5665_PWR_ADC_R2 … #define RT5665_PWR_ADC_R2_BIT … /* Power Management for Digital 2 (0x0062) */ #define RT5665_PWR_ADC_S1F … #define RT5665_PWR_ADC_S1F_BIT … #define RT5665_PWR_ADC_S2F … #define RT5665_PWR_ADC_S2F_BIT … #define RT5665_PWR_ADC_MF_L … #define RT5665_PWR_ADC_MF_L_BIT … #define RT5665_PWR_ADC_MF_R … #define RT5665_PWR_ADC_MF_R_BIT … #define RT5665_PWR_DAC_S2F … #define RT5665_PWR_DAC_S2F_BIT … #define RT5665_PWR_DAC_S1F … #define RT5665_PWR_DAC_S1F_BIT … #define RT5665_PWR_DAC_MF_L … #define RT5665_PWR_DAC_MF_L_BIT … #define RT5665_PWR_DAC_MF_R … #define RT5665_PWR_DAC_MF_R_BIT … #define RT5665_PWR_PDM1 … #define RT5665_PWR_PDM1_BIT … /* Power Management for Analog 1 (0x0063) */ #define RT5665_PWR_VREF1 … #define RT5665_PWR_VREF1_BIT … #define RT5665_PWR_FV1 … #define RT5665_PWR_FV1_BIT … #define RT5665_PWR_VREF2 … #define RT5665_PWR_VREF2_BIT … #define RT5665_PWR_FV2 … #define RT5665_PWR_FV2_BIT … #define RT5665_PWR_VREF3 … #define RT5665_PWR_VREF3_BIT … #define RT5665_PWR_FV3 … #define RT5665_PWR_FV3_BIT … #define RT5665_PWR_MB … #define RT5665_PWR_MB_BIT … #define RT5665_PWR_LM … #define RT5665_PWR_LM_BIT … #define RT5665_PWR_BG … #define RT5665_PWR_BG_BIT … #define RT5665_PWR_MA … #define RT5665_PWR_MA_BIT … #define RT5665_PWR_HA_L … #define RT5665_PWR_HA_L_BIT … #define RT5665_PWR_HA_R … #define RT5665_PWR_HA_R_BIT … #define RT5665_HP_DRIVER_MASK … #define RT5665_HP_DRIVER_1X … #define RT5665_HP_DRIVER_3X … #define RT5665_HP_DRIVER_5X … #define RT5665_LDO1_DVO_MASK … #define RT5665_LDO1_DVO_09 … #define RT5665_LDO1_DVO_10 … #define RT5665_LDO1_DVO_12 … #define RT5665_LDO1_DVO_14 … /* Power Management for Analog 2 (0x0064) */ #define RT5665_PWR_BST1 … #define RT5665_PWR_BST1_BIT … #define RT5665_PWR_BST2 … #define RT5665_PWR_BST2_BIT … #define RT5665_PWR_BST3 … #define RT5665_PWR_BST3_BIT … #define RT5665_PWR_BST4 … #define RT5665_PWR_BST4_BIT … #define RT5665_PWR_MB1 … #define RT5665_PWR_MB1_PWR_DOWN … #define RT5665_PWR_MB1_BIT … #define RT5665_PWR_MB2 … #define RT5665_PWR_MB2_PWR_DOWN … #define RT5665_PWR_MB2_BIT … #define RT5665_PWR_MB3 … #define RT5665_PWR_MB3_BIT … #define RT5665_PWR_BST1_P … #define RT5665_PWR_BST1_P_BIT … #define RT5665_PWR_BST2_P … #define RT5665_PWR_BST2_P_BIT … #define RT5665_PWR_BST3_P … #define RT5665_PWR_BST3_P_BIT … #define RT5665_PWR_BST4_P … #define RT5665_PWR_BST4_P_BIT … #define RT5665_PWR_JD1 … #define RT5665_PWR_JD1_BIT … #define RT5665_PWR_JD2 … #define RT5665_PWR_JD2_BIT … #define RT5665_PWR_RM1_L … #define RT5665_PWR_RM1_L_BIT … #define RT5665_PWR_RM1_R … #define RT5665_PWR_RM1_R_BIT … /* Power Management for Analog 3 (0x0065) */ #define RT5665_PWR_CBJ … #define RT5665_PWR_CBJ_BIT … #define RT5665_PWR_BST_L … #define RT5665_PWR_BST_L_BIT … #define RT5665_PWR_BST_R … #define RT5665_PWR_BST_R_BIT … #define RT5665_PWR_PLL … #define RT5665_PWR_PLL_BIT … #define RT5665_PWR_LDO2 … #define RT5665_PWR_LDO2_BIT … #define RT5665_PWR_SVD … #define RT5665_PWR_SVD_BIT … /* Power Management for Mixer (0x0066) */ #define RT5665_PWR_RM2_L … #define RT5665_PWR_RM2_L_BIT … #define RT5665_PWR_RM2_R … #define RT5665_PWR_RM2_R_BIT … #define RT5665_PWR_OM_L … #define RT5665_PWR_OM_L_BIT … #define RT5665_PWR_OM_R … #define RT5665_PWR_OM_R_BIT … #define RT5665_PWR_MM … #define RT5665_PWR_MM_BIT … #define RT5665_PWR_AEC_REF … #define RT5665_PWR_AEC_REF_BIT … #define RT5665_PWR_STO1_DAC_L … #define RT5665_PWR_STO1_DAC_L_BIT … #define RT5665_PWR_STO1_DAC_R … #define RT5665_PWR_STO1_DAC_R_BIT … #define RT5665_PWR_MONO_DAC_L … #define RT5665_PWR_MONO_DAC_L_BIT … #define RT5665_PWR_MONO_DAC_R … #define RT5665_PWR_MONO_DAC_R_BIT … #define RT5665_PWR_STO2_DAC_L … #define RT5665_PWR_STO2_DAC_L_BIT … #define RT5665_PWR_STO2_DAC_R … #define RT5665_PWR_STO2_DAC_R_BIT … /* Power Management for Volume (0x0067) */ #define RT5665_PWR_OV_L … #define RT5665_PWR_OV_L_BIT … #define RT5665_PWR_OV_R … #define RT5665_PWR_OV_R_BIT … #define RT5665_PWR_IN_L … #define RT5665_PWR_IN_L_BIT … #define RT5665_PWR_IN_R … #define RT5665_PWR_IN_R_BIT … #define RT5665_PWR_MV … #define RT5665_PWR_MV_BIT … #define RT5665_PWR_MIC_DET … #define RT5665_PWR_MIC_DET_BIT … /* (0x006b) */ #define RT5665_SYS_CLK_DET … #define RT5665_HP_CLK_DET … #define RT5665_MONO_CLK_DET … #define RT5665_LOUT_CLK_DET … #define RT5665_POW_CLK_DET … /* Digital Microphone Control 1 (0x006e) */ #define RT5665_DMIC_1_EN_MASK … #define RT5665_DMIC_1_EN_SFT … #define RT5665_DMIC_1_DIS … #define RT5665_DMIC_1_EN … #define RT5665_DMIC_2_EN_MASK … #define RT5665_DMIC_2_EN_SFT … #define RT5665_DMIC_2_DIS … #define RT5665_DMIC_2_EN … #define RT5665_DMIC_2_DP_MASK … #define RT5665_DMIC_2_DP_SFT … #define RT5665_DMIC_2_DP_GPIO5 … #define RT5665_DMIC_2_DP_IN2P … #define RT5665_DMIC_CLK_MASK … #define RT5665_DMIC_CLK_SFT … #define RT5665_DMIC_1_DP_MASK … #define RT5665_DMIC_1_DP_SFT … #define RT5665_DMIC_1_DP_GPIO4 … #define RT5665_DMIC_1_DP_IN2N … /* Digital Microphone Control 1 (0x006f) */ #define RT5665_DMIC_2L_LH_MASK … #define RT5665_DMIC_2L_LH_SFT … #define RT5665_DMIC_2L_LH_RISING … #define RT5665_DMIC_2L_LH_FALLING … #define RT5665_DMIC_2R_LH_MASK … #define RT5665_DMIC_2R_LH_SFT … #define RT5665_DMIC_2R_LH_RISING … #define RT5665_DMIC_2R_LH_FALLING … #define RT5665_DMIC_1L_LH_MASK … #define RT5665_DMIC_1L_LH_SFT … #define RT5665_DMIC_1L_LH_RISING … #define RT5665_DMIC_1L_LH_FALLING … #define RT5665_DMIC_1R_LH_MASK … #define RT5665_DMIC_1R_LH_SFT … #define RT5665_DMIC_1R_LH_RISING … #define RT5665_DMIC_1R_LH_FALLING … /* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */ #define RT5665_I2S_MS_MASK … #define RT5665_I2S_MS_SFT … #define RT5665_I2S_MS_M … #define RT5665_I2S_MS_S … #define RT5665_I2S_PIN_CFG_MASK … #define RT5665_I2S_PIN_CFG_SFT … #define RT5665_I2S_CLK_SEL_MASK … #define RT5665_I2S_CLK_SEL_SFT … #define RT5665_I2S_BP_MASK … #define RT5665_I2S_BP_SFT … #define RT5665_I2S_BP_NOR … #define RT5665_I2S_BP_INV … #define RT5665_I2S_DL_MASK … #define RT5665_I2S_DL_SFT … #define RT5665_I2S_DL_16 … #define RT5665_I2S_DL_20 … #define RT5665_I2S_DL_24 … #define RT5665_I2S_DL_8 … #define RT5665_I2S_DF_MASK … #define RT5665_I2S_DF_SFT … #define RT5665_I2S_DF_I2S … #define RT5665_I2S_DF_LEFT … #define RT5665_I2S_DF_PCM_A … #define RT5665_I2S_DF_PCM_B … #define RT5665_I2S_DF_PCM_A_N … #define RT5665_I2S_DF_PCM_B_N … /* ADC/DAC Clock Control 1 (0x0073) */ #define RT5665_I2S_PD1_MASK … #define RT5665_I2S_PD1_SFT … #define RT5665_I2S_PD1_1 … #define RT5665_I2S_PD1_2 … #define RT5665_I2S_PD1_3 … #define RT5665_I2S_PD1_4 … #define RT5665_I2S_PD1_6 … #define RT5665_I2S_PD1_8 … #define RT5665_I2S_PD1_12 … #define RT5665_I2S_PD1_16 … #define RT5665_I2S_M_PD2_MASK … #define RT5665_I2S_M_PD2_SFT … #define RT5665_I2S_M_PD2_1 … #define RT5665_I2S_M_PD2_2 … #define RT5665_I2S_M_PD2_3 … #define RT5665_I2S_M_PD2_4 … #define RT5665_I2S_M_PD2_6 … #define RT5665_I2S_M_PD2_8 … #define RT5665_I2S_M_PD2_12 … #define RT5665_I2S_M_PD2_16 … #define RT5665_I2S_CLK_SRC_MASK … #define RT5665_I2S_CLK_SRC_SFT … #define RT5665_I2S_CLK_SRC_MCLK … #define RT5665_I2S_CLK_SRC_PLL1 … #define RT5665_I2S_CLK_SRC_RCCLK … #define RT5665_DAC_OSR_MASK … #define RT5665_DAC_OSR_SFT … #define RT5665_DAC_OSR_128 … #define RT5665_DAC_OSR_64 … #define RT5665_DAC_OSR_32 … #define RT5665_ADC_OSR_MASK … #define RT5665_ADC_OSR_SFT … #define RT5665_ADC_OSR_128 … #define RT5665_ADC_OSR_64 … #define RT5665_ADC_OSR_32 … /* ADC/DAC Clock Control 2 (0x0074) */ #define RT5665_I2S_BCLK_MS2_MASK … #define RT5665_I2S_BCLK_MS2_SFT … #define RT5665_I2S_BCLK_MS2_32 … #define RT5665_I2S_BCLK_MS2_64 … #define RT5665_I2S_PD2_MASK … #define RT5665_I2S_PD2_SFT … #define RT5665_I2S_PD2_1 … #define RT5665_I2S_PD2_2 … #define RT5665_I2S_PD2_3 … #define RT5665_I2S_PD2_4 … #define RT5665_I2S_PD2_6 … #define RT5665_I2S_PD2_8 … #define RT5665_I2S_PD2_12 … #define RT5665_I2S_PD2_16 … #define RT5665_I2S_BCLK_MS3_MASK … #define RT5665_I2S_BCLK_MS3_SFT … #define RT5665_I2S_BCLK_MS3_32 … #define RT5665_I2S_BCLK_MS3_64 … #define RT5665_I2S_PD3_MASK … #define RT5665_I2S_PD3_SFT … #define RT5665_I2S_PD3_1 … #define RT5665_I2S_PD3_2 … #define RT5665_I2S_PD3_3 … #define RT5665_I2S_PD3_4 … #define RT5665_I2S_PD3_6 … #define RT5665_I2S_PD3_8 … #define RT5665_I2S_PD3_12 … #define RT5665_I2S_PD3_16 … #define RT5665_I2S_PD4_MASK … #define RT5665_I2S_PD4_SFT … #define RT5665_I2S_PD4_1 … #define RT5665_I2S_PD4_2 … #define RT5665_I2S_PD4_3 … #define RT5665_I2S_PD4_4 … #define RT5665_I2S_PD4_6 … #define RT5665_I2S_PD4_8 … #define RT5665_I2S_PD4_12 … #define RT5665_I2S_PD4_16 … /* TDM control 1 (0x0078) */ #define RT5665_I2S1_MODE_MASK … #define RT5665_I2S1_MODE_I2S … #define RT5665_I2S1_MODE_TDM … #define RT5665_TDM_IN_CH_MASK … #define RT5665_TDM_IN_CH_2 … #define RT5665_TDM_IN_CH_4 … #define RT5665_TDM_IN_CH_6 … #define RT5665_TDM_IN_CH_8 … #define RT5665_TDM_OUT_CH_MASK … #define RT5665_TDM_OUT_CH_2 … #define RT5665_TDM_OUT_CH_4 … #define RT5665_TDM_OUT_CH_6 … #define RT5665_TDM_OUT_CH_8 … #define RT5665_TDM_IN_LEN_MASK … #define RT5665_TDM_IN_LEN_16 … #define RT5665_TDM_IN_LEN_20 … #define RT5665_TDM_IN_LEN_24 … #define RT5665_TDM_IN_LEN_32 … #define RT5665_TDM_OUT_LEN_MASK … #define RT5665_TDM_OUT_LEN_16 … #define RT5665_TDM_OUT_LEN_20 … #define RT5665_TDM_OUT_LEN_24 … #define RT5665_TDM_OUT_LEN_32 … /* TDM control 2 (0x0079) */ #define RT5665_I2S1_1_DS_ADC_SLOT01_SFT … #define RT5665_I2S1_1_DS_ADC_SLOT23_SFT … #define RT5665_I2S1_1_DS_ADC_SLOT45_SFT … #define RT5665_I2S1_1_DS_ADC_SLOT67_SFT … #define RT5665_I2S1_2_DS_ADC_SLOT01_SFT … #define RT5665_I2S1_2_DS_ADC_SLOT23_SFT … #define RT5665_I2S1_2_DS_ADC_SLOT45_SFT … #define RT5665_I2S1_2_DS_ADC_SLOT67_SFT … /* TDM control 3/4 (0x007a) (0x007b) */ #define RT5665_IF1_ADC1_SEL_SFT … #define RT5665_IF1_ADC2_SEL_SFT … #define RT5665_IF1_ADC3_SEL_SFT … #define RT5665_IF1_ADC4_SEL_SFT … #define RT5665_TDM_ADC_SEL_SFT … #define RT5665_TDM_ADC_CTRL_MASK … #define RT5665_TDM_ADC_DATA_06 … /* Global Clock Control (0x0080) */ #define RT5665_SCLK_SRC_MASK … #define RT5665_SCLK_SRC_SFT … #define RT5665_SCLK_SRC_MCLK … #define RT5665_SCLK_SRC_PLL1 … #define RT5665_SCLK_SRC_RCCLK … #define RT5665_PLL1_SRC_MASK … #define RT5665_PLL1_SRC_SFT … #define RT5665_PLL1_SRC_MCLK … #define RT5665_PLL1_SRC_BCLK1 … #define RT5665_PLL1_SRC_BCLK2 … #define RT5665_PLL1_SRC_BCLK3 … #define RT5665_PLL1_PD_MASK … #define RT5665_PLL1_PD_SFT … #define RT5665_PLL_INP_MAX … #define RT5665_PLL_INP_MIN … /* PLL M/N/K Code Control 1 (0x0081) */ #define RT5665_PLL_N_MAX … #define RT5665_PLL_N_MASK … #define RT5665_PLL_N_SFT … #define RT5665_PLL_K_MAX … #define RT5665_PLL_K_MASK … #define RT5665_PLL_K_SFT … /* PLL M/N/K Code Control 2 (0x0082) */ #define RT5665_PLL_M_MAX … #define RT5665_PLL_M_MASK … #define RT5665_PLL_M_SFT … #define RT5665_PLL_M_BP … #define RT5665_PLL_M_BP_SFT … #define RT5665_PLL_K_BP … #define RT5665_PLL_K_BP_SFT … /* PLL tracking mode 1 (0x0083) */ #define RT5665_I2S3_ASRC_MASK … #define RT5665_I2S3_ASRC_SFT … #define RT5665_I2S2_ASRC_MASK … #define RT5665_I2S2_ASRC_SFT … #define RT5665_I2S1_ASRC_MASK … #define RT5665_I2S1_ASRC_SFT … #define RT5665_DAC_STO1_ASRC_MASK … #define RT5665_DAC_STO1_ASRC_SFT … #define RT5665_DAC_STO2_ASRC_MASK … #define RT5665_DAC_STO2_ASRC_SFT … #define RT5665_DAC_MONO_L_ASRC_MASK … #define RT5665_DAC_MONO_L_ASRC_SFT … #define RT5665_DAC_MONO_R_ASRC_MASK … #define RT5665_DAC_MONO_R_ASRC_SFT … #define RT5665_DMIC_STO1_ASRC_MASK … #define RT5665_DMIC_STO1_ASRC_SFT … #define RT5665_DMIC_STO2_ASRC_MASK … #define RT5665_DMIC_STO2_ASRC_SFT … #define RT5665_DMIC_MONO_L_ASRC_MASK … #define RT5665_DMIC_MONO_L_ASRC_SFT … #define RT5665_DMIC_MONO_R_ASRC_MASK … #define RT5665_DMIC_MONO_R_ASRC_SFT … #define RT5665_ADC_STO1_ASRC_MASK … #define RT5665_ADC_STO1_ASRC_SFT … #define RT5665_ADC_STO2_ASRC_MASK … #define RT5665_ADC_STO2_ASRC_SFT … #define RT5665_ADC_MONO_L_ASRC_MASK … #define RT5665_ADC_MONO_L_ASRC_SFT … #define RT5665_ADC_MONO_R_ASRC_MASK … #define RT5665_ADC_MONO_R_ASRC_SFT … /* PLL tracking mode 2 (0x0084)*/ #define RT5665_DA_STO1_CLK_SEL_MASK … #define RT5665_DA_STO1_CLK_SEL_SFT … #define RT5665_DA_STO2_CLK_SEL_MASK … #define RT5665_DA_STO2_CLK_SEL_SFT … #define RT5665_DA_MONOL_CLK_SEL_MASK … #define RT5665_DA_MONOL_CLK_SEL_SFT … #define RT5665_DA_MONOR_CLK_SEL_MASK … #define RT5665_DA_MONOR_CLK_SEL_SFT … /* PLL tracking mode 3 (0x0085)*/ #define RT5665_AD_STO1_CLK_SEL_MASK … #define RT5665_AD_STO1_CLK_SEL_SFT … #define RT5665_AD_STO2_CLK_SEL_MASK … #define RT5665_AD_STO2_CLK_SEL_SFT … #define RT5665_AD_MONOL_CLK_SEL_MASK … #define RT5665_AD_MONOL_CLK_SEL_SFT … #define RT5665_AD_MONOR_CLK_SEL_MASK … #define RT5665_AD_MONOR_CLK_SEL_SFT … /* ASRC Control 4 (0x0086) */ #define RT5665_I2S1_RATE_MASK … #define RT5665_I2S1_RATE_SFT … #define RT5665_I2S2_RATE_MASK … #define RT5665_I2S2_RATE_SFT … #define RT5665_I2S3_RATE_MASK … #define RT5665_I2S3_RATE_SFT … /* Depop Mode Control 1 (0x008e) */ #define RT5665_PUMP_EN … /* Depop Mode Control 2 (0x8f) */ #define RT5665_DEPOP_MASK … #define RT5665_DEPOP_SFT … #define RT5665_DEPOP_AUTO … #define RT5665_DEPOP_MAN … #define RT5665_RAMP_MASK … #define RT5665_RAMP_SFT … #define RT5665_RAMP_DIS … #define RT5665_RAMP_EN … #define RT5665_BPS_MASK … #define RT5665_BPS_SFT … #define RT5665_BPS_DIS … #define RT5665_BPS_EN … #define RT5665_FAST_UPDN_MASK … #define RT5665_FAST_UPDN_SFT … #define RT5665_FAST_UPDN_DIS … #define RT5665_FAST_UPDN_EN … #define RT5665_MRES_MASK … #define RT5665_MRES_SFT … #define RT5665_MRES_15MO … #define RT5665_MRES_25MO … #define RT5665_MRES_35MO … #define RT5665_MRES_45MO … #define RT5665_VLO_MASK … #define RT5665_VLO_SFT … #define RT5665_VLO_3V … #define RT5665_VLO_32V … #define RT5665_DIG_DP_MASK … #define RT5665_DIG_DP_SFT … #define RT5665_DIG_DP_DIS … #define RT5665_DIG_DP_EN … #define RT5665_DP_TH_MASK … #define RT5665_DP_TH_SFT … /* Depop Mode Control 3 (0x90) */ #define RT5665_CP_SYS_MASK … #define RT5665_CP_SYS_SFT … #define RT5665_CP_FQ1_MASK … #define RT5665_CP_FQ1_SFT … #define RT5665_CP_FQ2_MASK … #define RT5665_CP_FQ2_SFT … #define RT5665_CP_FQ3_MASK … #define RT5665_CP_FQ3_SFT … #define RT5665_CP_FQ_1_5_KHZ … #define RT5665_CP_FQ_3_KHZ … #define RT5665_CP_FQ_6_KHZ … #define RT5665_CP_FQ_12_KHZ … #define RT5665_CP_FQ_24_KHZ … #define RT5665_CP_FQ_48_KHZ … #define RT5665_CP_FQ_96_KHZ … #define RT5665_CP_FQ_192_KHZ … /* HPOUT charge pump 1 (0x0091) */ #define RT5665_OSW_L_MASK … #define RT5665_OSW_L_SFT … #define RT5665_OSW_L_DIS … #define RT5665_OSW_L_EN … #define RT5665_OSW_R_MASK … #define RT5665_OSW_R_SFT … #define RT5665_OSW_R_DIS … #define RT5665_OSW_R_EN … #define RT5665_PM_HP_MASK … #define RT5665_PM_HP_SFT … #define RT5665_PM_HP_LV … #define RT5665_PM_HP_MV … #define RT5665_PM_HP_HV … #define RT5665_IB_HP_MASK … #define RT5665_IB_HP_SFT … #define RT5665_IB_HP_125IL … #define RT5665_IB_HP_25IL … #define RT5665_IB_HP_5IL … #define RT5665_IB_HP_1IL … /* PV detection and SPK gain control (0x92) */ #define RT5665_PVDD_DET_MASK … #define RT5665_PVDD_DET_SFT … #define RT5665_PVDD_DET_DIS … #define RT5665_PVDD_DET_EN … #define RT5665_SPK_AG_MASK … #define RT5665_SPK_AG_SFT … #define RT5665_SPK_AG_DIS … #define RT5665_SPK_AG_EN … /* Micbias Control1 (0x93) */ #define RT5665_MIC1_BS_MASK … #define RT5665_MIC1_BS_SFT … #define RT5665_MIC1_BS_9AV … #define RT5665_MIC1_BS_75AV … #define RT5665_MIC2_BS_MASK … #define RT5665_MIC2_BS_SFT … #define RT5665_MIC2_BS_9AV … #define RT5665_MIC2_BS_75AV … #define RT5665_MIC1_CLK_MASK … #define RT5665_MIC1_CLK_SFT … #define RT5665_MIC1_CLK_DIS … #define RT5665_MIC1_CLK_EN … #define RT5665_MIC2_CLK_MASK … #define RT5665_MIC2_CLK_SFT … #define RT5665_MIC2_CLK_DIS … #define RT5665_MIC2_CLK_EN … #define RT5665_MIC1_OVCD_MASK … #define RT5665_MIC1_OVCD_SFT … #define RT5665_MIC1_OVCD_DIS … #define RT5665_MIC1_OVCD_EN … #define RT5665_MIC1_OVTH_MASK … #define RT5665_MIC1_OVTH_SFT … #define RT5665_MIC1_OVTH_600UA … #define RT5665_MIC1_OVTH_1500UA … #define RT5665_MIC1_OVTH_2000UA … #define RT5665_MIC2_OVCD_MASK … #define RT5665_MIC2_OVCD_SFT … #define RT5665_MIC2_OVCD_DIS … #define RT5665_MIC2_OVCD_EN … #define RT5665_MIC2_OVTH_MASK … #define RT5665_MIC2_OVTH_SFT … #define RT5665_MIC2_OVTH_600UA … #define RT5665_MIC2_OVTH_1500UA … #define RT5665_MIC2_OVTH_2000UA … #define RT5665_PWR_MB_MASK … #define RT5665_PWR_MB_SFT … #define RT5665_PWR_MB_PD … #define RT5665_PWR_MB_PU … /* Micbias Control2 (0x94) */ #define RT5665_PWR_CLK25M_MASK … #define RT5665_PWR_CLK25M_SFT … #define RT5665_PWR_CLK25M_PD … #define RT5665_PWR_CLK25M_PU … #define RT5665_PWR_CLK1M_MASK … #define RT5665_PWR_CLK1M_SFT … #define RT5665_PWR_CLK1M_PD … #define RT5665_PWR_CLK1M_PU … /* I2S Master Mode Clock Control 1 (0x00a0) */ #define RT5665_CLK_SRC_MCLK … #define RT5665_CLK_SRC_PLL1 … #define RT5665_CLK_SRC_RCCLK … #define RT5665_I2S_PD_1 … #define RT5665_I2S_PD_2 … #define RT5665_I2S_PD_3 … #define RT5665_I2S_PD_4 … #define RT5665_I2S_PD_6 … #define RT5665_I2S_PD_8 … #define RT5665_I2S_PD_12 … #define RT5665_I2S_PD_16 … #define RT5665_I2S2_SRC_MASK … #define RT5665_I2S2_SRC_SFT … #define RT5665_I2S2_M_PD_MASK … #define RT5665_I2S2_M_PD_SFT … #define RT5665_I2S3_SRC_MASK … #define RT5665_I2S3_SRC_SFT … #define RT5665_I2S3_M_PD_MASK … #define RT5665_I2S3_M_PD_SFT … /* EQ Control 1 (0x00b0) */ #define RT5665_EQ_SRC_DAC … #define RT5665_EQ_SRC_ADC … #define RT5665_EQ_UPD … #define RT5665_EQ_UPD_BIT … #define RT5665_EQ_CD_MASK … #define RT5665_EQ_CD_SFT … #define RT5665_EQ_CD_DIS … #define RT5665_EQ_CD_EN … #define RT5665_EQ_DITH_MASK … #define RT5665_EQ_DITH_SFT … #define RT5665_EQ_DITH_NOR … #define RT5665_EQ_DITH_LSB … #define RT5665_EQ_DITH_LSB_1 … #define RT5665_EQ_DITH_LSB_2 … /* IRQ Control 1 (0x00b7) */ #define RT5665_JD1_1_EN_MASK … #define RT5665_JD1_1_EN_SFT … #define RT5665_JD1_1_DIS … #define RT5665_JD1_1_EN … #define RT5665_JD1_2_EN_MASK … #define RT5665_JD1_2_EN_SFT … #define RT5665_JD1_2_DIS … #define RT5665_JD1_2_EN … /* IRQ Control 2 (0x00b8) */ #define RT5665_IL_IRQ_MASK … #define RT5665_IL_IRQ_DIS … #define RT5665_IL_IRQ_EN … /* IRQ Control 5 (0x00ba) */ #define RT5665_IRQ_JD_EN … #define RT5665_IRQ_JD_EN_SFT … /* GPIO Control 1 (0x00c0) */ #define RT5665_GP1_PIN_MASK … #define RT5665_GP1_PIN_SFT … #define RT5665_GP1_PIN_GPIO1 … #define RT5665_GP1_PIN_IRQ … #define RT5665_GP2_PIN_MASK … #define RT5665_GP2_PIN_SFT … #define RT5665_GP2_PIN_GPIO2 … #define RT5665_GP2_PIN_BCLK2 … #define RT5665_GP2_PIN_PDM_SCL … #define RT5665_GP3_PIN_MASK … #define RT5665_GP3_PIN_SFT … #define RT5665_GP3_PIN_GPIO3 … #define RT5665_GP3_PIN_LRCK2 … #define RT5665_GP3_PIN_PDM_SDA … #define RT5665_GP4_PIN_MASK … #define RT5665_GP4_PIN_SFT … #define RT5665_GP4_PIN_GPIO4 … #define RT5665_GP4_PIN_DACDAT2_1 … #define RT5665_GP4_PIN_DMIC1_SDA … #define RT5665_GP5_PIN_MASK … #define RT5665_GP5_PIN_SFT … #define RT5665_GP5_PIN_GPIO5 … #define RT5665_GP5_PIN_ADCDAT2_1 … #define RT5665_GP5_PIN_DMIC2_SDA … #define RT5665_GP6_PIN_MASK … #define RT5665_GP6_PIN_SFT … #define RT5665_GP6_PIN_GPIO6 … #define RT5665_GP6_PIN_BCLK3 … #define RT5665_GP6_PIN_PDM_SCL … #define RT5665_GP7_PIN_MASK … #define RT5665_GP7_PIN_SFT … #define RT5665_GP7_PIN_GPIO7 … #define RT5665_GP7_PIN_LRCK3 … #define RT5665_GP7_PIN_PDM_SDA … #define RT5665_GP8_PIN_MASK … #define RT5665_GP8_PIN_SFT … #define RT5665_GP8_PIN_GPIO8 … #define RT5665_GP8_PIN_DACDAT3 … #define RT5665_GP8_PIN_DMIC2_SCL … #define RT5665_GP8_PIN_DACDAT2_2 … /* GPIO Control 2 (0x00c1)*/ #define RT5665_GP9_PIN_MASK … #define RT5665_GP9_PIN_SFT … #define RT5665_GP9_PIN_GPIO9 … #define RT5665_GP9_PIN_ADCDAT3 … #define RT5665_GP9_PIN_DMIC1_SCL … #define RT5665_GP9_PIN_ADCDAT2_2 … #define RT5665_GP10_PIN_MASK … #define RT5665_GP10_PIN_SFT … #define RT5665_GP10_PIN_GPIO10 … #define RT5665_GP10_PIN_ADCDAT1_2 … #define RT5665_GP10_PIN_LPD … #define RT5665_GP1_PF_MASK … #define RT5665_GP1_PF_IN … #define RT5665_GP1_PF_OUT … #define RT5665_GP1_OUT_MASK … #define RT5665_GP1_OUT_H … #define RT5665_GP1_OUT_L … #define RT5665_GP2_PF_MASK … #define RT5665_GP2_PF_IN … #define RT5665_GP2_PF_OUT … #define RT5665_GP2_OUT_MASK … #define RT5665_GP2_OUT_H … #define RT5665_GP2_OUT_L … #define RT5665_GP3_PF_MASK … #define RT5665_GP3_PF_IN … #define RT5665_GP3_PF_OUT … #define RT5665_GP3_OUT_MASK … #define RT5665_GP3_OUT_H … #define RT5665_GP3_OUT_L … #define RT5665_GP4_PF_MASK … #define RT5665_GP4_PF_IN … #define RT5665_GP4_PF_OUT … #define RT5665_GP4_OUT_MASK … #define RT5665_GP4_OUT_H … #define RT5665_GP4_OUT_L … #define RT5665_GP5_PF_MASK … #define RT5665_GP5_PF_IN … #define RT5665_GP5_PF_OUT … #define RT5665_GP5_OUT_MASK … #define RT5665_GP5_OUT_H … #define RT5665_GP5_OUT_L … #define RT5665_GP6_PF_MASK … #define RT5665_GP6_PF_IN … #define RT5665_GP6_PF_OUT … #define RT5665_GP6_OUT_MASK … #define RT5665_GP6_OUT_H … #define RT5665_GP6_OUT_L … /* GPIO Control 3 (0x00c2) */ #define RT5665_GP7_PF_MASK … #define RT5665_GP7_PF_IN … #define RT5665_GP7_PF_OUT … #define RT5665_GP7_OUT_MASK … #define RT5665_GP7_OUT_H … #define RT5665_GP7_OUT_L … #define RT5665_GP8_PF_MASK … #define RT5665_GP8_PF_IN … #define RT5665_GP8_PF_OUT … #define RT5665_GP8_OUT_MASK … #define RT5665_GP8_OUT_H … #define RT5665_GP8_OUT_L … #define RT5665_GP9_PF_MASK … #define RT5665_GP9_PF_IN … #define RT5665_GP9_PF_OUT … #define RT5665_GP9_OUT_MASK … #define RT5665_GP9_OUT_H … #define RT5665_GP9_OUT_L … #define RT5665_GP10_PF_MASK … #define RT5665_GP10_PF_IN … #define RT5665_GP10_PF_OUT … #define RT5665_GP10_OUT_MASK … #define RT5665_GP10_OUT_H … #define RT5665_GP10_OUT_L … #define RT5665_GP11_PF_MASK … #define RT5665_GP11_PF_IN … #define RT5665_GP11_PF_OUT … #define RT5665_GP11_OUT_MASK … #define RT5665_GP11_OUT_H … #define RT5665_GP11_OUT_L … /* Soft volume and zero cross control 1 (0x00d9) */ #define RT5665_SV_MASK … #define RT5665_SV_SFT … #define RT5665_SV_DIS … #define RT5665_SV_EN … #define RT5665_OUT_SV_MASK … #define RT5665_OUT_SV_SFT … #define RT5665_OUT_SV_DIS … #define RT5665_OUT_SV_EN … #define RT5665_HP_SV_MASK … #define RT5665_HP_SV_SFT … #define RT5665_HP_SV_DIS … #define RT5665_HP_SV_EN … #define RT5665_ZCD_DIG_MASK … #define RT5665_ZCD_DIG_SFT … #define RT5665_ZCD_DIG_DIS … #define RT5665_ZCD_DIG_EN … #define RT5665_ZCD_MASK … #define RT5665_ZCD_SFT … #define RT5665_ZCD_PD … #define RT5665_ZCD_PU … #define RT5665_SV_DLY_MASK … #define RT5665_SV_DLY_SFT … /* Soft volume and zero cross control 2 (0x00da) */ #define RT5665_ZCD_HP_MASK … #define RT5665_ZCD_HP_SFT … #define RT5665_ZCD_HP_DIS … #define RT5665_ZCD_HP_EN … /* 4 Button Inline Command Control 2 (0x00e0) */ #define RT5665_4BTN_IL_MASK … #define RT5665_4BTN_IL_EN … #define RT5665_4BTN_IL_DIS … #define RT5665_4BTN_IL_RST_MASK … #define RT5665_4BTN_IL_NOR … #define RT5665_4BTN_IL_RST … /* Analog JD Control 1 (0x00f0) */ #define RT5665_JD1_MODE_MASK … #define RT5665_JD1_MODE_0 … #define RT5665_JD1_MODE_1 … #define RT5665_JD1_MODE_2 … /* Jack Detect Control 3 (0x00f8) */ #define RT5665_JD_TRI_HPO_SEL_MASK … #define RT5665_JD_TRI_HPO_SEL_SFT … #define RT5665_JD_HPO_GPIO_JD1 … #define RT5665_JD_HPO_JD1_1 … #define RT5665_JD_HPO_JD1_2 … #define RT5665_JD_HPO_JD2 … #define RT5665_JD_HPO_GPIO_JD2 … #define RT5665_JD_HPO_JD3 … #define RT5665_JD_HPO_JD_D … /* Digital Misc Control (0x00fa) */ #define RT5665_AM_MASK … #define RT5665_AM_EN … #define RT5665_AM_DIS … #define RT5665_DIG_GATE_CTRL … #define RT5665_DIG_GATE_CTRL_SFT … /* Chopper and Clock control for ADC (0x011c)*/ #define RT5665_M_RF_DIG_MASK … #define RT5665_M_RF_DIG_SFT … #define RT5665_M_RI_DIG … /* Chopper and Clock control for DAC (0x013a)*/ #define RT5665_CKXEN_DAC1_MASK … #define RT5665_CKXEN_DAC1_SFT … #define RT5665_CKGEN_DAC1_MASK … #define RT5665_CKGEN_DAC1_SFT … #define RT5665_CKXEN_DAC2_MASK … #define RT5665_CKXEN_DAC2_SFT … #define RT5665_CKGEN_DAC2_MASK … #define RT5665_CKGEN_DAC2_SFT … /* Chopper and Clock control for ADC (0x013b)*/ #define RT5665_CKXEN_ADC1_MASK … #define RT5665_CKXEN_ADC1_SFT … #define RT5665_CKGEN_ADC1_MASK … #define RT5665_CKGEN_ADC1_SFT … #define RT5665_CKXEN_ADC2_MASK … #define RT5665_CKXEN_ADC2_SFT … #define RT5665_CKGEN_ADC2_MASK … #define RT5665_CKGEN_ADC2_SFT … /* Volume test (0x013f)*/ #define RT5665_SEL_CLK_VOL_MASK … #define RT5665_SEL_CLK_VOL_EN … #define RT5665_SEL_CLK_VOL_DIS … /* Test Mode Control 1 (0x0145) */ #define RT5665_AD2DA_LB_MASK … #define RT5665_AD2DA_LB_SFT … /* Stereo Noise Gate Control 1 (0x0160) */ #define RT5665_NG2_EN_MASK … #define RT5665_NG2_EN … #define RT5665_NG2_DIS … /* Stereo1 DAC Silence Detection Control (0x0190) */ #define RT5665_DEB_STO_DAC_MASK … #define RT5665_DEB_80_MS … /* SAR ADC Inline Command Control 1 (0x0210) */ #define RT5665_SAR_BUTT_DET_MASK … #define RT5665_SAR_BUTT_DET_EN … #define RT5665_SAR_BUTT_DET_DIS … #define RT5665_SAR_BUTDET_MODE_MASK … #define RT5665_SAR_BUTDET_POW_SAV … #define RT5665_SAR_BUTDET_POW_NORM … #define RT5665_SAR_BUTDET_RST_MASK … #define RT5665_SAR_BUTDET_RST_NORMAL … #define RT5665_SAR_BUTDET_RST … #define RT5665_SAR_POW_MASK … #define RT5665_SAR_POW_EN … #define RT5665_SAR_POW_DIS … #define RT5665_SAR_RST_MASK … #define RT5665_SAR_RST_NORMAL … #define RT5665_SAR_RST … #define RT5665_SAR_BYPASS_MASK … #define RT5665_SAR_BYPASS_EN … #define RT5665_SAR_BYPASS_DIS … #define RT5665_SAR_SEL_MB1_MASK … #define RT5665_SAR_SEL_MB1_SEL … #define RT5665_SAR_SEL_MB1_NOSEL … #define RT5665_SAR_SEL_MB2_MASK … #define RT5665_SAR_SEL_MB2_SEL … #define RT5665_SAR_SEL_MB2_NOSEL … #define RT5665_SAR_SEL_MODE_MASK … #define RT5665_SAR_SEL_MODE_CMP … #define RT5665_SAR_SEL_MODE_ADC … #define RT5665_SAR_SEL_MB1_MB2_MASK … #define RT5665_SAR_SEL_MB1_MB2_AUTO … #define RT5665_SAR_SEL_MB1_MB2_MANU … #define RT5665_SAR_SEL_SIGNAL_MASK … #define RT5665_SAR_SEL_SIGNAL_AUTO … #define RT5665_SAR_SEL_SIGNAL_MANU … /* System Clock Source */ enum { … }; /* PLL1 Source */ enum { … }; enum { … }; enum { … }; /* filter mask */ enum { … }; enum { … }; int rt5665_sel_asrc_clk_src(struct snd_soc_component *component, unsigned int filter_mask, unsigned int clk_src); #endif /* __RT5665_H__ */
Codebase Browser
linux