/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt5677.h -- RT5677 ALSA SoC audio driver * * Copyright 2013 Realtek Semiconductor Corp. * Author: Oder Chiou <[email protected]> */ #ifndef __RT5677_H__ #define __RT5677_H__ #include <linux/gpio/driver.h> #include <linux/gpio/consumer.h> /* Info */ #define RT5677_RESET … #define RT5677_VENDOR_ID … #define RT5677_VENDOR_ID1 … #define RT5677_VENDOR_ID2 … /* I/O - Output */ #define RT5677_LOUT1 … /* I/O - Input */ #define RT5677_IN1 … #define RT5677_MICBIAS … /* I/O - SLIMBus */ #define RT5677_SLIMBUS_PARAM … #define RT5677_SLIMBUS_RX … #define RT5677_SLIMBUS_CTRL … /* I/O */ #define RT5677_SIDETONE_CTRL … /* I/O - ADC/DAC */ #define RT5677_ANA_DAC1_2_3_SRC … #define RT5677_IF_DSP_DAC3_4_MIXER … #define RT5677_DAC4_DIG_VOL … #define RT5677_DAC3_DIG_VOL … #define RT5677_DAC1_DIG_VOL … #define RT5677_DAC2_DIG_VOL … #define RT5677_IF_DSP_DAC2_MIXER … #define RT5677_STO1_ADC_DIG_VOL … #define RT5677_MONO_ADC_DIG_VOL … #define RT5677_STO1_2_ADC_BST … #define RT5677_STO2_ADC_DIG_VOL … /* Mixer - D-D */ #define RT5677_ADC_BST_CTRL2 … #define RT5677_STO3_4_ADC_BST … #define RT5677_STO3_ADC_DIG_VOL … #define RT5677_STO4_ADC_DIG_VOL … #define RT5677_STO4_ADC_MIXER … #define RT5677_STO3_ADC_MIXER … #define RT5677_STO2_ADC_MIXER … #define RT5677_STO1_ADC_MIXER … #define RT5677_MONO_ADC_MIXER … #define RT5677_ADC_IF_DSP_DAC1_MIXER … #define RT5677_STO1_DAC_MIXER … #define RT5677_MONO_DAC_MIXER … #define RT5677_DD1_MIXER … #define RT5677_DD2_MIXER … #define RT5677_IF3_DATA … #define RT5677_IF4_DATA … /* Mixer - PDM */ #define RT5677_PDM_OUT_CTRL … #define RT5677_PDM_DATA_CTRL1 … #define RT5677_PDM_DATA_CTRL2 … #define RT5677_PDM1_DATA_CTRL2 … #define RT5677_PDM1_DATA_CTRL3 … #define RT5677_PDM1_DATA_CTRL4 … #define RT5677_PDM2_DATA_CTRL2 … #define RT5677_PDM2_DATA_CTRL3 … #define RT5677_PDM2_DATA_CTRL4 … /* TDM */ #define RT5677_TDM1_CTRL1 … #define RT5677_TDM1_CTRL2 … #define RT5677_TDM1_CTRL3 … #define RT5677_TDM1_CTRL4 … #define RT5677_TDM1_CTRL5 … #define RT5677_TDM2_CTRL1 … #define RT5677_TDM2_CTRL2 … #define RT5677_TDM2_CTRL3 … #define RT5677_TDM2_CTRL4 … #define RT5677_TDM2_CTRL5 … /* I2C_MASTER_CTRL */ #define RT5677_I2C_MASTER_CTRL1 … #define RT5677_I2C_MASTER_CTRL2 … #define RT5677_I2C_MASTER_CTRL3 … #define RT5677_I2C_MASTER_CTRL4 … #define RT5677_I2C_MASTER_CTRL5 … #define RT5677_I2C_MASTER_CTRL6 … #define RT5677_I2C_MASTER_CTRL7 … #define RT5677_I2C_MASTER_CTRL8 … /* DMIC */ #define RT5677_DMIC_CTRL1 … #define RT5677_DMIC_CTRL2 … /* Haptic Generator */ #define RT5677_HAP_GENE_CTRL1 … #define RT5677_HAP_GENE_CTRL2 … #define RT5677_HAP_GENE_CTRL3 … #define RT5677_HAP_GENE_CTRL4 … #define RT5677_HAP_GENE_CTRL5 … #define RT5677_HAP_GENE_CTRL6 … #define RT5677_HAP_GENE_CTRL7 … #define RT5677_HAP_GENE_CTRL8 … #define RT5677_HAP_GENE_CTRL9 … #define RT5677_HAP_GENE_CTRL10 … /* Power */ #define RT5677_PWR_DIG1 … #define RT5677_PWR_DIG2 … #define RT5677_PWR_ANLG1 … #define RT5677_PWR_ANLG2 … #define RT5677_PWR_DSP1 … #define RT5677_PWR_DSP_ST … #define RT5677_PWR_DSP2 … #define RT5677_ADC_DAC_HPF_CTRL1 … /* Private Register Control */ #define RT5677_PRIV_INDEX … #define RT5677_PRIV_DATA … /* Format - ADC/DAC */ #define RT5677_I2S4_SDP … #define RT5677_I2S1_SDP … #define RT5677_I2S2_SDP … #define RT5677_I2S3_SDP … #define RT5677_CLK_TREE_CTRL1 … #define RT5677_CLK_TREE_CTRL2 … #define RT5677_CLK_TREE_CTRL3 … /* Function - Analog */ #define RT5677_PLL1_CTRL1 … #define RT5677_PLL1_CTRL2 … #define RT5677_PLL2_CTRL1 … #define RT5677_PLL2_CTRL2 … #define RT5677_GLB_CLK1 … #define RT5677_GLB_CLK2 … #define RT5677_ASRC_1 … #define RT5677_ASRC_2 … #define RT5677_ASRC_3 … #define RT5677_ASRC_4 … #define RT5677_ASRC_5 … #define RT5677_ASRC_6 … #define RT5677_ASRC_7 … #define RT5677_ASRC_8 … #define RT5677_ASRC_9 … #define RT5677_ASRC_10 … #define RT5677_ASRC_11 … #define RT5677_ASRC_12 … #define RT5677_ASRC_13 … #define RT5677_ASRC_14 … #define RT5677_ASRC_15 … #define RT5677_ASRC_16 … #define RT5677_ASRC_17 … #define RT5677_ASRC_18 … #define RT5677_ASRC_19 … #define RT5677_ASRC_20 … #define RT5677_ASRC_21 … #define RT5677_ASRC_22 … #define RT5677_ASRC_23 … #define RT5677_VAD_CTRL1 … #define RT5677_VAD_CTRL2 … #define RT5677_VAD_CTRL3 … #define RT5677_VAD_CTRL4 … #define RT5677_VAD_CTRL5 … /* Function - Digital */ #define RT5677_DSP_INB_CTRL1 … #define RT5677_DSP_INB_CTRL2 … #define RT5677_DSP_IN_OUTB_CTRL … #define RT5677_DSP_OUTB0_1_DIG_VOL … #define RT5677_DSP_OUTB2_3_DIG_VOL … #define RT5677_DSP_OUTB4_5_DIG_VOL … #define RT5677_DSP_OUTB6_7_DIG_VOL … #define RT5677_ADC_EQ_CTRL1 … #define RT5677_ADC_EQ_CTRL2 … #define RT5677_EQ_CTRL1 … #define RT5677_EQ_CTRL2 … #define RT5677_EQ_CTRL3 … #define RT5677_SOFT_VOL_ZERO_CROSS1 … #define RT5677_JD_CTRL1 … #define RT5677_JD_CTRL2 … #define RT5677_JD_CTRL3 … #define RT5677_IRQ_CTRL1 … #define RT5677_IRQ_CTRL2 … #define RT5677_GPIO_ST … #define RT5677_GPIO_CTRL1 … #define RT5677_GPIO_CTRL2 … #define RT5677_GPIO_CTRL3 … #define RT5677_STO1_ADC_HI_FILTER1 … #define RT5677_STO1_ADC_HI_FILTER2 … #define RT5677_MONO_ADC_HI_FILTER1 … #define RT5677_MONO_ADC_HI_FILTER2 … #define RT5677_STO2_ADC_HI_FILTER1 … #define RT5677_STO2_ADC_HI_FILTER2 … #define RT5677_STO3_ADC_HI_FILTER1 … #define RT5677_STO3_ADC_HI_FILTER2 … #define RT5677_STO4_ADC_HI_FILTER1 … #define RT5677_STO4_ADC_HI_FILTER2 … #define RT5677_MB_DRC_CTRL1 … #define RT5677_DRC1_CTRL1 … #define RT5677_DRC1_CTRL2 … #define RT5677_DRC1_CTRL3 … #define RT5677_DRC1_CTRL4 … #define RT5677_DRC1_CTRL5 … #define RT5677_DRC1_CTRL6 … #define RT5677_DRC2_CTRL1 … #define RT5677_DRC2_CTRL2 … #define RT5677_DRC2_CTRL3 … #define RT5677_DRC2_CTRL4 … #define RT5677_DRC2_CTRL5 … #define RT5677_DRC2_CTRL6 … #define RT5677_DRC1_HL_CTRL1 … #define RT5677_DRC1_HL_CTRL2 … #define RT5677_DRC2_HL_CTRL1 … #define RT5677_DRC2_HL_CTRL2 … #define RT5677_DSP_INB1_SRC_CTRL1 … #define RT5677_DSP_INB1_SRC_CTRL2 … #define RT5677_DSP_INB1_SRC_CTRL3 … #define RT5677_DSP_INB1_SRC_CTRL4 … #define RT5677_DSP_INB2_SRC_CTRL1 … #define RT5677_DSP_INB2_SRC_CTRL2 … #define RT5677_DSP_INB2_SRC_CTRL3 … #define RT5677_DSP_INB2_SRC_CTRL4 … #define RT5677_DSP_INB3_SRC_CTRL1 … #define RT5677_DSP_INB3_SRC_CTRL2 … #define RT5677_DSP_INB3_SRC_CTRL3 … #define RT5677_DSP_INB3_SRC_CTRL4 … #define RT5677_DSP_OUTB1_SRC_CTRL1 … #define RT5677_DSP_OUTB1_SRC_CTRL2 … #define RT5677_DSP_OUTB1_SRC_CTRL3 … #define RT5677_DSP_OUTB1_SRC_CTRL4 … #define RT5677_DSP_OUTB2_SRC_CTRL1 … #define RT5677_DSP_OUTB2_SRC_CTRL2 … #define RT5677_DSP_OUTB2_SRC_CTRL3 … #define RT5677_DSP_OUTB2_SRC_CTRL4 … /* Virtual DSP Mixer Control */ #define RT5677_DSP_OUTB_0123_MIXER_CTRL … #define RT5677_DSP_OUTB_45_MIXER_CTRL … #define RT5677_DSP_OUTB_67_MIXER_CTRL … /* General Control */ #define RT5677_DIG_MISC … #define RT5677_GEN_CTRL1 … #define RT5677_GEN_CTRL2 … /* DSP Mode I2C Control*/ #define RT5677_DSP_I2C_OP_CODE … #define RT5677_DSP_I2C_ADDR_LSB … #define RT5677_DSP_I2C_ADDR_MSB … #define RT5677_DSP_I2C_DATA_LSB … #define RT5677_DSP_I2C_DATA_MSB … /* Index of Codec Private Register definition */ #define RT5677_PR_DRC1_CTRL_1 … #define RT5677_PR_DRC1_CTRL_2 … #define RT5677_PR_DRC1_CTRL_3 … #define RT5677_PR_DRC1_CTRL_4 … #define RT5677_PR_DRC1_CTRL_5 … #define RT5677_PR_DRC1_CTRL_6 … #define RT5677_PR_DRC1_CTRL_7 … #define RT5677_PR_DRC2_CTRL_1 … #define RT5677_PR_DRC2_CTRL_2 … #define RT5677_PR_DRC2_CTRL_3 … #define RT5677_PR_DRC2_CTRL_4 … #define RT5677_PR_DRC2_CTRL_5 … #define RT5677_PR_DRC2_CTRL_6 … #define RT5677_PR_DRC2_CTRL_7 … #define RT5677_BIAS_CUR1 … #define RT5677_BIAS_CUR2 … #define RT5677_BIAS_CUR3 … #define RT5677_BIAS_CUR4 … #define RT5677_BIAS_CUR5 … #define RT5677_VREF_LOUT_CTRL … #define RT5677_DIG_VOL_CTRL1 … #define RT5677_DIG_VOL_CTRL2 … #define RT5677_ANA_ADC_GAIN_CTRL … #define RT5677_VAD_SRAM_TEST1 … #define RT5677_VAD_SRAM_TEST2 … #define RT5677_VAD_SRAM_TEST3 … #define RT5677_VAD_SRAM_TEST4 … #define RT5677_PAD_DRV_CTRL … #define RT5677_DIG_IN_PIN_ST_CTRL1 … #define RT5677_DIG_IN_PIN_ST_CTRL2 … #define RT5677_DIG_IN_PIN_ST_CTRL3 … #define RT5677_PLL1_INT … #define RT5677_PLL2_INT … #define RT5677_TEST_CTRL1 … #define RT5677_TEST_CTRL2 … #define RT5677_TEST_CTRL3 … #define RT5677_CHOP_DAC_ADC … #define RT5677_SOFT_DEPOP_DAC_CLK_CTRL … #define RT5677_CROSS_OVER_FILTER1 … #define RT5677_CROSS_OVER_FILTER2 … #define RT5677_CROSS_OVER_FILTER3 … #define RT5677_CROSS_OVER_FILTER4 … #define RT5677_CROSS_OVER_FILTER5 … #define RT5677_CROSS_OVER_FILTER6 … #define RT5677_CROSS_OVER_FILTER7 … #define RT5677_CROSS_OVER_FILTER8 … #define RT5677_CROSS_OVER_FILTER9 … #define RT5677_CROSS_OVER_FILTER10 … /* global definition */ #define RT5677_L_MUTE … #define RT5677_L_MUTE_SFT … #define RT5677_VOL_L_MUTE … #define RT5677_VOL_L_SFT … #define RT5677_R_MUTE … #define RT5677_R_MUTE_SFT … #define RT5677_VOL_R_MUTE … #define RT5677_VOL_R_SFT … #define RT5677_L_VOL_MASK … #define RT5677_L_VOL_SFT … #define RT5677_R_VOL_MASK … #define RT5677_R_VOL_SFT … /* LOUT1 Control (0x01) */ #define RT5677_LOUT1_L_MUTE … #define RT5677_LOUT1_L_MUTE_SFT … #define RT5677_LOUT1_L_DF … #define RT5677_LOUT1_L_DF_SFT … #define RT5677_LOUT2_L_MUTE … #define RT5677_LOUT2_L_MUTE_SFT … #define RT5677_LOUT2_L_DF … #define RT5677_LOUT2_L_DF_SFT … #define RT5677_LOUT3_L_MUTE … #define RT5677_LOUT3_L_MUTE_SFT … #define RT5677_LOUT3_L_DF … #define RT5677_LOUT3_L_DF_SFT … #define RT5677_LOUT1_ENH_DRV … #define RT5677_LOUT1_ENH_DRV_SFT … #define RT5677_LOUT2_ENH_DRV … #define RT5677_LOUT2_ENH_DRV_SFT … #define RT5677_LOUT3_ENH_DRV … #define RT5677_LOUT3_ENH_DRV_SFT … /* IN1 Control (0x03) */ #define RT5677_BST_MASK1 … #define RT5677_BST_SFT1 … #define RT5677_BST_MASK2 … #define RT5677_BST_SFT2 … #define RT5677_IN_DF1 … #define RT5677_IN_DF1_SFT … #define RT5677_IN_DF2 … #define RT5677_IN_DF2_SFT … /* Micbias Control (0x04) */ #define RT5677_MICBIAS1_OUTVOLT_MASK … #define RT5677_MICBIAS1_OUTVOLT_SFT … #define RT5677_MICBIAS1_OUTVOLT_2_7V … #define RT5677_MICBIAS1_OUTVOLT_2_25V … #define RT5677_MICBIAS1_CTRL_VDD_MASK … #define RT5677_MICBIAS1_CTRL_VDD_SFT … #define RT5677_MICBIAS1_CTRL_VDD_1_8V … #define RT5677_MICBIAS1_CTRL_VDD_3_3V … #define RT5677_MICBIAS1_OVCD_MASK … #define RT5677_MICBIAS1_OVCD_SHIFT … #define RT5677_MICBIAS1_OVCD_DIS … #define RT5677_MICBIAS1_OVCD_EN … #define RT5677_MICBIAS1_OVTH_MASK … #define RT5677_MICBIAS1_OVTH_SFT … #define RT5677_MICBIAS1_OVTH_640UA … #define RT5677_MICBIAS1_OVTH_1280UA … #define RT5677_MICBIAS1_OVTH_1920UA … /* SLIMbus Parameter (0x07) */ /* SLIMbus Rx (0x08) */ #define RT5677_SLB_ADC4_MASK … #define RT5677_SLB_ADC4_SFT … #define RT5677_SLB_ADC3_MASK … #define RT5677_SLB_ADC3_SFT … #define RT5677_SLB_ADC2_MASK … #define RT5677_SLB_ADC2_SFT … #define RT5677_SLB_ADC1_MASK … #define RT5677_SLB_ADC1_SFT … /* SLIMBus control (0x09) */ /* Sidetone Control (0x13) */ #define RT5677_ST_HPF_SEL_MASK … #define RT5677_ST_HPF_SEL_SFT … #define RT5677_ST_HPF_PATH … #define RT5677_ST_HPF_PATH_SFT … #define RT5677_ST_SEL_MASK … #define RT5677_ST_SEL_SFT … #define RT5677_ST_EN … #define RT5677_ST_EN_SFT … #define RT5677_ST_GAIN … #define RT5677_ST_GAIN_SFT … #define RT5677_ST_VOL_MASK … #define RT5677_ST_VOL_SFT … /* Analog DAC1/2/3 Source Control (0x15) */ #define RT5677_ANA_DAC3_SRC_SEL_MASK … #define RT5677_ANA_DAC3_SRC_SEL_SFT … #define RT5677_ANA_DAC1_2_SRC_SEL_MASK … #define RT5677_ANA_DAC1_2_SRC_SEL_SFT … /* IF/DSP to DAC3/4 Mixer Control (0x16) */ #define RT5677_M_DAC4_L_VOL … #define RT5677_M_DAC4_L_VOL_SFT … #define RT5677_SEL_DAC4_L_SRC_MASK … #define RT5677_SEL_DAC4_L_SRC_SFT … #define RT5677_M_DAC4_R_VOL … #define RT5677_M_DAC4_R_VOL_SFT … #define RT5677_SEL_DAC4_R_SRC_MASK … #define RT5677_SEL_DAC4_R_SRC_SFT … #define RT5677_M_DAC3_L_VOL … #define RT5677_M_DAC3_L_VOL_SFT … #define RT5677_SEL_DAC3_L_SRC_MASK … #define RT5677_SEL_DAC3_L_SRC_SFT … #define RT5677_M_DAC3_R_VOL … #define RT5677_M_DAC3_R_VOL_SFT … #define RT5677_SEL_DAC3_R_SRC_MASK … #define RT5677_SEL_DAC3_R_SRC_SFT … /* DAC4 Digital Volume (0x17) */ #define RT5677_DAC4_L_VOL_MASK … #define RT5677_DAC4_L_VOL_SFT … #define RT5677_DAC4_R_VOL_MASK … #define RT5677_DAC4_R_VOL_SFT … /* DAC3 Digital Volume (0x18) */ #define RT5677_DAC3_L_VOL_MASK … #define RT5677_DAC3_L_VOL_SFT … #define RT5677_DAC3_R_VOL_MASK … #define RT5677_DAC3_R_VOL_SFT … /* DAC3 Digital Volume (0x19) */ #define RT5677_DAC1_L_VOL_MASK … #define RT5677_DAC1_L_VOL_SFT … #define RT5677_DAC1_R_VOL_MASK … #define RT5677_DAC1_R_VOL_SFT … /* DAC2 Digital Volume (0x1a) */ #define RT5677_DAC2_L_VOL_MASK … #define RT5677_DAC2_L_VOL_SFT … #define RT5677_DAC2_R_VOL_MASK … #define RT5677_DAC2_R_VOL_SFT … /* IF/DSP to DAC2 Mixer Control (0x1b) */ #define RT5677_M_DAC2_L_VOL … #define RT5677_M_DAC2_L_VOL_SFT … #define RT5677_SEL_DAC2_L_SRC_MASK … #define RT5677_SEL_DAC2_L_SRC_SFT … #define RT5677_M_DAC2_R_VOL … #define RT5677_M_DAC2_R_VOL_SFT … #define RT5677_SEL_DAC2_R_SRC_MASK … #define RT5677_SEL_DAC2_R_SRC_SFT … /* Stereo1 ADC Digital Volume Control (0x1c) */ #define RT5677_STO1_ADC_L_VOL_MASK … #define RT5677_STO1_ADC_L_VOL_SFT … #define RT5677_STO1_ADC_R_VOL_MASK … #define RT5677_STO1_ADC_R_VOL_SFT … /* Mono ADC Digital Volume Control (0x1d) */ #define RT5677_MONO_ADC_L_VOL_MASK … #define RT5677_MONO_ADC_L_VOL_SFT … #define RT5677_MONO_ADC_R_VOL_MASK … #define RT5677_MONO_ADC_R_VOL_SFT … /* Stereo 1/2 ADC Boost Gain Control (0x1e) */ #define RT5677_STO1_ADC_L_BST_MASK … #define RT5677_STO1_ADC_L_BST_SFT … #define RT5677_STO1_ADC_R_BST_MASK … #define RT5677_STO1_ADC_R_BST_SFT … #define RT5677_STO1_ADC_COMP_MASK … #define RT5677_STO1_ADC_COMP_SFT … #define RT5677_STO2_ADC_L_BST_MASK … #define RT5677_STO2_ADC_L_BST_SFT … #define RT5677_STO2_ADC_R_BST_MASK … #define RT5677_STO2_ADC_R_BST_SFT … #define RT5677_STO2_ADC_COMP_MASK … #define RT5677_STO2_ADC_COMP_SFT … /* Stereo2 ADC Digital Volume Control (0x1f) */ #define RT5677_STO2_ADC_L_VOL_MASK … #define RT5677_STO2_ADC_L_VOL_SFT … #define RT5677_STO2_ADC_R_VOL_MASK … #define RT5677_STO2_ADC_R_VOL_SFT … /* ADC Boost Gain Control 2 (0x20) */ #define RT5677_MONO_ADC_L_BST_MASK … #define RT5677_MONO_ADC_L_BST_SFT … #define RT5677_MONO_ADC_R_BST_MASK … #define RT5677_MONO_ADC_R_BST_SFT … #define RT5677_MONO_ADC_COMP_MASK … #define RT5677_MONO_ADC_COMP_SFT … /* Stereo 3/4 ADC Boost Gain Control (0x21) */ #define RT5677_STO3_ADC_L_BST_MASK … #define RT5677_STO3_ADC_L_BST_SFT … #define RT5677_STO3_ADC_R_BST_MASK … #define RT5677_STO3_ADC_R_BST_SFT … #define RT5677_STO3_ADC_COMP_MASK … #define RT5677_STO3_ADC_COMP_SFT … #define RT5677_STO4_ADC_L_BST_MASK … #define RT5677_STO4_ADC_L_BST_SFT … #define RT5677_STO4_ADC_R_BST_MASK … #define RT5677_STO4_ADC_R_BST_SFT … #define RT5677_STO4_ADC_COMP_MASK … #define RT5677_STO4_ADC_COMP_SFT … /* Stereo3 ADC Digital Volume Control (0x22) */ #define RT5677_STO3_ADC_L_VOL_MASK … #define RT5677_STO3_ADC_L_VOL_SFT … #define RT5677_STO3_ADC_R_VOL_MASK … #define RT5677_STO3_ADC_R_VOL_SFT … /* Stereo4 ADC Digital Volume Control (0x23) */ #define RT5677_STO4_ADC_L_VOL_MASK … #define RT5677_STO4_ADC_L_VOL_SFT … #define RT5677_STO4_ADC_R_VOL_MASK … #define RT5677_STO4_ADC_R_VOL_SFT … /* Stereo4 ADC Mixer control (0x24) */ #define RT5677_M_STO4_ADC_L2 … #define RT5677_M_STO4_ADC_L2_SFT … #define RT5677_M_STO4_ADC_L1 … #define RT5677_M_STO4_ADC_L1_SFT … #define RT5677_SEL_STO4_ADC1_MASK … #define RT5677_SEL_STO4_ADC1_SFT … #define RT5677_SEL_STO4_ADC2_MASK … #define RT5677_SEL_STO4_ADC2_SFT … #define RT5677_SEL_STO4_DMIC_MASK … #define RT5677_SEL_STO4_DMIC_SFT … #define RT5677_M_STO4_ADC_R1 … #define RT5677_M_STO4_ADC_R1_SFT … #define RT5677_M_STO4_ADC_R2 … #define RT5677_M_STO4_ADC_R2_SFT … /* Stereo3 ADC Mixer control (0x25) */ #define RT5677_M_STO3_ADC_L2 … #define RT5677_M_STO3_ADC_L2_SFT … #define RT5677_M_STO3_ADC_L1 … #define RT5677_M_STO3_ADC_L1_SFT … #define RT5677_SEL_STO3_ADC1_MASK … #define RT5677_SEL_STO3_ADC1_SFT … #define RT5677_SEL_STO3_ADC2_MASK … #define RT5677_SEL_STO3_ADC2_SFT … #define RT5677_SEL_STO3_DMIC_MASK … #define RT5677_SEL_STO3_DMIC_SFT … #define RT5677_M_STO3_ADC_R1 … #define RT5677_M_STO3_ADC_R1_SFT … #define RT5677_M_STO3_ADC_R2 … #define RT5677_M_STO3_ADC_R2_SFT … /* Stereo2 ADC Mixer Control (0x26) */ #define RT5677_M_STO2_ADC_L2 … #define RT5677_M_STO2_ADC_L2_SFT … #define RT5677_M_STO2_ADC_L1 … #define RT5677_M_STO2_ADC_L1_SFT … #define RT5677_SEL_STO2_ADC1_MASK … #define RT5677_SEL_STO2_ADC1_SFT … #define RT5677_SEL_STO2_ADC2_MASK … #define RT5677_SEL_STO2_ADC2_SFT … #define RT5677_SEL_STO2_DMIC_MASK … #define RT5677_SEL_STO2_DMIC_SFT … #define RT5677_M_STO2_ADC_R1 … #define RT5677_M_STO2_ADC_R1_SFT … #define RT5677_M_STO2_ADC_R2 … #define RT5677_M_STO2_ADC_R2_SFT … #define RT5677_SEL_STO2_LR_MIX_MASK … #define RT5677_SEL_STO2_LR_MIX_SFT … #define RT5677_SEL_STO2_LR_MIX_L … #define RT5677_SEL_STO2_LR_MIX_LR … /* Stereo1 ADC Mixer control (0x27) */ #define RT5677_M_STO1_ADC_L2 … #define RT5677_M_STO1_ADC_L2_SFT … #define RT5677_M_STO1_ADC_L1 … #define RT5677_M_STO1_ADC_L1_SFT … #define RT5677_SEL_STO1_ADC1_MASK … #define RT5677_SEL_STO1_ADC1_SFT … #define RT5677_SEL_STO1_ADC2_MASK … #define RT5677_SEL_STO1_ADC2_SFT … #define RT5677_SEL_STO1_DMIC_MASK … #define RT5677_SEL_STO1_DMIC_SFT … #define RT5677_M_STO1_ADC_R1 … #define RT5677_M_STO1_ADC_R1_SFT … #define RT5677_M_STO1_ADC_R2 … #define RT5677_M_STO1_ADC_R2_SFT … /* Mono ADC Mixer control (0x28) */ #define RT5677_M_MONO_ADC_L2 … #define RT5677_M_MONO_ADC_L2_SFT … #define RT5677_M_MONO_ADC_L1 … #define RT5677_M_MONO_ADC_L1_SFT … #define RT5677_SEL_MONO_ADC_L1_MASK … #define RT5677_SEL_MONO_ADC_L1_SFT … #define RT5677_SEL_MONO_ADC_L2_MASK … #define RT5677_SEL_MONO_ADC_L2_SFT … #define RT5677_SEL_MONO_DMIC_L_MASK … #define RT5677_SEL_MONO_DMIC_L_SFT … #define RT5677_M_MONO_ADC_R1 … #define RT5677_M_MONO_ADC_R1_SFT … #define RT5677_M_MONO_ADC_R2 … #define RT5677_M_MONO_ADC_R2_SFT … #define RT5677_SEL_MONO_ADC_R1_MASK … #define RT5677_SEL_MONO_ADC_R1_SFT … #define RT5677_SEL_MONO_ADC_R2_MASK … #define RT5677_SEL_MONO_ADC_R2_SFT … #define RT5677_SEL_MONO_DMIC_R_MASK … #define RT5677_SEL_MONO_DMIC_R_SFT … /* ADC/IF/DSP to DAC1 Mixer control (0x29) */ #define RT5677_M_ADDA_MIXER1_L … #define RT5677_M_ADDA_MIXER1_L_SFT … #define RT5677_M_DAC1_L … #define RT5677_M_DAC1_L_SFT … #define RT5677_DAC1_L_SEL_MASK … #define RT5677_DAC1_L_SEL_SFT … #define RT5677_M_ADDA_MIXER1_R … #define RT5677_M_ADDA_MIXER1_R_SFT … #define RT5677_M_DAC1_R … #define RT5677_M_DAC1_R_SFT … #define RT5677_ADDA1_SEL_MASK … #define RT5677_ADDA1_SEL_SFT … /* Stereo1 DAC Mixer L/R Control (0x2a) */ #define RT5677_M_ST_DAC1_L … #define RT5677_M_ST_DAC1_L_SFT … #define RT5677_M_DAC1_L_STO_L … #define RT5677_M_DAC1_L_STO_L_SFT … #define RT5677_DAC1_L_STO_L_VOL_MASK … #define RT5677_DAC1_L_STO_L_VOL_SFT … #define RT5677_M_DAC2_L_STO_L … #define RT5677_M_DAC2_L_STO_L_SFT … #define RT5677_DAC2_L_STO_L_VOL_MASK … #define RT5677_DAC2_L_STO_L_VOL_SFT … #define RT5677_M_DAC1_R_STO_L … #define RT5677_M_DAC1_R_STO_L_SFT … #define RT5677_DAC1_R_STO_L_VOL_MASK … #define RT5677_DAC1_R_STO_L_VOL_SFT … #define RT5677_M_ST_DAC1_R … #define RT5677_M_ST_DAC1_R_SFT … #define RT5677_M_DAC1_R_STO_R … #define RT5677_M_DAC1_R_STO_R_SFT … #define RT5677_DAC1_R_STO_R_VOL_MASK … #define RT5677_DAC1_R_STO_R_VOL_SFT … #define RT5677_M_DAC2_R_STO_R … #define RT5677_M_DAC2_R_STO_R_SFT … #define RT5677_DAC2_R_STO_R_VOL_MASK … #define RT5677_DAC2_R_STO_R_VOL_SFT … #define RT5677_M_DAC1_L_STO_R … #define RT5677_M_DAC1_L_STO_R_SFT … #define RT5677_DAC1_L_STO_R_VOL_MASK … #define RT5677_DAC1_L_STO_R_VOL_SFT … /* Mono DAC Mixer L/R Control (0x2b) */ #define RT5677_M_ST_DAC2_L … #define RT5677_M_ST_DAC2_L_SFT … #define RT5677_M_DAC2_L_MONO_L … #define RT5677_M_DAC2_L_MONO_L_SFT … #define RT5677_DAC2_L_MONO_L_VOL_MASK … #define RT5677_DAC2_L_MONO_L_VOL_SFT … #define RT5677_M_DAC2_R_MONO_L … #define RT5677_M_DAC2_R_MONO_L_SFT … #define RT5677_DAC2_R_MONO_L_VOL_MASK … #define RT5677_DAC2_R_MONO_L_VOL_SFT … #define RT5677_M_DAC1_L_MONO_L … #define RT5677_M_DAC1_L_MONO_L_SFT … #define RT5677_DAC1_L_MONO_L_VOL_MASK … #define RT5677_DAC1_L_MONO_L_VOL_SFT … #define RT5677_M_ST_DAC2_R … #define RT5677_M_ST_DAC2_R_SFT … #define RT5677_M_DAC2_R_MONO_R … #define RT5677_M_DAC2_R_MONO_R_SFT … #define RT5677_DAC2_R_MONO_R_VOL_MASK … #define RT5677_DAC2_R_MONO_R_VOL_SFT … #define RT5677_M_DAC1_R_MONO_R … #define RT5677_M_DAC1_R_MONO_R_SFT … #define RT5677_DAC1_R_MONO_R_VOL_MASK … #define RT5677_DAC1_R_MONO_R_VOL_SFT … #define RT5677_M_DAC2_L_MONO_R … #define RT5677_M_DAC2_L_MONO_R_SFT … #define RT5677_DAC2_L_MONO_R_VOL_MASK … #define RT5677_DAC2_L_MONO_R_VOL_SFT … /* DD Mixer 1 Control (0x2c) */ #define RT5677_M_STO_L_DD1_L … #define RT5677_M_STO_L_DD1_L_SFT … #define RT5677_STO_L_DD1_L_VOL_MASK … #define RT5677_STO_L_DD1_L_VOL_SFT … #define RT5677_M_MONO_L_DD1_L … #define RT5677_M_MONO_L_DD1_L_SFT … #define RT5677_MONO_L_DD1_L_VOL_MASK … #define RT5677_MONO_L_DD1_L_VOL_SFT … #define RT5677_M_DAC3_L_DD1_L … #define RT5677_M_DAC3_L_DD1_L_SFT … #define RT5677_DAC3_L_DD1_L_VOL_MASK … #define RT5677_DAC3_L_DD1_L_VOL_SFT … #define RT5677_M_DAC3_R_DD1_L … #define RT5677_M_DAC3_R_DD1_L_SFT … #define RT5677_DAC3_R_DD1_L_VOL_MASK … #define RT5677_DAC3_R_DD1_L_VOL_SFT … #define RT5677_M_STO_R_DD1_R … #define RT5677_M_STO_R_DD1_R_SFT … #define RT5677_STO_R_DD1_R_VOL_MASK … #define RT5677_STO_R_DD1_R_VOL_SFT … #define RT5677_M_MONO_R_DD1_R … #define RT5677_M_MONO_R_DD1_R_SFT … #define RT5677_MONO_R_DD1_R_VOL_MASK … #define RT5677_MONO_R_DD1_R_VOL_SFT … #define RT5677_M_DAC3_R_DD1_R … #define RT5677_M_DAC3_R_DD1_R_SFT … #define RT5677_DAC3_R_DD1_R_VOL_MASK … #define RT5677_DAC3_R_DD1_R_VOL_SFT … #define RT5677_M_DAC3_L_DD1_R … #define RT5677_M_DAC3_L_DD1_R_SFT … #define RT5677_DAC3_L_DD1_R_VOL_MASK … #define RT5677_DAC3_L_DD1_R_VOL_SFT … /* DD Mixer 2 Control (0x2d) */ #define RT5677_M_STO_L_DD2_L … #define RT5677_M_STO_L_DD2_L_SFT … #define RT5677_STO_L_DD2_L_VOL_MASK … #define RT5677_STO_L_DD2_L_VOL_SFT … #define RT5677_M_MONO_L_DD2_L … #define RT5677_M_MONO_L_DD2_L_SFT … #define RT5677_MONO_L_DD2_L_VOL_MASK … #define RT5677_MONO_L_DD2_L_VOL_SFT … #define RT5677_M_DAC4_L_DD2_L … #define RT5677_M_DAC4_L_DD2_L_SFT … #define RT5677_DAC4_L_DD2_L_VOL_MASK … #define RT5677_DAC4_L_DD2_L_VOL_SFT … #define RT5677_M_DAC4_R_DD2_L … #define RT5677_M_DAC4_R_DD2_L_SFT … #define RT5677_DAC4_R_DD2_L_VOL_MASK … #define RT5677_DAC4_R_DD2_L_VOL_SFT … #define RT5677_M_STO_R_DD2_R … #define RT5677_M_STO_R_DD2_R_SFT … #define RT5677_STO_R_DD2_R_VOL_MASK … #define RT5677_STO_R_DD2_R_VOL_SFT … #define RT5677_M_MONO_R_DD2_R … #define RT5677_M_MONO_R_DD2_R_SFT … #define RT5677_MONO_R_DD2_R_VOL_MASK … #define RT5677_MONO_R_DD2_R_VOL_SFT … #define RT5677_M_DAC4_R_DD2_R … #define RT5677_M_DAC4_R_DD2_R_SFT … #define RT5677_DAC4_R_DD2_R_VOL_MASK … #define RT5677_DAC4_R_DD2_R_VOL_SFT … #define RT5677_M_DAC4_L_DD2_R … #define RT5677_M_DAC4_L_DD2_R_SFT … #define RT5677_DAC4_L_DD2_R_VOL_MASK … #define RT5677_DAC4_L_DD2_R_VOL_SFT … /* IF3 data control (0x2f) */ #define RT5677_IF3_DAC_SEL_MASK … #define RT5677_IF3_DAC_SEL_SFT … #define RT5677_IF3_ADC_SEL_MASK … #define RT5677_IF3_ADC_SEL_SFT … #define RT5677_IF3_ADC_IN_MASK … #define RT5677_IF3_ADC_IN_SFT … /* IF4 data control (0x30) */ #define RT5677_IF4_ADC_IN_MASK … #define RT5677_IF4_ADC_IN_SFT … #define RT5677_IF4_DAC_SEL_MASK … #define RT5677_IF4_DAC_SEL_SFT … #define RT5677_IF4_ADC_SEL_MASK … #define RT5677_IF4_ADC_SEL_SFT … /* PDM Output Control (0x31) */ #define RT5677_M_PDM1_L … #define RT5677_M_PDM1_L_SFT … #define RT5677_SEL_PDM1_L_MASK … #define RT5677_SEL_PDM1_L_SFT … #define RT5677_M_PDM1_R … #define RT5677_M_PDM1_R_SFT … #define RT5677_SEL_PDM1_R_MASK … #define RT5677_SEL_PDM1_R_SFT … #define RT5677_M_PDM2_L … #define RT5677_M_PDM2_L_SFT … #define RT5677_SEL_PDM2_L_MASK … #define RT5677_SEL_PDM2_L_SFT … #define RT5677_M_PDM2_R … #define RT5677_M_PDM2_R_SFT … #define RT5677_SEL_PDM2_R_MASK … #define RT5677_SEL_PDM2_R_SFT … /* PDM I2C / Data Control 1 (0x32) */ #define RT5677_PDM2_PW_DOWN … #define RT5677_PDM1_PW_DOWN … #define RT5677_PDM2_BUSY … #define RT5677_PDM1_BUSY … #define RT5677_PDM_PATTERN … #define RT5677_PDM_GAIN … #define RT5677_PDM_DIV_MASK … /* PDM I2C / Data Control 2 (0x33) */ #define RT5677_PDM1_I2C_ID … #define RT5677_PDM1_EXE … #define RT5677_PDM1_I2C_CMD … #define RT5677_PDM1_I2C_EXE … #define RT5677_PDM1_I2C_BUSY … #define RT5677_PDM2_I2C_ID … #define RT5677_PDM2_EXE … #define RT5677_PDM2_I2C_CMD … #define RT5677_PDM2_I2C_EXE … #define RT5677_PDM2_I2C_BUSY … /* TDM1 control 1 (0x3b) */ #define RT5677_IF1_ADC_MODE_MASK … #define RT5677_IF1_ADC_MODE_SFT … #define RT5677_IF1_ADC_MODE_I2S … #define RT5677_IF1_ADC_MODE_TDM … #define RT5677_IF1_ADC1_SWAP_MASK … #define RT5677_IF1_ADC1_SWAP_SFT … #define RT5677_IF1_ADC2_SWAP_MASK … #define RT5677_IF1_ADC2_SWAP_SFT … #define RT5677_IF1_ADC3_SWAP_MASK … #define RT5677_IF1_ADC3_SWAP_SFT … #define RT5677_IF1_ADC4_SWAP_MASK … #define RT5677_IF1_ADC4_SWAP_SFT … /* TDM1 control 2 (0x3c) */ #define RT5677_IF1_ADC4_MASK … #define RT5677_IF1_ADC4_SFT … #define RT5677_IF1_ADC3_MASK … #define RT5677_IF1_ADC3_SFT … #define RT5677_IF1_ADC2_MASK … #define RT5677_IF1_ADC2_SFT … #define RT5677_IF1_ADC1_MASK … #define RT5677_IF1_ADC1_SFT … #define RT5677_IF1_ADC_CTRL_MASK … #define RT5677_IF1_ADC_CTRL_SFT … /* TDM1 control 4 (0x3e) */ #define RT5677_IF1_DAC0_MASK … #define RT5677_IF1_DAC0_SFT … #define RT5677_IF1_DAC1_MASK … #define RT5677_IF1_DAC1_SFT … #define RT5677_IF1_DAC2_MASK … #define RT5677_IF1_DAC2_SFT … #define RT5677_IF1_DAC3_MASK … #define RT5677_IF1_DAC3_SFT … /* TDM1 control 5 (0x3f) */ #define RT5677_IF1_DAC4_MASK … #define RT5677_IF1_DAC4_SFT … #define RT5677_IF1_DAC5_MASK … #define RT5677_IF1_DAC5_SFT … #define RT5677_IF1_DAC6_MASK … #define RT5677_IF1_DAC6_SFT … #define RT5677_IF1_DAC7_MASK … #define RT5677_IF1_DAC7_SFT … /* TDM2 control 1 (0x40) */ #define RT5677_IF2_ADC_MODE_MASK … #define RT5677_IF2_ADC_MODE_SFT … #define RT5677_IF2_ADC_MODE_I2S … #define RT5677_IF2_ADC_MODE_TDM … #define RT5677_IF2_ADC1_SWAP_MASK … #define RT5677_IF2_ADC1_SWAP_SFT … #define RT5677_IF2_ADC2_SWAP_MASK … #define RT5677_IF2_ADC2_SWAP_SFT … #define RT5677_IF2_ADC3_SWAP_MASK … #define RT5677_IF2_ADC3_SWAP_SFT … #define RT5677_IF2_ADC4_SWAP_MASK … #define RT5677_IF2_ADC4_SWAP_SFT … /* TDM2 control 2 (0x41) */ #define RT5677_IF2_ADC4_MASK … #define RT5677_IF2_ADC4_SFT … #define RT5677_IF2_ADC3_MASK … #define RT5677_IF2_ADC3_SFT … #define RT5677_IF2_ADC2_MASK … #define RT5677_IF2_ADC2_SFT … #define RT5677_IF2_ADC1_MASK … #define RT5677_IF2_ADC1_SFT … #define RT5677_IF2_ADC_CTRL_MASK … #define RT5677_IF2_ADC_CTRL_SFT … /* TDM2 control 4 (0x43) */ #define RT5677_IF2_DAC0_MASK … #define RT5677_IF2_DAC0_SFT … #define RT5677_IF2_DAC1_MASK … #define RT5677_IF2_DAC1_SFT … #define RT5677_IF2_DAC2_MASK … #define RT5677_IF2_DAC2_SFT … #define RT5677_IF2_DAC3_MASK … #define RT5677_IF2_DAC3_SFT … /* TDM2 control 5 (0x44) */ #define RT5677_IF2_DAC4_MASK … #define RT5677_IF2_DAC4_SFT … #define RT5677_IF2_DAC5_MASK … #define RT5677_IF2_DAC5_SFT … #define RT5677_IF2_DAC6_MASK … #define RT5677_IF2_DAC6_SFT … #define RT5677_IF2_DAC7_MASK … #define RT5677_IF2_DAC7_SFT … /* Digital Microphone Control 1 (0x50) */ #define RT5677_DMIC_1_EN_MASK … #define RT5677_DMIC_1_EN_SFT … #define RT5677_DMIC_1_DIS … #define RT5677_DMIC_1_EN … #define RT5677_DMIC_2_EN_MASK … #define RT5677_DMIC_2_EN_SFT … #define RT5677_DMIC_2_DIS … #define RT5677_DMIC_2_EN … #define RT5677_DMIC_L_STO1_LH_MASK … #define RT5677_DMIC_L_STO1_LH_SFT … #define RT5677_DMIC_L_STO1_LH_FALLING … #define RT5677_DMIC_L_STO1_LH_RISING … #define RT5677_DMIC_R_STO1_LH_MASK … #define RT5677_DMIC_R_STO1_LH_SFT … #define RT5677_DMIC_R_STO1_LH_FALLING … #define RT5677_DMIC_R_STO1_LH_RISING … #define RT5677_DMIC_L_STO3_LH_MASK … #define RT5677_DMIC_L_STO3_LH_SFT … #define RT5677_DMIC_L_STO3_LH_FALLING … #define RT5677_DMIC_L_STO3_LH_RISING … #define RT5677_DMIC_R_STO3_LH_MASK … #define RT5677_DMIC_R_STO3_LH_SFT … #define RT5677_DMIC_R_STO3_LH_FALLING … #define RT5677_DMIC_R_STO3_LH_RISING … #define RT5677_DMIC_L_STO2_LH_MASK … #define RT5677_DMIC_L_STO2_LH_SFT … #define RT5677_DMIC_L_STO2_LH_FALLING … #define RT5677_DMIC_L_STO2_LH_RISING … #define RT5677_DMIC_R_STO2_LH_MASK … #define RT5677_DMIC_R_STO2_LH_SFT … #define RT5677_DMIC_R_STO2_LH_FALLING … #define RT5677_DMIC_R_STO2_LH_RISING … #define RT5677_DMIC_CLK_MASK … #define RT5677_DMIC_CLK_SFT … #define RT5677_DMIC_3_EN_MASK … #define RT5677_DMIC_3_EN_SFT … #define RT5677_DMIC_3_DIS … #define RT5677_DMIC_3_EN … #define RT5677_DMIC_R_MONO_LH_MASK … #define RT5677_DMIC_R_MONO_LH_SFT … #define RT5677_DMIC_R_MONO_LH_FALLING … #define RT5677_DMIC_R_MONO_LH_RISING … #define RT5677_DMIC_L_STO4_LH_MASK … #define RT5677_DMIC_L_STO4_LH_SFT … #define RT5677_DMIC_L_STO4_LH_FALLING … #define RT5677_DMIC_L_STO4_LH_RISING … #define RT5677_DMIC_R_STO4_LH_MASK … #define RT5677_DMIC_R_STO4_LH_SFT … #define RT5677_DMIC_R_STO4_LH_FALLING … #define RT5677_DMIC_R_STO4_LH_RISING … /* Digital Microphone Control 2 (0x51) */ #define RT5677_DMIC_4_EN_MASK … #define RT5677_DMIC_4_EN_SFT … #define RT5677_DMIC_4_DIS … #define RT5677_DMIC_4_EN … #define RT5677_DMIC_4L_LH_MASK … #define RT5677_DMIC_4L_LH_SFT … #define RT5677_DMIC_4L_LH_FALLING … #define RT5677_DMIC_4L_LH_RISING … #define RT5677_DMIC_4R_LH_MASK … #define RT5677_DMIC_4R_LH_SFT … #define RT5677_DMIC_4R_LH_FALLING … #define RT5677_DMIC_4R_LH_RISING … #define RT5677_DMIC_3L_LH_MASK … #define RT5677_DMIC_3L_LH_SFT … #define RT5677_DMIC_3L_LH_FALLING … #define RT5677_DMIC_3L_LH_RISING … #define RT5677_DMIC_3R_LH_MASK … #define RT5677_DMIC_3R_LH_SFT … #define RT5677_DMIC_3R_LH_FALLING … #define RT5677_DMIC_3R_LH_RISING … #define RT5677_DMIC_2L_LH_MASK … #define RT5677_DMIC_2L_LH_SFT … #define RT5677_DMIC_2L_LH_FALLING … #define RT5677_DMIC_2L_LH_RISING … #define RT5677_DMIC_2R_LH_MASK … #define RT5677_DMIC_2R_LH_SFT … #define RT5677_DMIC_2R_LH_FALLING … #define RT5677_DMIC_2R_LH_RISING … #define RT5677_DMIC_1L_LH_MASK … #define RT5677_DMIC_1L_LH_SFT … #define RT5677_DMIC_1L_LH_FALLING … #define RT5677_DMIC_1L_LH_RISING … #define RT5677_DMIC_1R_LH_MASK … #define RT5677_DMIC_1R_LH_SFT … #define RT5677_DMIC_1R_LH_FALLING … #define RT5677_DMIC_1R_LH_RISING … /* Power Management for Digital 1 (0x61) */ #define RT5677_PWR_I2S1 … #define RT5677_PWR_I2S1_BIT … #define RT5677_PWR_I2S2 … #define RT5677_PWR_I2S2_BIT … #define RT5677_PWR_I2S3 … #define RT5677_PWR_I2S3_BIT … #define RT5677_PWR_DAC1 … #define RT5677_PWR_DAC1_BIT … #define RT5677_PWR_DAC2 … #define RT5677_PWR_DAC2_BIT … #define RT5677_PWR_I2S4 … #define RT5677_PWR_I2S4_BIT … #define RT5677_PWR_SLB … #define RT5677_PWR_SLB_BIT … #define RT5677_PWR_DAC3 … #define RT5677_PWR_DAC3_BIT … #define RT5677_PWR_ADCFED2 … #define RT5677_PWR_ADCFED2_BIT … #define RT5677_PWR_ADCFED1 … #define RT5677_PWR_ADCFED1_BIT … #define RT5677_PWR_ADC_L … #define RT5677_PWR_ADC_L_BIT … #define RT5677_PWR_ADC_R … #define RT5677_PWR_ADC_R_BIT … #define RT5677_PWR_I2C_MASTER … #define RT5677_PWR_I2C_MASTER_BIT … /* Power Management for Digital 2 (0x62) */ #define RT5677_PWR_ADC_S1F … #define RT5677_PWR_ADC_S1F_BIT … #define RT5677_PWR_ADC_MF_L … #define RT5677_PWR_ADC_MF_L_BIT … #define RT5677_PWR_ADC_MF_R … #define RT5677_PWR_ADC_MF_R_BIT … #define RT5677_PWR_DAC_S1F … #define RT5677_PWR_DAC_S1F_BIT … #define RT5677_PWR_DAC_M2F_L … #define RT5677_PWR_DAC_M2F_L_BIT … #define RT5677_PWR_DAC_M2F_R … #define RT5677_PWR_DAC_M2F_R_BIT … #define RT5677_PWR_DAC_M3F_L … #define RT5677_PWR_DAC_M3F_L_BIT … #define RT5677_PWR_DAC_M3F_R … #define RT5677_PWR_DAC_M3F_R_BIT … #define RT5677_PWR_DAC_M4F_L … #define RT5677_PWR_DAC_M4F_L_BIT … #define RT5677_PWR_DAC_M4F_R … #define RT5677_PWR_DAC_M4F_R_BIT … #define RT5677_PWR_ADC_S2F … #define RT5677_PWR_ADC_S2F_BIT … #define RT5677_PWR_ADC_S3F … #define RT5677_PWR_ADC_S3F_BIT … #define RT5677_PWR_ADC_S4F … #define RT5677_PWR_ADC_S4F_BIT … #define RT5677_PWR_PDM1 … #define RT5677_PWR_PDM1_BIT … #define RT5677_PWR_PDM2 … #define RT5677_PWR_PDM2_BIT … /* Power Management for Analog 1 (0x63) */ #define RT5677_PWR_VREF1 … #define RT5677_PWR_VREF1_BIT … #define RT5677_PWR_FV1 … #define RT5677_PWR_FV1_BIT … #define RT5677_PWR_MB … #define RT5677_PWR_MB_BIT … #define RT5677_PWR_LO1 … #define RT5677_PWR_LO1_BIT … #define RT5677_PWR_BG … #define RT5677_PWR_BG_BIT … #define RT5677_PWR_LO2 … #define RT5677_PWR_LO2_BIT … #define RT5677_PWR_LO3 … #define RT5677_PWR_LO3_BIT … #define RT5677_PWR_VREF2 … #define RT5677_PWR_VREF2_BIT … #define RT5677_PWR_FV2 … #define RT5677_PWR_FV2_BIT … #define RT5677_LDO2_SEL_MASK … #define RT5677_LDO2_SEL_SFT … #define RT5677_LDO1_SEL_MASK … #define RT5677_LDO1_SEL_SFT … /* Power Management for Analog 2 (0x64) */ #define RT5677_PWR_BST1 … #define RT5677_PWR_BST1_BIT … #define RT5677_PWR_BST2 … #define RT5677_PWR_BST2_BIT … #define RT5677_PWR_CLK_MB1 … #define RT5677_PWR_CLK_MB1_BIT … #define RT5677_PWR_SLIM … #define RT5677_PWR_SLIM_BIT … #define RT5677_PWR_MB1 … #define RT5677_PWR_MB1_BIT … #define RT5677_PWR_PP_MB1 … #define RT5677_PWR_PP_MB1_BIT … #define RT5677_PWR_PLL1 … #define RT5677_PWR_PLL1_BIT … #define RT5677_PWR_PLL2 … #define RT5677_PWR_PLL2_BIT … #define RT5677_PWR_CORE … #define RT5677_PWR_CORE_BIT … #define RT5677_PWR_CLK_MB … #define RT5677_PWR_CLK_MB_BIT … #define RT5677_PWR_BST1_P … #define RT5677_PWR_BST1_P_BIT … #define RT5677_PWR_BST2_P … #define RT5677_PWR_BST2_P_BIT … #define RT5677_PWR_IPTV … #define RT5677_PWR_IPTV_BIT … #define RT5677_PWR_25M_CLK … #define RT5677_PWR_25M_CLK_BIT … #define RT5677_PWR_LDO1 … #define RT5677_PWR_LDO1_BIT … /* Power Management for DSP (0x65) */ #define RT5677_PWR_SR7 … #define RT5677_PWR_SR7_BIT … #define RT5677_PWR_SR6 … #define RT5677_PWR_SR6_BIT … #define RT5677_PWR_SR5 … #define RT5677_PWR_SR5_BIT … #define RT5677_PWR_SR4 … #define RT5677_PWR_SR4_BIT … #define RT5677_PWR_SR3 … #define RT5677_PWR_SR3_BIT … #define RT5677_PWR_SR2 … #define RT5677_PWR_SR2_BIT … #define RT5677_PWR_SR1 … #define RT5677_PWR_SR1_BIT … #define RT5677_PWR_SR0 … #define RT5677_PWR_SR0_BIT … #define RT5677_PWR_MLT … #define RT5677_PWR_MLT_BIT … #define RT5677_PWR_DSP … #define RT5677_PWR_DSP_BIT … #define RT5677_PWR_DSP_CPU … #define RT5677_PWR_DSP_CPU_BIT … /* Power Status for DSP (0x66) */ #define RT5677_PWR_SR7_RDY … #define RT5677_PWR_SR7_RDY_BIT … #define RT5677_PWR_SR6_RDY … #define RT5677_PWR_SR6_RDY_BIT … #define RT5677_PWR_SR5_RDY … #define RT5677_PWR_SR5_RDY_BIT … #define RT5677_PWR_SR4_RDY … #define RT5677_PWR_SR4_RDY_BIT … #define RT5677_PWR_SR3_RDY … #define RT5677_PWR_SR3_RDY_BIT … #define RT5677_PWR_SR2_RDY … #define RT5677_PWR_SR2_RDY_BIT … #define RT5677_PWR_SR1_RDY … #define RT5677_PWR_SR1_RDY_BIT … #define RT5677_PWR_SR0_RDY … #define RT5677_PWR_SR0_RDY_BIT … #define RT5677_PWR_MLT_RDY … #define RT5677_PWR_MLT_RDY_BIT … #define RT5677_PWR_DSP_RDY … #define RT5677_PWR_DSP_RDY_BIT … /* Power Management for DSP (0x67) */ #define RT5677_PWR_SLIM_ISO … #define RT5677_PWR_SLIM_ISO_BIT … #define RT5677_PWR_CORE_ISO … #define RT5677_PWR_CORE_ISO_BIT … #define RT5677_PWR_DSP_ISO … #define RT5677_PWR_DSP_ISO_BIT … #define RT5677_PWR_SR7_ISO … #define RT5677_PWR_SR7_ISO_BIT … #define RT5677_PWR_SR6_ISO … #define RT5677_PWR_SR6_ISO_BIT … #define RT5677_PWR_SR5_ISO … #define RT5677_PWR_SR5_ISO_BIT … #define RT5677_PWR_SR4_ISO … #define RT5677_PWR_SR4_ISO_BIT … #define RT5677_PWR_SR3_ISO … #define RT5677_PWR_SR3_ISO_BIT … #define RT5677_PWR_SR2_ISO … #define RT5677_PWR_SR2_ISO_BIT … #define RT5677_PWR_SR1_ISO … #define RT5677_PWR_SR1_ISO_BIT … #define RT5677_PWR_SR0_ISO … #define RT5677_PWR_SR0_ISO_BIT … #define RT5677_PWR_MLT_ISO … #define RT5677_PWR_MLT_ISO_BIT … /* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */ #define RT5677_I2S_MS_MASK … #define RT5677_I2S_MS_SFT … #define RT5677_I2S_MS_M … #define RT5677_I2S_MS_S … #define RT5677_I2S_O_CP_MASK … #define RT5677_I2S_O_CP_SFT … #define RT5677_I2S_O_CP_OFF … #define RT5677_I2S_O_CP_U_LAW … #define RT5677_I2S_O_CP_A_LAW … #define RT5677_I2S_I_CP_MASK … #define RT5677_I2S_I_CP_SFT … #define RT5677_I2S_I_CP_OFF … #define RT5677_I2S_I_CP_U_LAW … #define RT5677_I2S_I_CP_A_LAW … #define RT5677_I2S_BP_MASK … #define RT5677_I2S_BP_SFT … #define RT5677_I2S_BP_NOR … #define RT5677_I2S_BP_INV … #define RT5677_I2S_DL_MASK … #define RT5677_I2S_DL_SFT … #define RT5677_I2S_DL_16 … #define RT5677_I2S_DL_20 … #define RT5677_I2S_DL_24 … #define RT5677_I2S_DL_8 … #define RT5677_I2S_DF_MASK … #define RT5677_I2S_DF_SFT … #define RT5677_I2S_DF_I2S … #define RT5677_I2S_DF_LEFT … #define RT5677_I2S_DF_PCM_A … #define RT5677_I2S_DF_PCM_B … /* Clock Tree Control 1 (0x73) */ #define RT5677_I2S_PD1_MASK … #define RT5677_I2S_PD1_SFT … #define RT5677_I2S_PD1_1 … #define RT5677_I2S_PD1_2 … #define RT5677_I2S_PD1_3 … #define RT5677_I2S_PD1_4 … #define RT5677_I2S_PD1_6 … #define RT5677_I2S_PD1_8 … #define RT5677_I2S_PD1_12 … #define RT5677_I2S_PD1_16 … #define RT5677_I2S_BCLK_MS2_MASK … #define RT5677_I2S_BCLK_MS2_SFT … #define RT5677_I2S_BCLK_MS2_32 … #define RT5677_I2S_BCLK_MS2_64 … #define RT5677_I2S_PD2_MASK … #define RT5677_I2S_PD2_SFT … #define RT5677_I2S_PD2_1 … #define RT5677_I2S_PD2_2 … #define RT5677_I2S_PD2_3 … #define RT5677_I2S_PD2_4 … #define RT5677_I2S_PD2_6 … #define RT5677_I2S_PD2_8 … #define RT5677_I2S_PD2_12 … #define RT5677_I2S_PD2_16 … #define RT5677_I2S_BCLK_MS3_MASK … #define RT5677_I2S_BCLK_MS3_SFT … #define RT5677_I2S_BCLK_MS3_32 … #define RT5677_I2S_BCLK_MS3_64 … #define RT5677_I2S_PD3_MASK … #define RT5677_I2S_PD3_SFT … #define RT5677_I2S_PD3_1 … #define RT5677_I2S_PD3_2 … #define RT5677_I2S_PD3_3 … #define RT5677_I2S_PD3_4 … #define RT5677_I2S_PD3_6 … #define RT5677_I2S_PD3_8 … #define RT5677_I2S_PD3_12 … #define RT5677_I2S_PD3_16 … #define RT5677_I2S_BCLK_MS4_MASK … #define RT5677_I2S_BCLK_MS4_SFT … #define RT5677_I2S_BCLK_MS4_32 … #define RT5677_I2S_BCLK_MS4_64 … #define RT5677_I2S_PD4_MASK … #define RT5677_I2S_PD4_SFT … #define RT5677_I2S_PD4_1 … #define RT5677_I2S_PD4_2 … #define RT5677_I2S_PD4_3 … #define RT5677_I2S_PD4_4 … #define RT5677_I2S_PD4_6 … #define RT5677_I2S_PD4_8 … #define RT5677_I2S_PD4_12 … #define RT5677_I2S_PD4_16 … /* Clock Tree Control 2 (0x74) */ #define RT5677_I2S_PD5_MASK … #define RT5677_I2S_PD5_SFT … #define RT5677_I2S_PD5_1 … #define RT5677_I2S_PD5_2 … #define RT5677_I2S_PD5_3 … #define RT5677_I2S_PD5_4 … #define RT5677_I2S_PD5_6 … #define RT5677_I2S_PD5_8 … #define RT5677_I2S_PD5_12 … #define RT5677_I2S_PD5_16 … #define RT5677_I2S_PD6_MASK … #define RT5677_I2S_PD6_SFT … #define RT5677_I2S_PD6_1 … #define RT5677_I2S_PD6_2 … #define RT5677_I2S_PD6_3 … #define RT5677_I2S_PD6_4 … #define RT5677_I2S_PD6_6 … #define RT5677_I2S_PD6_8 … #define RT5677_I2S_PD6_12 … #define RT5677_I2S_PD6_16 … #define RT5677_I2S_PD7_MASK … #define RT5677_I2S_PD7_SFT … #define RT5677_I2S_PD7_1 … #define RT5677_I2S_PD7_2 … #define RT5677_I2S_PD7_3 … #define RT5677_I2S_PD7_4 … #define RT5677_I2S_PD7_6 … #define RT5677_I2S_PD7_8 … #define RT5677_I2S_PD7_12 … #define RT5677_I2S_PD7_16 … #define RT5677_I2S_PD8_MASK … #define RT5677_I2S_PD8_SFT … #define RT5677_I2S_PD8_1 … #define RT5677_I2S_PD8_2 … #define RT5677_I2S_PD8_3 … #define RT5677_I2S_PD8_4 … #define RT5677_I2S_PD8_6 … #define RT5677_I2S_PD8_8 … #define RT5677_I2S_PD8_12 … #define RT5677_I2S_PD8_16 … /* Clock Tree Control 3 (0x75) */ #define RT5677_DSP_ASRC_O_MASK … #define RT5677_DSP_ASRC_O_SFT … #define RT5677_DSP_ASRC_O_1_0 … #define RT5677_DSP_ASRC_O_1_5 … #define RT5677_DSP_ASRC_O_2_0 … #define RT5677_DSP_ASRC_O_3_0 … #define RT5677_DSP_ASRC_I_MASK … #define RT5677_DSP_ASRC_I_SFT … #define RT5677_DSP_ASRC_I_1_0 … #define RT5677_DSP_ASRC_I_1_5 … #define RT5677_DSP_ASRC_I_2_0 … #define RT5677_DSP_ASRC_I_3_0 … #define RT5677_DSP_BUS_PD_MASK … #define RT5677_DSP_BUS_PD_SFT … #define RT5677_DSP_BUS_PD_1 … #define RT5677_DSP_BUS_PD_2 … #define RT5677_DSP_BUS_PD_3 … #define RT5677_DSP_BUS_PD_4 … #define RT5677_DSP_BUS_PD_6 … #define RT5677_DSP_BUS_PD_8 … #define RT5677_DSP_BUS_PD_12 … #define RT5677_DSP_BUS_PD_16 … #define RT5677_PLL_INP_MAX … #define RT5677_PLL_INP_MIN … /* PLL M/N/K Code Control 1 (0x7a 0x7c) */ #define RT5677_PLL_N_MAX … #define RT5677_PLL_N_MASK … #define RT5677_PLL_N_SFT … #define RT5677_PLL_K_BP … #define RT5677_PLL_K_BP_SFT … #define RT5677_PLL_K_MAX … #define RT5677_PLL_K_MASK … #define RT5677_PLL_K_SFT … /* PLL M/N/K Code Control 2 (0x7b 0x7d) */ #define RT5677_PLL_M_MAX … #define RT5677_PLL_M_MASK … #define RT5677_PLL_M_SFT … #define RT5677_PLL_M_BP … #define RT5677_PLL_M_BP_SFT … #define RT5677_PLL_UPDATE_PLL1 … #define RT5677_PLL_UPDATE_PLL1_SFT … /* Global Clock Control 1 (0x80) */ #define RT5677_SCLK_SRC_MASK … #define RT5677_SCLK_SRC_SFT … #define RT5677_SCLK_SRC_MCLK … #define RT5677_SCLK_SRC_PLL1 … #define RT5677_SCLK_SRC_RCCLK … #define RT5677_SCLK_SRC_SLIM … #define RT5677_PLL1_SRC_MASK … #define RT5677_PLL1_SRC_SFT … #define RT5677_PLL1_SRC_MCLK … #define RT5677_PLL1_SRC_BCLK1 … #define RT5677_PLL1_SRC_BCLK2 … #define RT5677_PLL1_SRC_BCLK3 … #define RT5677_PLL1_SRC_BCLK4 … #define RT5677_PLL1_SRC_RCCLK … #define RT5677_PLL1_SRC_SLIM … #define RT5677_MCLK_SRC_MASK … #define RT5677_MCLK_SRC_SFT … #define RT5677_MCLK1_SRC … #define RT5677_MCLK2_SRC … #define RT5677_PLL1_PD_MASK … #define RT5677_PLL1_PD_SFT … #define RT5677_PLL1_PD_1 … #define RT5677_PLL1_PD_2 … #define RT5677_DAC_OSR_MASK … #define RT5677_DAC_OSR_SFT … #define RT5677_DAC_OSR_128 … #define RT5677_DAC_OSR_64 … #define RT5677_DAC_OSR_32 … #define RT5677_ADC_OSR_MASK … #define RT5677_ADC_OSR_SFT … #define RT5677_ADC_OSR_128 … #define RT5677_ADC_OSR_64 … #define RT5677_ADC_OSR_32 … /* Global Clock Control 2 (0x81) */ #define RT5677_PLL2_PR_SRC_MASK … #define RT5677_PLL2_PR_SRC_SFT … #define RT5677_PLL2_PR_SRC_MCLK1 … #define RT5677_PLL2_PR_SRC_MCLK2 … #define RT5677_PLL2_SRC_MASK … #define RT5677_PLL2_SRC_SFT … #define RT5677_PLL2_SRC_MCLK … #define RT5677_PLL2_SRC_BCLK1 … #define RT5677_PLL2_SRC_BCLK2 … #define RT5677_PLL2_SRC_BCLK3 … #define RT5677_PLL2_SRC_BCLK4 … #define RT5677_PLL2_SRC_RCCLK … #define RT5677_PLL2_SRC_SLIM … #define RT5677_DSP_ASRC_O_SRC … #define RT5677_DSP_ASRC_O_SRC_SFT … #define RT5677_DSP_ASRC_O_MCLK … #define RT5677_DSP_ASRC_O_PLL1 … #define RT5677_DSP_ASRC_O_SLIM … #define RT5677_DSP_ASRC_O_RCCLK … #define RT5677_DSP_ASRC_I_SRC … #define RT5677_DSP_ASRC_I_SRC_SFT … #define RT5677_DSP_ASRC_I_MCLK … #define RT5677_DSP_ASRC_I_PLL1 … #define RT5677_DSP_ASRC_I_SLIM … #define RT5677_DSP_ASRC_I_RCCLK … #define RT5677_DSP_CLK_SRC_MASK … #define RT5677_DSP_CLK_SRC_SFT … #define RT5677_DSP_CLK_SRC_PLL2 … #define RT5677_DSP_CLK_SRC_BYPASS … /* ASRC Control 3 (0x85) */ #define RT5677_DA_STO_CLK_SEL_MASK … #define RT5677_DA_STO_CLK_SEL_SFT … #define RT5677_DA_MONO2L_CLK_SEL_MASK … #define RT5677_DA_MONO2L_CLK_SEL_SFT … #define RT5677_DA_MONO2R_CLK_SEL_MASK … #define RT5677_DA_MONO2R_CLK_SEL_SFT … /* ASRC Control 4 (0x86) */ #define RT5677_DA_MONO3L_CLK_SEL_MASK … #define RT5677_DA_MONO3L_CLK_SEL_SFT … #define RT5677_DA_MONO3R_CLK_SEL_MASK … #define RT5677_DA_MONO3R_CLK_SEL_SFT … #define RT5677_DA_MONO4L_CLK_SEL_MASK … #define RT5677_DA_MONO4L_CLK_SEL_SFT … #define RT5677_DA_MONO4R_CLK_SEL_MASK … #define RT5677_DA_MONO4R_CLK_SEL_SFT … /* ASRC Control 5 (0x87) */ #define RT5677_AD_STO1_CLK_SEL_MASK … #define RT5677_AD_STO1_CLK_SEL_SFT … #define RT5677_AD_STO2_CLK_SEL_MASK … #define RT5677_AD_STO2_CLK_SEL_SFT … #define RT5677_AD_STO3_CLK_SEL_MASK … #define RT5677_AD_STO3_CLK_SEL_SFT … #define RT5677_AD_STO4_CLK_SEL_MASK … #define RT5677_AD_STO4_CLK_SEL_SFT … /* ASRC Control 6 (0x88) */ #define RT5677_AD_MONOL_CLK_SEL_MASK … #define RT5677_AD_MONOL_CLK_SEL_SFT … #define RT5677_AD_MONOR_CLK_SEL_MASK … #define RT5677_AD_MONOR_CLK_SEL_SFT … /* ASRC Control 7 (0x89) */ #define RT5677_DSP_OB_0_3_CLK_SEL_MASK … #define RT5677_DSP_OB_0_3_CLK_SEL_SFT … #define RT5677_DSP_OB_4_7_CLK_SEL_MASK … #define RT5677_DSP_OB_4_7_CLK_SEL_SFT … /* ASRC Control 8 (0x8a) */ #define RT5677_I2S1_CLK_SEL_MASK … #define RT5677_I2S1_CLK_SEL_SFT … #define RT5677_I2S2_CLK_SEL_MASK … #define RT5677_I2S2_CLK_SEL_SFT … #define RT5677_I2S3_CLK_SEL_MASK … #define RT5677_I2S3_CLK_SEL_SFT … #define RT5677_I2S4_CLK_SEL_MASK … #define RT5677_I2S4_CLK_SEL_SFT … /* VAD Function Control 1 (0x9c) */ #define RT5677_VAD_MIN_DUR_MASK … #define RT5677_VAD_MIN_DUR_SFT … #define RT5677_VAD_ADPCM_BYPASS … #define RT5677_VAD_ADPCM_BYPASS_BIT … #define RT5677_VAD_FG2ENC … #define RT5677_VAD_FG2ENC_BIT … #define RT5677_VAD_BUF_OW … #define RT5677_VAD_BUF_OW_BIT … #define RT5677_VAD_CLR_FLAG … #define RT5677_VAD_CLR_FLAG_BIT … #define RT5677_VAD_BUF_POP … #define RT5677_VAD_BUF_POP_BIT … #define RT5677_VAD_BUF_PUSH … #define RT5677_VAD_BUF_PUSH_BIT … #define RT5677_VAD_DET_ENABLE … #define RT5677_VAD_DET_ENABLE_BIT … #define RT5677_VAD_FUNC_ENABLE … #define RT5677_VAD_FUNC_ENABLE_BIT … #define RT5677_VAD_FUNC_RESET … #define RT5677_VAD_FUNC_RESET_BIT … /* VAD Function Control 4 (0x9f) */ #define RT5677_VAD_OUT_SRC_RATE_MASK … #define RT5677_VAD_OUT_SRC_RATE_SFT … #define RT5677_VAD_OUT_SRC_MASK … #define RT5677_VAD_OUT_SRC_SFT … #define RT5677_VAD_SRC_MASK … #define RT5677_VAD_SRC_SFT … #define RT5677_VAD_LV_DIFF_MASK … #define RT5677_VAD_LV_DIFF_SFT … /* DSP InBound Control (0xa3) */ #define RT5677_IB01_SRC_MASK … #define RT5677_IB01_SRC_SFT … #define RT5677_IB23_SRC_MASK … #define RT5677_IB23_SRC_SFT … #define RT5677_IB45_SRC_MASK … #define RT5677_IB45_SRC_SFT … #define RT5677_IB6_SRC_MASK … #define RT5677_IB6_SRC_SFT … /* DSP InBound Control (0xa4) */ #define RT5677_IB7_SRC_MASK … #define RT5677_IB7_SRC_SFT … #define RT5677_IB8_SRC_MASK … #define RT5677_IB8_SRC_SFT … #define RT5677_IB9_SRC_MASK … #define RT5677_IB9_SRC_SFT … /* DSP In/OutBound Control (0xa5) */ #define RT5677_SEL_SRC_OB23 … #define RT5677_SEL_SRC_OB23_SFT … #define RT5677_SEL_SRC_OB01 … #define RT5677_SEL_SRC_OB01_SFT … #define RT5677_SEL_SRC_IB45 … #define RT5677_SEL_SRC_IB45_SFT … #define RT5677_SEL_SRC_IB23 … #define RT5677_SEL_SRC_IB23_SFT … #define RT5677_SEL_SRC_IB01 … #define RT5677_SEL_SRC_IB01_SFT … /* Jack Detect Control 1 (0xb5) */ #define RT5677_SEL_GPIO_JD1_MASK … #define RT5677_SEL_GPIO_JD1_SFT … #define RT5677_SEL_GPIO_JD2_MASK … #define RT5677_SEL_GPIO_JD2_SFT … #define RT5677_SEL_GPIO_JD3_MASK … #define RT5677_SEL_GPIO_JD3_SFT … /* IRQ Control 1 (0xbd) */ #define RT5677_STA_GPIO_JD1 … #define RT5677_STA_GPIO_JD1_SFT … #define RT5677_EN_IRQ_GPIO_JD1 … #define RT5677_EN_IRQ_GPIO_JD1_SFT … #define RT5677_EN_GPIO_JD1_STICKY … #define RT5677_EN_GPIO_JD1_STICKY_SFT … #define RT5677_INV_GPIO_JD1 … #define RT5677_INV_GPIO_JD1_SFT … #define RT5677_STA_GPIO_JD2 … #define RT5677_STA_GPIO_JD2_SFT … #define RT5677_EN_IRQ_GPIO_JD2 … #define RT5677_EN_IRQ_GPIO_JD2_SFT … #define RT5677_EN_GPIO_JD2_STICKY … #define RT5677_EN_GPIO_JD2_STICKY_SFT … #define RT5677_INV_GPIO_JD2 … #define RT5677_INV_GPIO_JD2_SFT … #define RT5677_STA_MICBIAS1_OVCD … #define RT5677_STA_MICBIAS1_OVCD_SFT … #define RT5677_EN_IRQ_MICBIAS1_OVCD … #define RT5677_EN_IRQ_MICBIAS1_OVCD_SFT … #define RT5677_EN_MICBIAS1_OVCD_STICKY … #define RT5677_EN_MICBIAS1_OVCD_STICKY_SFT … #define RT5677_INV_MICBIAS1_OVCD … #define RT5677_INV_MICBIAS1_OVCD_SFT … #define RT5677_STA_GPIO_JD3 … #define RT5677_STA_GPIO_JD3_SFT … #define RT5677_EN_IRQ_GPIO_JD3 … #define RT5677_EN_IRQ_GPIO_JD3_SFT … #define RT5677_EN_GPIO_JD3_STICKY … #define RT5677_EN_GPIO_JD3_STICKY_SFT … #define RT5677_INV_GPIO_JD3 … #define RT5677_INV_GPIO_JD3_SFT … /* GPIO status (0xbf) */ #define RT5677_GPIO6_STATUS_MASK … #define RT5677_GPIO6_STATUS_SFT … #define RT5677_GPIO5_STATUS_MASK … #define RT5677_GPIO5_STATUS_SFT … #define RT5677_GPIO4_STATUS_MASK … #define RT5677_GPIO4_STATUS_SFT … #define RT5677_GPIO3_STATUS_MASK … #define RT5677_GPIO3_STATUS_SFT … #define RT5677_GPIO2_STATUS_MASK … #define RT5677_GPIO2_STATUS_SFT … #define RT5677_GPIO1_STATUS_MASK … #define RT5677_GPIO1_STATUS_SFT … /* GPIO Control 1 (0xc0) */ #define RT5677_GPIO1_PIN_MASK … #define RT5677_GPIO1_PIN_SFT … #define RT5677_GPIO1_PIN_GPIO1 … #define RT5677_GPIO1_PIN_IRQ … #define RT5677_IPTV_MODE_MASK … #define RT5677_IPTV_MODE_SFT … #define RT5677_IPTV_MODE_GPIO … #define RT5677_IPTV_MODE_IPTV … #define RT5677_FUNC_MODE_MASK … #define RT5677_FUNC_MODE_SFT … #define RT5677_FUNC_MODE_DMIC_GPIO … #define RT5677_FUNC_MODE_JTAG … /* GPIO Control 2 (0xc1) & 3 (0xc2) common bits */ #define RT5677_GPIOx_DIR_MASK … #define RT5677_GPIOx_DIR_SFT … #define RT5677_GPIOx_DIR_IN … #define RT5677_GPIOx_DIR_OUT … #define RT5677_GPIOx_OUT_MASK … #define RT5677_GPIOx_OUT_SFT … #define RT5677_GPIOx_OUT_LO … #define RT5677_GPIOx_OUT_HI … #define RT5677_GPIOx_P_MASK … #define RT5677_GPIOx_P_SFT … #define RT5677_GPIOx_P_NOR … #define RT5677_GPIOx_P_INV … /* General Control (0xfa) */ #define RT5677_IRQ_DEBOUNCE_SEL_MASK … #define RT5677_IRQ_DEBOUNCE_SEL_MCLK … #define RT5677_IRQ_DEBOUNCE_SEL_RC … #define RT5677_IRQ_DEBOUNCE_SEL_SLIM … /* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */ #define RT5677_DSP_IB_01_H … #define RT5677_DSP_IB_01_H_SFT … #define RT5677_DSP_IB_23_H … #define RT5677_DSP_IB_23_H_SFT … #define RT5677_DSP_IB_45_H … #define RT5677_DSP_IB_45_H_SFT … #define RT5677_DSP_IB_6_H … #define RT5677_DSP_IB_6_H_SFT … #define RT5677_DSP_IB_7_H … #define RT5677_DSP_IB_7_H_SFT … #define RT5677_DSP_IB_8_H … #define RT5677_DSP_IB_8_H_SFT … #define RT5677_DSP_IB_9_H … #define RT5677_DSP_IB_9_H_SFT … #define RT5677_DSP_IB_01_L … #define RT5677_DSP_IB_01_L_SFT … #define RT5677_DSP_IB_23_L … #define RT5677_DSP_IB_23_L_SFT … #define RT5677_DSP_IB_45_L … #define RT5677_DSP_IB_45_L_SFT … #define RT5677_DSP_IB_6_L … #define RT5677_DSP_IB_6_L_SFT … #define RT5677_DSP_IB_7_L … #define RT5677_DSP_IB_7_L_SFT … #define RT5677_DSP_IB_8_L … #define RT5677_DSP_IB_8_L_SFT … #define RT5677_DSP_IB_9_L … #define RT5677_DSP_IB_9_L_SFT … /* General Control2 (0xfc)*/ #define RT5677_GPIO5_FUNC_MASK … #define RT5677_GPIO5_FUNC_GPIO … #define RT5677_GPIO5_FUNC_DMIC … #define RT5677_FIRMWARE1 … #define RT5677_FIRMWARE2 … #define RT5677_DRV_NAME … /* System Clock Source */ enum { … }; /* PLL1 Source */ enum { … }; enum { … }; enum { … }; enum { … }; enum rt5677_type { … }; /* ASRC clock source selection */ enum { … }; /* filter mask */ enum { … }; enum rt5677_dmic2_clk { … }; struct rt5677_platform_data { … }; struct rt5677_priv { … }; int rt5677_sel_asrc_clk_src(struct snd_soc_component *component, unsigned int filter_mask, unsigned int clk_src); #endif /* __RT5677_H__ */
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