/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt5682.h -- RT5682/RT5658 ALSA SoC audio driver * * Copyright 2018 Realtek Microelectronics * Author: Bard Liao <[email protected]> */ #ifndef __RT5682_H__ #define __RT5682_H__ #include <sound/rt5682.h> #include <linux/regulator/consumer.h> #include <linux/gpio/consumer.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/soundwire/sdw.h> #include <linux/soundwire/sdw_type.h> #define DEVICE_ID … /* Info */ #define RT5682_RESET … #define RT5682_VERSION_ID … #define RT5682_VENDOR_ID … #define RT5682_DEVICE_ID … /* I/O - Output */ #define RT5682_HP_CTRL_1 … #define RT5682_HP_CTRL_2 … #define RT5682_HPL_GAIN … #define RT5682_HPR_GAIN … #define RT5682_I2C_CTRL … /* I/O - Input */ #define RT5682_CBJ_BST_CTRL … #define RT5682_CBJ_CTRL_1 … #define RT5682_CBJ_CTRL_2 … #define RT5682_CBJ_CTRL_3 … #define RT5682_CBJ_CTRL_4 … #define RT5682_CBJ_CTRL_5 … #define RT5682_CBJ_CTRL_6 … #define RT5682_CBJ_CTRL_7 … /* I/O - ADC/DAC/DMIC */ #define RT5682_DAC1_DIG_VOL … #define RT5682_STO1_ADC_DIG_VOL … #define RT5682_STO1_ADC_BOOST … #define RT5682_HP_IMP_GAIN_1 … #define RT5682_HP_IMP_GAIN_2 … /* Mixer - D-D */ #define RT5682_SIDETONE_CTRL … #define RT5682_STO1_ADC_MIXER … #define RT5682_AD_DA_MIXER … #define RT5682_STO1_DAC_MIXER … #define RT5682_A_DAC1_MUX … #define RT5682_DIG_INF2_DATA … /* Mixer - ADC */ #define RT5682_REC_MIXER … #define RT5682_CAL_REC … #define RT5682_ALC_BACK_GAIN … /* Power */ #define RT5682_PWR_DIG_1 … #define RT5682_PWR_DIG_2 … #define RT5682_PWR_ANLG_1 … #define RT5682_PWR_ANLG_2 … #define RT5682_PWR_ANLG_3 … #define RT5682_PWR_MIXER … #define RT5682_PWR_VOL … /* Clock Detect */ #define RT5682_CLK_DET … /* Filter Auto Reset */ #define RT5682_RESET_LPF_CTRL … #define RT5682_RESET_HPF_CTRL … /* DMIC */ #define RT5682_DMIC_CTRL_1 … /* Format - ADC/DAC */ #define RT5682_I2S1_SDP … #define RT5682_I2S2_SDP … #define RT5682_ADDA_CLK_1 … #define RT5682_ADDA_CLK_2 … #define RT5682_I2S1_F_DIV_CTRL_1 … #define RT5682_I2S1_F_DIV_CTRL_2 … /* Format - TDM Control */ #define RT5682_TDM_CTRL … #define RT5682_TDM_ADDA_CTRL_1 … #define RT5682_TDM_ADDA_CTRL_2 … #define RT5682_DATA_SEL_CTRL_1 … #define RT5682_TDM_TCON_CTRL … /* Function - Analog */ #define RT5682_GLB_CLK … #define RT5682_PLL_CTRL_1 … #define RT5682_PLL_CTRL_2 … #define RT5682_PLL_TRACK_1 … #define RT5682_PLL_TRACK_2 … #define RT5682_PLL_TRACK_3 … #define RT5682_PLL_TRACK_4 … #define RT5682_PLL_TRACK_5 … #define RT5682_PLL_TRACK_6 … #define RT5682_PLL_TRACK_11 … #define RT5682_SDW_REF_CLK … #define RT5682_DEPOP_1 … #define RT5682_DEPOP_2 … #define RT5682_HP_CHARGE_PUMP_1 … #define RT5682_HP_CHARGE_PUMP_2 … #define RT5682_MICBIAS_1 … #define RT5682_MICBIAS_2 … #define RT5682_PLL_TRACK_12 … #define RT5682_PLL_TRACK_14 … #define RT5682_PLL2_CTRL_1 … #define RT5682_PLL2_CTRL_2 … #define RT5682_PLL2_CTRL_3 … #define RT5682_PLL2_CTRL_4 … #define RT5682_RC_CLK_CTRL … #define RT5682_I2S_M_CLK_CTRL_1 … #define RT5682_I2S2_F_DIV_CTRL_1 … #define RT5682_I2S2_F_DIV_CTRL_2 … /* Function - Digital */ #define RT5682_EQ_CTRL_1 … #define RT5682_EQ_CTRL_2 … #define RT5682_IRQ_CTRL_1 … #define RT5682_IRQ_CTRL_2 … #define RT5682_IRQ_CTRL_3 … #define RT5682_IRQ_CTRL_4 … #define RT5682_INT_ST_1 … #define RT5682_GPIO_CTRL_1 … #define RT5682_GPIO_CTRL_2 … #define RT5682_GPIO_CTRL_3 … #define RT5682_HP_AMP_DET_CTRL_1 … #define RT5682_HP_AMP_DET_CTRL_2 … #define RT5682_MID_HP_AMP_DET … #define RT5682_LOW_HP_AMP_DET … #define RT5682_DELAY_BUF_CTRL … #define RT5682_SV_ZCD_1 … #define RT5682_SV_ZCD_2 … #define RT5682_IL_CMD_1 … #define RT5682_IL_CMD_2 … #define RT5682_IL_CMD_3 … #define RT5682_IL_CMD_4 … #define RT5682_IL_CMD_5 … #define RT5682_IL_CMD_6 … #define RT5682_4BTN_IL_CMD_1 … #define RT5682_4BTN_IL_CMD_2 … #define RT5682_4BTN_IL_CMD_3 … #define RT5682_4BTN_IL_CMD_4 … #define RT5682_4BTN_IL_CMD_5 … #define RT5682_4BTN_IL_CMD_6 … #define RT5682_4BTN_IL_CMD_7 … #define RT5682_ADC_STO1_HP_CTRL_1 … #define RT5682_ADC_STO1_HP_CTRL_2 … #define RT5682_AJD1_CTRL … #define RT5682_JD1_THD … #define RT5682_JD2_THD … #define RT5682_JD_CTRL_1 … /* General Control */ #define RT5682_DUMMY_1 … #define RT5682_DUMMY_2 … #define RT5682_DUMMY_3 … #define RT5682_DAC_ADC_DIG_VOL1 … #define RT5682_BIAS_CUR_CTRL_2 … #define RT5682_BIAS_CUR_CTRL_3 … #define RT5682_BIAS_CUR_CTRL_4 … #define RT5682_BIAS_CUR_CTRL_5 … #define RT5682_BIAS_CUR_CTRL_6 … #define RT5682_BIAS_CUR_CTRL_7 … #define RT5682_BIAS_CUR_CTRL_8 … #define RT5682_BIAS_CUR_CTRL_9 … #define RT5682_BIAS_CUR_CTRL_10 … #define RT5682_VREF_REC_OP_FB_CAP_CTRL … #define RT5682_CHARGE_PUMP_1 … #define RT5682_DIG_IN_CTRL_1 … #define RT5682_PAD_DRIVING_CTRL … #define RT5682_SOFT_RAMP_DEPOP … #define RT5682_CHOP_DAC … #define RT5682_CHOP_ADC … #define RT5682_CALIB_ADC_CTRL … #define RT5682_VOL_TEST … #define RT5682_SPKVDD_DET_STA … #define RT5682_TEST_MODE_CTRL_1 … #define RT5682_TEST_MODE_CTRL_2 … #define RT5682_TEST_MODE_CTRL_3 … #define RT5682_TEST_MODE_CTRL_4 … #define RT5682_TEST_MODE_CTRL_5 … #define RT5682_PLL1_INTERNAL … #define RT5682_PLL2_INTERNAL … #define RT5682_STO_NG2_CTRL_1 … #define RT5682_STO_NG2_CTRL_2 … #define RT5682_STO_NG2_CTRL_3 … #define RT5682_STO_NG2_CTRL_4 … #define RT5682_STO_NG2_CTRL_5 … #define RT5682_STO_NG2_CTRL_6 … #define RT5682_STO_NG2_CTRL_7 … #define RT5682_STO_NG2_CTRL_8 … #define RT5682_STO_NG2_CTRL_9 … #define RT5682_STO_NG2_CTRL_10 … #define RT5682_STO1_DAC_SIL_DET … #define RT5682_SIL_PSV_CTRL1 … #define RT5682_SIL_PSV_CTRL2 … #define RT5682_SIL_PSV_CTRL3 … #define RT5682_SIL_PSV_CTRL4 … #define RT5682_SIL_PSV_CTRL5 … #define RT5682_HP_IMP_SENS_CTRL_01 … #define RT5682_HP_IMP_SENS_CTRL_02 … #define RT5682_HP_IMP_SENS_CTRL_03 … #define RT5682_HP_IMP_SENS_CTRL_04 … #define RT5682_HP_IMP_SENS_CTRL_05 … #define RT5682_HP_IMP_SENS_CTRL_06 … #define RT5682_HP_IMP_SENS_CTRL_07 … #define RT5682_HP_IMP_SENS_CTRL_08 … #define RT5682_HP_IMP_SENS_CTRL_09 … #define RT5682_HP_IMP_SENS_CTRL_10 … #define RT5682_HP_IMP_SENS_CTRL_11 … #define RT5682_HP_IMP_SENS_CTRL_12 … #define RT5682_HP_IMP_SENS_CTRL_13 … #define RT5682_HP_IMP_SENS_CTRL_14 … #define RT5682_HP_IMP_SENS_CTRL_15 … #define RT5682_HP_IMP_SENS_CTRL_16 … #define RT5682_HP_IMP_SENS_CTRL_17 … #define RT5682_HP_IMP_SENS_CTRL_18 … #define RT5682_HP_IMP_SENS_CTRL_19 … #define RT5682_HP_IMP_SENS_CTRL_20 … #define RT5682_HP_IMP_SENS_CTRL_21 … #define RT5682_HP_IMP_SENS_CTRL_22 … #define RT5682_HP_IMP_SENS_CTRL_23 … #define RT5682_HP_IMP_SENS_CTRL_24 … #define RT5682_HP_IMP_SENS_CTRL_25 … #define RT5682_HP_IMP_SENS_CTRL_26 … #define RT5682_HP_IMP_SENS_CTRL_27 … #define RT5682_HP_IMP_SENS_CTRL_28 … #define RT5682_HP_IMP_SENS_CTRL_29 … #define RT5682_HP_IMP_SENS_CTRL_30 … #define RT5682_HP_IMP_SENS_CTRL_31 … #define RT5682_HP_IMP_SENS_CTRL_32 … #define RT5682_HP_IMP_SENS_CTRL_33 … #define RT5682_HP_IMP_SENS_CTRL_34 … #define RT5682_HP_IMP_SENS_CTRL_35 … #define RT5682_HP_IMP_SENS_CTRL_36 … #define RT5682_HP_IMP_SENS_CTRL_37 … #define RT5682_HP_IMP_SENS_CTRL_38 … #define RT5682_HP_IMP_SENS_CTRL_39 … #define RT5682_HP_IMP_SENS_CTRL_40 … #define RT5682_HP_IMP_SENS_CTRL_41 … #define RT5682_HP_IMP_SENS_CTRL_42 … #define RT5682_HP_IMP_SENS_CTRL_43 … #define RT5682_HP_LOGIC_CTRL_1 … #define RT5682_HP_LOGIC_CTRL_2 … #define RT5682_HP_LOGIC_CTRL_3 … #define RT5682_HP_CALIB_CTRL_1 … #define RT5682_HP_CALIB_CTRL_2 … #define RT5682_HP_CALIB_CTRL_3 … #define RT5682_HP_CALIB_CTRL_4 … #define RT5682_HP_CALIB_CTRL_5 … #define RT5682_HP_CALIB_CTRL_6 … #define RT5682_HP_CALIB_CTRL_7 … #define RT5682_HP_CALIB_CTRL_9 … #define RT5682_HP_CALIB_CTRL_10 … #define RT5682_HP_CALIB_CTRL_11 … #define RT5682_HP_CALIB_STA_1 … #define RT5682_HP_CALIB_STA_2 … #define RT5682_HP_CALIB_STA_3 … #define RT5682_HP_CALIB_STA_4 … #define RT5682_HP_CALIB_STA_5 … #define RT5682_HP_CALIB_STA_6 … #define RT5682_HP_CALIB_STA_7 … #define RT5682_HP_CALIB_STA_8 … #define RT5682_HP_CALIB_STA_9 … #define RT5682_HP_CALIB_STA_10 … #define RT5682_HP_CALIB_STA_11 … #define RT5682_SAR_IL_CMD_1 … #define RT5682_SAR_IL_CMD_2 … #define RT5682_SAR_IL_CMD_3 … #define RT5682_SAR_IL_CMD_4 … #define RT5682_SAR_IL_CMD_5 … #define RT5682_SAR_IL_CMD_6 … #define RT5682_SAR_IL_CMD_7 … #define RT5682_SAR_IL_CMD_8 … #define RT5682_SAR_IL_CMD_9 … #define RT5682_SAR_IL_CMD_10 … #define RT5682_SAR_IL_CMD_11 … #define RT5682_SAR_IL_CMD_12 … #define RT5682_SAR_IL_CMD_13 … #define RT5682_EFUSE_CTRL_1 … #define RT5682_EFUSE_CTRL_2 … #define RT5682_EFUSE_CTRL_3 … #define RT5682_EFUSE_CTRL_4 … #define RT5682_EFUSE_CTRL_5 … #define RT5682_EFUSE_CTRL_6 … #define RT5682_EFUSE_CTRL_7 … #define RT5682_EFUSE_CTRL_8 … #define RT5682_EFUSE_CTRL_9 … #define RT5682_EFUSE_CTRL_10 … #define RT5682_EFUSE_CTRL_11 … #define RT5682_JD_TOP_VC_VTRL … #define RT5682_DRC1_CTRL_0 … #define RT5682_DRC1_CTRL_1 … #define RT5682_DRC1_CTRL_2 … #define RT5682_DRC1_CTRL_3 … #define RT5682_DRC1_CTRL_4 … #define RT5682_DRC1_CTRL_5 … #define RT5682_DRC1_CTRL_6 … #define RT5682_DRC1_HARD_LMT_CTRL_1 … #define RT5682_DRC1_HARD_LMT_CTRL_2 … #define RT5682_DRC1_PRIV_1 … #define RT5682_DRC1_PRIV_2 … #define RT5682_DRC1_PRIV_3 … #define RT5682_DRC1_PRIV_4 … #define RT5682_DRC1_PRIV_5 … #define RT5682_DRC1_PRIV_6 … #define RT5682_DRC1_PRIV_7 … #define RT5682_DRC1_PRIV_8 … #define RT5682_EQ_AUTO_RCV_CTRL1 … #define RT5682_EQ_AUTO_RCV_CTRL2 … #define RT5682_EQ_AUTO_RCV_CTRL3 … #define RT5682_EQ_AUTO_RCV_CTRL4 … #define RT5682_EQ_AUTO_RCV_CTRL5 … #define RT5682_EQ_AUTO_RCV_CTRL6 … #define RT5682_EQ_AUTO_RCV_CTRL7 … #define RT5682_EQ_AUTO_RCV_CTRL8 … #define RT5682_EQ_AUTO_RCV_CTRL9 … #define RT5682_EQ_AUTO_RCV_CTRL10 … #define RT5682_EQ_AUTO_RCV_CTRL11 … #define RT5682_EQ_AUTO_RCV_CTRL12 … #define RT5682_EQ_AUTO_RCV_CTRL13 … #define RT5682_ADC_L_EQ_LPF1_A1 … #define RT5682_R_EQ_LPF1_A1 … #define RT5682_L_EQ_LPF1_H0 … #define RT5682_R_EQ_LPF1_H0 … #define RT5682_L_EQ_BPF1_A1 … #define RT5682_R_EQ_BPF1_A1 … #define RT5682_L_EQ_BPF1_A2 … #define RT5682_R_EQ_BPF1_A2 … #define RT5682_L_EQ_BPF1_H0 … #define RT5682_R_EQ_BPF1_H0 … #define RT5682_L_EQ_BPF2_A1 … #define RT5682_R_EQ_BPF2_A1 … #define RT5682_L_EQ_BPF2_A2 … #define RT5682_R_EQ_BPF2_A2 … #define RT5682_L_EQ_BPF2_H0 … #define RT5682_R_EQ_BPF2_H0 … #define RT5682_L_EQ_BPF3_A1 … #define RT5682_R_EQ_BPF3_A1 … #define RT5682_L_EQ_BPF3_A2 … #define RT5682_R_EQ_BPF3_A2 … #define RT5682_L_EQ_BPF3_H0 … #define RT5682_R_EQ_BPF3_H0 … #define RT5682_L_EQ_BPF4_A1 … #define RT5682_R_EQ_BPF4_A1 … #define RT5682_L_EQ_BPF4_A2 … #define RT5682_R_EQ_BPF4_A2 … #define RT5682_L_EQ_BPF4_H0 … #define RT5682_R_EQ_BPF4_H0 … #define RT5682_L_EQ_HPF1_A1 … #define RT5682_R_EQ_HPF1_A1 … #define RT5682_L_EQ_HPF1_H0 … #define RT5682_R_EQ_HPF1_H0 … #define RT5682_L_EQ_PRE_VOL … #define RT5682_R_EQ_PRE_VOL … #define RT5682_L_EQ_POST_VOL … #define RT5682_R_EQ_POST_VOL … #define RT5682_I2C_MODE … /* global definition */ #define RT5682_L_MUTE … #define RT5682_L_MUTE_SFT … #define RT5682_VOL_L_MUTE … #define RT5682_VOL_L_SFT … #define RT5682_R_MUTE … #define RT5682_R_MUTE_SFT … #define RT5682_VOL_R_MUTE … #define RT5682_VOL_R_SFT … #define RT5682_L_VOL_MASK … #define RT5682_L_VOL_SFT … #define RT5682_R_VOL_MASK … #define RT5682_R_VOL_SFT … /* Headphone Amp Control 2 (0x0003) */ #define RT5682_HP_C2_DAC_AMP_MUTE_SFT … #define RT5682_HP_C2_DAC_AMP_MUTE … #define RT5682_HP_C2_DAC_L_EN_SFT … #define RT5682_HP_C2_DAC_L_EN … #define RT5682_HP_C2_DAC_R_EN_SFT … #define RT5682_HP_C2_DAC_R_EN … /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ #define RT5682_G_HP … #define RT5682_G_HP_SFT … #define RT5682_G_STO_DA_DMIX … #define RT5682_G_STO_DA_SFT … /* CBJ Control (0x000b) */ #define RT5682_BST_CBJ_MASK … #define RT5682_BST_CBJ_SFT … /* Embeeded Jack and Type Detection Control 1 (0x0010) */ #define RT5682_EMB_JD_EN … #define RT5682_EMB_JD_EN_SFT … #define RT5682_EMB_JD_RST … #define RT5682_JD_MODE … #define RT5682_JD_MODE_SFT … #define RT5682_DET_TYPE … #define RT5682_DET_TYPE_SFT … #define RT5682_POLA_EXT_JD_MASK … #define RT5682_POLA_EXT_JD_LOW … #define RT5682_POLA_EXT_JD_HIGH … #define RT5682_EXT_JD_DIG … #define RT5682_POL_FAST_OFF_MASK … #define RT5682_POL_FAST_OFF_HIGH … #define RT5682_POL_FAST_OFF_LOW … #define RT5682_FAST_OFF_MASK … #define RT5682_FAST_OFF_EN … #define RT5682_FAST_OFF_DIS … #define RT5682_VREF_POW_MASK … #define RT5682_VREF_POW_FSM … #define RT5682_VREF_POW_REG … #define RT5682_MB1_PATH_MASK … #define RT5682_CTRL_MB1_REG … #define RT5682_CTRL_MB1_FSM … #define RT5682_MB2_PATH_MASK … #define RT5682_CTRL_MB2_REG … #define RT5682_CTRL_MB2_FSM … #define RT5682_TRIG_JD_MASK … #define RT5682_TRIG_JD_HIGH … #define RT5682_TRIG_JD_LOW … #define RT5682_MIC_CAP_MASK … #define RT5682_MIC_CAP_HS … #define RT5682_MIC_CAP_HP … #define RT5682_MIC_CAP_SRC_MASK … #define RT5682_MIC_CAP_SRC_REG … #define RT5682_MIC_CAP_SRC_ANA … /* Embeeded Jack and Type Detection Control 2 (0x0011) */ #define RT5682_EXT_JD_SRC … #define RT5682_EXT_JD_SRC_SFT … #define RT5682_EXT_JD_SRC_GPIO_JD1 … #define RT5682_EXT_JD_SRC_GPIO_JD2 … #define RT5682_EXT_JD_SRC_JDH … #define RT5682_EXT_JD_SRC_JDL … #define RT5682_EXT_JD_SRC_MANUAL … #define RT5682_JACK_TYPE_MASK … /* Combo Jack and Type Detection Control 3 (0x0012) */ #define RT5682_CBJ_IN_BUF_EN … /* Combo Jack and Type Detection Control 4 (0x0013) */ #define RT5682_SEL_SHT_MID_TON_MASK … #define RT5682_SEL_SHT_MID_TON_2 … #define RT5682_SEL_SHT_MID_TON_3 … #define RT5682_CBJ_JD_TEST_MASK … #define RT5682_CBJ_JD_TEST_NORM … #define RT5682_CBJ_JD_TEST_MODE … /* DAC1 Digital Volume (0x0019) */ #define RT5682_DAC_L1_VOL_MASK … #define RT5682_DAC_L1_VOL_SFT … #define RT5682_DAC_R1_VOL_MASK … #define RT5682_DAC_R1_VOL_SFT … /* ADC Digital Volume Control (0x001c) */ #define RT5682_ADC_L_VOL_MASK … #define RT5682_ADC_L_VOL_SFT … #define RT5682_ADC_R_VOL_MASK … #define RT5682_ADC_R_VOL_SFT … /* Stereo1 ADC Boost Gain Control (0x001f) */ #define RT5682_STO1_ADC_L_BST_MASK … #define RT5682_STO1_ADC_L_BST_SFT … #define RT5682_STO1_ADC_R_BST_MASK … #define RT5682_STO1_ADC_R_BST_SFT … /* Sidetone Control (0x0024) */ #define RT5682_ST_SRC_SEL … #define RT5682_ST_SRC_SFT … #define RT5682_ST_EN_MASK … #define RT5682_ST_DIS … #define RT5682_ST_EN … #define RT5682_ST_EN_SFT … /* Stereo1 ADC Mixer Control (0x0026) */ #define RT5682_M_STO1_ADC_L1 … #define RT5682_M_STO1_ADC_L1_SFT … #define RT5682_M_STO1_ADC_L2 … #define RT5682_M_STO1_ADC_L2_SFT … #define RT5682_STO1_ADC1L_SRC_MASK … #define RT5682_STO1_ADC1L_SRC_SFT … #define RT5682_STO1_ADC1_SRC_ADC … #define RT5682_STO1_ADC1_SRC_DACMIX … #define RT5682_STO1_ADC2L_SRC_MASK … #define RT5682_STO1_ADC2L_SRC_SFT … #define RT5682_STO1_ADCL_SRC_MASK … #define RT5682_STO1_ADCL_SRC_SFT … #define RT5682_STO1_DD_L_SRC_MASK … #define RT5682_STO1_DD_L_SRC_SFT … #define RT5682_STO1_DMIC_SRC_MASK … #define RT5682_STO1_DMIC_SRC_SFT … #define RT5682_STO1_DMIC_SRC_DMIC2 … #define RT5682_STO1_DMIC_SRC_DMIC1 … #define RT5682_M_STO1_ADC_R1 … #define RT5682_M_STO1_ADC_R1_SFT … #define RT5682_M_STO1_ADC_R2 … #define RT5682_M_STO1_ADC_R2_SFT … #define RT5682_STO1_ADC1R_SRC_MASK … #define RT5682_STO1_ADC1R_SRC_SFT … #define RT5682_STO1_ADC2R_SRC_MASK … #define RT5682_STO1_ADC2R_SRC_SFT … #define RT5682_STO1_ADCR_SRC_MASK … #define RT5682_STO1_ADCR_SRC_SFT … /* ADC Mixer to DAC Mixer Control (0x0029) */ #define RT5682_M_ADCMIX_L … #define RT5682_M_ADCMIX_L_SFT … #define RT5682_M_DAC1_L … #define RT5682_M_DAC1_L_SFT … #define RT5682_DAC1_R_SEL_MASK … #define RT5682_DAC1_R_SEL_SFT … #define RT5682_DAC1_L_SEL_MASK … #define RT5682_DAC1_L_SEL_SFT … #define RT5682_M_ADCMIX_R … #define RT5682_M_ADCMIX_R_SFT … #define RT5682_M_DAC1_R … #define RT5682_M_DAC1_R_SFT … /* Stereo1 DAC Mixer Control (0x002a) */ #define RT5682_M_DAC_L1_STO_L … #define RT5682_M_DAC_L1_STO_L_SFT … #define RT5682_G_DAC_L1_STO_L_MASK … #define RT5682_G_DAC_L1_STO_L_SFT … #define RT5682_M_DAC_R1_STO_L … #define RT5682_M_DAC_R1_STO_L_SFT … #define RT5682_G_DAC_R1_STO_L_MASK … #define RT5682_G_DAC_R1_STO_L_SFT … #define RT5682_M_DAC_L1_STO_R … #define RT5682_M_DAC_L1_STO_R_SFT … #define RT5682_G_DAC_L1_STO_R_MASK … #define RT5682_G_DAC_L1_STO_R_SFT … #define RT5682_M_DAC_R1_STO_R … #define RT5682_M_DAC_R1_STO_R_SFT … #define RT5682_G_DAC_R1_STO_R_MASK … #define RT5682_G_DAC_R1_STO_R_SFT … /* Analog DAC1 Input Source Control (0x002b) */ #define RT5682_M_ST_STO_L … #define RT5682_M_ST_STO_L_SFT … #define RT5682_M_ST_STO_R … #define RT5682_M_ST_STO_R_SFT … #define RT5682_DAC_L1_SRC_MASK … #define RT5682_A_DACL1_SFT … #define RT5682_DAC_R1_SRC_MASK … #define RT5682_A_DACR1_SFT … /* Digital Interface Data Control (0x0030) */ #define RT5682_IF2_ADC_SEL_MASK … #define RT5682_IF2_ADC_SEL_SFT … /* REC Left Mixer Control 2 (0x003c) */ #define RT5682_G_CBJ_RM1_L … #define RT5682_G_CBJ_RM1_L_SFT … #define RT5682_M_CBJ_RM1_L … #define RT5682_M_CBJ_RM1_L_SFT … /* Power Management for Digital 1 (0x0061) */ #define RT5682_PWR_I2S1 … #define RT5682_PWR_I2S1_BIT … #define RT5682_PWR_I2S2 … #define RT5682_PWR_I2S2_BIT … #define RT5682_PWR_DAC_L1 … #define RT5682_PWR_DAC_L1_BIT … #define RT5682_PWR_DAC_R1 … #define RT5682_PWR_DAC_R1_BIT … #define RT5682_PWR_LDO … #define RT5682_PWR_LDO_BIT … #define RT5682_PWR_ADC_L1 … #define RT5682_PWR_ADC_L1_BIT … #define RT5682_PWR_ADC_R1 … #define RT5682_PWR_ADC_R1_BIT … #define RT5682_DIG_GATE_CTRL … #define RT5682_DIG_GATE_CTRL_SFT … /* Power Management for Digital 2 (0x0062) */ #define RT5682_PWR_ADC_S1F … #define RT5682_PWR_ADC_S1F_BIT … #define RT5682_PWR_DAC_S1F … #define RT5682_PWR_DAC_S1F_BIT … /* Power Management for Analog 1 (0x0063) */ #define RT5682_PWR_VREF1 … #define RT5682_PWR_VREF1_BIT … #define RT5682_PWR_FV1 … #define RT5682_PWR_FV1_BIT … #define RT5682_PWR_VREF2 … #define RT5682_PWR_VREF2_BIT … #define RT5682_PWR_FV2 … #define RT5682_PWR_FV2_BIT … #define RT5682_LDO1_DBG_MASK … #define RT5682_PWR_MB … #define RT5682_PWR_MB_BIT … #define RT5682_PWR_BG … #define RT5682_PWR_BG_BIT … #define RT5682_LDO1_BYPASS_MASK … #define RT5682_LDO1_BYPASS … #define RT5682_LDO1_NOT_BYPASS … #define RT5682_PWR_MA_BIT … #define RT5682_LDO1_DVO_MASK … #define RT5682_LDO1_DVO_09 … #define RT5682_LDO1_DVO_10 … #define RT5682_LDO1_DVO_12 … #define RT5682_LDO1_DVO_14 … #define RT5682_HP_DRIVER_MASK … #define RT5682_HP_DRIVER_1X … #define RT5682_HP_DRIVER_3X … #define RT5682_HP_DRIVER_5X … #define RT5682_PWR_HA_L … #define RT5682_PWR_HA_L_BIT … #define RT5682_PWR_HA_R … #define RT5682_PWR_HA_R_BIT … /* Power Management for Analog 2 (0x0064) */ #define RT5682_PWR_MB1 … #define RT5682_PWR_MB1_PWR_DOWN … #define RT5682_PWR_MB1_BIT … #define RT5682_PWR_MB2 … #define RT5682_PWR_MB2_PWR_DOWN … #define RT5682_PWR_MB2_BIT … #define RT5682_PWR_JDH … #define RT5682_PWR_JDH_BIT … #define RT5682_PWR_JDL … #define RT5682_PWR_JDL_BIT … #define RT5682_PWR_RM1_L … #define RT5682_PWR_RM1_L_BIT … /* Power Management for Analog 3 (0x0065) */ #define RT5682_PWR_CBJ … #define RT5682_PWR_CBJ_BIT … #define RT5682_PWR_PLL … #define RT5682_PWR_PLL_BIT … #define RT5682_PWR_PLL2B … #define RT5682_PWR_PLL2B_BIT … #define RT5682_PWR_PLL2F … #define RT5682_PWR_PLL2F_BIT … #define RT5682_PWR_LDO2 … #define RT5682_PWR_LDO2_BIT … #define RT5682_PWR_DET_SPKVDD … #define RT5682_PWR_DET_SPKVDD_BIT … /* Power Management for Mixer (0x0066) */ #define RT5682_PWR_STO1_DAC_L … #define RT5682_PWR_STO1_DAC_L_BIT … #define RT5682_PWR_STO1_DAC_R … #define RT5682_PWR_STO1_DAC_R_BIT … /* MCLK and System Clock Detection Control (0x006b) */ #define RT5682_SYS_CLK_DET … #define RT5682_SYS_CLK_DET_SFT … #define RT5682_PLL1_CLK_DET … #define RT5682_PLL1_CLK_DET_SFT … #define RT5682_PLL2_CLK_DET … #define RT5682_PLL2_CLK_DET_SFT … #define RT5682_POW_CLK_DET2_SFT … #define RT5682_POW_CLK_DET_SFT … /* Digital Microphone Control 1 (0x006e) */ #define RT5682_DMIC_1_EN_MASK … #define RT5682_DMIC_1_EN_SFT … #define RT5682_DMIC_1_DIS … #define RT5682_DMIC_1_EN … #define RT5682_FIFO_CLK_DIV_MASK … #define RT5682_FIFO_CLK_DIV_2 … #define RT5682_DMIC_1_DP_MASK … #define RT5682_DMIC_1_DP_SFT … #define RT5682_DMIC_1_DP_GPIO2 … #define RT5682_DMIC_1_DP_GPIO5 … #define RT5682_DMIC_CLK_MASK … #define RT5682_DMIC_CLK_SFT … /* I2S1 Audio Serial Data Port Control (0x0070) */ #define RT5682_SEL_ADCDAT_MASK … #define RT5682_SEL_ADCDAT_OUT … #define RT5682_SEL_ADCDAT_IN … #define RT5682_SEL_ADCDAT_SFT … #define RT5682_I2S1_TX_CHL_MASK … #define RT5682_I2S1_TX_CHL_SFT … #define RT5682_I2S1_TX_CHL_16 … #define RT5682_I2S1_TX_CHL_20 … #define RT5682_I2S1_TX_CHL_24 … #define RT5682_I2S1_TX_CHL_32 … #define RT5682_I2S1_TX_CHL_8 … #define RT5682_I2S1_RX_CHL_MASK … #define RT5682_I2S1_RX_CHL_SFT … #define RT5682_I2S1_RX_CHL_16 … #define RT5682_I2S1_RX_CHL_20 … #define RT5682_I2S1_RX_CHL_24 … #define RT5682_I2S1_RX_CHL_32 … #define RT5682_I2S1_RX_CHL_8 … #define RT5682_I2S1_MONO_MASK … #define RT5682_I2S1_MONO_EN … #define RT5682_I2S1_MONO_DIS … #define RT5682_I2S2_MONO_MASK … #define RT5682_I2S2_MONO_EN … #define RT5682_I2S2_MONO_DIS … #define RT5682_I2S1_DL_MASK … #define RT5682_I2S1_DL_SFT … #define RT5682_I2S1_DL_16 … #define RT5682_I2S1_DL_20 … #define RT5682_I2S1_DL_24 … #define RT5682_I2S1_DL_32 … #define RT5682_I2S1_DL_8 … /* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */ #define RT5682_I2S2_MS_MASK … #define RT5682_I2S2_MS_SFT … #define RT5682_I2S2_MS_M … #define RT5682_I2S2_MS_S … #define RT5682_I2S2_PIN_CFG_MASK … #define RT5682_I2S2_PIN_CFG_SFT … #define RT5682_I2S2_CLK_SEL_MASK … #define RT5682_I2S2_CLK_SEL_SFT … #define RT5682_I2S2_OUT_MASK … #define RT5682_I2S2_OUT_SFT … #define RT5682_I2S2_OUT_UM … #define RT5682_I2S2_OUT_M … #define RT5682_I2S_BP_MASK … #define RT5682_I2S_BP_SFT … #define RT5682_I2S_BP_NOR … #define RT5682_I2S_BP_INV … #define RT5682_I2S2_MONO_EN … #define RT5682_I2S2_MONO_DIS … #define RT5682_I2S2_DL_MASK … #define RT5682_I2S2_DL_SFT … #define RT5682_I2S2_DL_16 … #define RT5682_I2S2_DL_20 … #define RT5682_I2S2_DL_24 … #define RT5682_I2S2_DL_8 … #define RT5682_I2S_DF_MASK … #define RT5682_I2S_DF_SFT … #define RT5682_I2S_DF_I2S … #define RT5682_I2S_DF_LEFT … #define RT5682_I2S_DF_PCM_A … #define RT5682_I2S_DF_PCM_B … #define RT5682_I2S_DF_PCM_A_N … #define RT5682_I2S_DF_PCM_B_N … /* ADC/DAC Clock Control 1 (0x0073) */ #define RT5682_ADC_OSR_MASK … #define RT5682_ADC_OSR_SFT … #define RT5682_ADC_OSR_D_1 … #define RT5682_ADC_OSR_D_2 … #define RT5682_ADC_OSR_D_4 … #define RT5682_ADC_OSR_D_6 … #define RT5682_ADC_OSR_D_8 … #define RT5682_ADC_OSR_D_12 … #define RT5682_ADC_OSR_D_16 … #define RT5682_ADC_OSR_D_24 … #define RT5682_ADC_OSR_D_32 … #define RT5682_ADC_OSR_D_48 … #define RT5682_I2S_M_DIV_MASK … #define RT5682_I2S_M_DIV_SFT … #define RT5682_I2S_M_D_1 … #define RT5682_I2S_M_D_2 … #define RT5682_I2S_M_D_3 … #define RT5682_I2S_M_D_4 … #define RT5682_I2S_M_D_6 … #define RT5682_I2S_M_D_8 … #define RT5682_I2S_M_D_12 … #define RT5682_I2S_M_D_16 … #define RT5682_I2S_M_D_24 … #define RT5682_I2S_M_D_32 … #define RT5682_I2S_M_D_48 … #define RT5682_I2S_CLK_SRC_MASK … #define RT5682_I2S_CLK_SRC_SFT … #define RT5682_I2S_CLK_SRC_MCLK … #define RT5682_I2S_CLK_SRC_PLL1 … #define RT5682_I2S_CLK_SRC_PLL2 … #define RT5682_I2S_CLK_SRC_SDW … #define RT5682_I2S_CLK_SRC_RCCLK … #define RT5682_DAC_OSR_MASK … #define RT5682_DAC_OSR_SFT … #define RT5682_DAC_OSR_D_1 … #define RT5682_DAC_OSR_D_2 … #define RT5682_DAC_OSR_D_4 … #define RT5682_DAC_OSR_D_6 … #define RT5682_DAC_OSR_D_8 … #define RT5682_DAC_OSR_D_12 … #define RT5682_DAC_OSR_D_16 … #define RT5682_DAC_OSR_D_24 … #define RT5682_DAC_OSR_D_32 … #define RT5682_DAC_OSR_D_48 … /* ADC/DAC Clock Control 2 (0x0074) */ #define RT5682_I2S2_BCLK_MS2_MASK … #define RT5682_I2S2_BCLK_MS2_SFT … #define RT5682_I2S2_BCLK_MS2_32 … #define RT5682_I2S2_BCLK_MS2_64 … /* TDM control 1 (0x0079) */ #define RT5682_TDM_TX_CH_MASK … #define RT5682_TDM_TX_CH_2 … #define RT5682_TDM_TX_CH_4 … #define RT5682_TDM_TX_CH_6 … #define RT5682_TDM_TX_CH_8 … #define RT5682_TDM_RX_CH_MASK … #define RT5682_TDM_RX_CH_2 … #define RT5682_TDM_RX_CH_4 … #define RT5682_TDM_RX_CH_6 … #define RT5682_TDM_RX_CH_8 … #define RT5682_TDM_ADC_LCA_MASK … #define RT5682_TDM_ADC_LCA_SFT … #define RT5682_TDM_ADC_DL_SFT … /* TDM control 2 (0x007a) */ #define RT5682_IF1_ADC1_SEL_SFT … #define RT5682_IF1_ADC2_SEL_SFT … #define RT5682_IF1_ADC3_SEL_SFT … #define RT5682_IF1_ADC4_SEL_SFT … #define RT5682_TDM_ADC_SEL_SFT … /* TDM control 3 (0x007b) */ #define RT5682_TDM_EN … /* TDM/I2S control (0x007e) */ #define RT5682_TDM_S_BP_MASK … #define RT5682_TDM_S_BP_SFT … #define RT5682_TDM_S_BP_NOR … #define RT5682_TDM_S_BP_INV … #define RT5682_TDM_S_LP_MASK … #define RT5682_TDM_S_LP_SFT … #define RT5682_TDM_S_LP_NOR … #define RT5682_TDM_S_LP_INV … #define RT5682_TDM_DF_MASK … #define RT5682_TDM_DF_SFT … #define RT5682_TDM_DF_I2S … #define RT5682_TDM_DF_LEFT … #define RT5682_TDM_DF_PCM_A … #define RT5682_TDM_DF_PCM_B … #define RT5682_TDM_DF_PCM_A_N … #define RT5682_TDM_DF_PCM_B_N … #define RT5682_TDM_BCLK_MS1_MASK … #define RT5682_TDM_BCLK_MS1_SFT … #define RT5682_TDM_BCLK_MS1_32 … #define RT5682_TDM_BCLK_MS1_64 … #define RT5682_TDM_BCLK_MS1_128 … #define RT5682_TDM_BCLK_MS1_256 … #define RT5682_TDM_CL_MASK … #define RT5682_TDM_CL_16 … #define RT5682_TDM_CL_20 … #define RT5682_TDM_CL_24 … #define RT5682_TDM_CL_32 … #define RT5682_TDM_M_BP_MASK … #define RT5682_TDM_M_BP_SFT … #define RT5682_TDM_M_BP_NOR … #define RT5682_TDM_M_BP_INV … #define RT5682_TDM_M_LP_MASK … #define RT5682_TDM_M_LP_SFT … #define RT5682_TDM_M_LP_NOR … #define RT5682_TDM_M_LP_INV … #define RT5682_TDM_MS_MASK … #define RT5682_TDM_MS_SFT … #define RT5682_TDM_MS_S … #define RT5682_TDM_MS_M … /* Global Clock Control (0x0080) */ #define RT5682_SCLK_SRC_MASK … #define RT5682_SCLK_SRC_SFT … #define RT5682_SCLK_SRC_MCLK … #define RT5682_SCLK_SRC_PLL1 … #define RT5682_SCLK_SRC_PLL2 … #define RT5682_SCLK_SRC_SDW … #define RT5682_SCLK_SRC_RCCLK … #define RT5682_PLL2_SRC_MASK … #define RT5682_PLL2_SRC_SFT … #define RT5682_PLL2_SRC_MCLK … #define RT5682_PLL2_SRC_BCLK1 … #define RT5682_PLL2_SRC_SDW … #define RT5682_PLL2_SRC_RC … #define RT5682_PLL1_SRC_MASK … #define RT5682_PLL1_SRC_SFT … #define RT5682_PLL1_SRC_MCLK … #define RT5682_PLL1_SRC_BCLK1 … #define RT5682_PLL1_SRC_SDW … #define RT5682_PLL1_SRC_RC … #define RT5682_PLL_INP_MAX … #define RT5682_PLL_INP_MIN … /* PLL M/N/K Code Control 1 (0x0081) */ #define RT5682_PLL_N_MAX … #define RT5682_PLL_N_MASK … #define RT5682_PLL_N_SFT … #define RT5682_PLL_K_MAX … #define RT5682_PLL_K_MASK … #define RT5682_PLL_K_SFT … /* PLL M/N/K Code Control 2 (0x0082) */ #define RT5682_PLL_M_MAX … #define RT5682_PLL_M_MASK … #define RT5682_PLL_M_SFT … #define RT5682_PLL_M_BP … #define RT5682_PLL_M_BP_SFT … #define RT5682_PLL_K_BP … #define RT5682_PLL_K_BP_SFT … #define RT5682_PLL_RST … /* PLL tracking mode 1 (0x0083) */ #define RT5682_DA_ASRC_MASK … #define RT5682_DA_ASRC_SFT … #define RT5682_DAC_STO1_ASRC_MASK … #define RT5682_DAC_STO1_ASRC_SFT … #define RT5682_AD_ASRC_MASK … #define RT5682_AD_ASRC_SFT … #define RT5682_AD_ASRC_SEL_MASK … #define RT5682_AD_ASRC_SEL_SFT … #define RT5682_DMIC_ASRC_MASK … #define RT5682_DMIC_ASRC_SFT … #define RT5682_ADC_STO1_ASRC_MASK … #define RT5682_ADC_STO1_ASRC_SFT … #define RT5682_DA_ASRC_SEL_MASK … #define RT5682_DA_ASRC_SEL_SFT … /* PLL tracking mode 2 3 (0x0084)(0x0085)*/ #define RT5682_FILTER_CLK_SEL_MASK … #define RT5682_FILTER_CLK_SEL_SFT … #define RT5682_FILTER_CLK_DIV_MASK … #define RT5682_FILTER_CLK_DIV_SFT … /* ASRC Control 4 (0x0086) */ #define RT5682_ASRCIN_FTK_N1_MASK … #define RT5682_ASRCIN_FTK_N1_SFT … #define RT5682_ASRCIN_FTK_N2_MASK … #define RT5682_ASRCIN_FTK_N2_SFT … #define RT5682_ASRCIN_FTK_M1_MASK … #define RT5682_ASRCIN_FTK_M1_SFT … #define RT5682_ASRCIN_FTK_M2_MASK … #define RT5682_ASRCIN_FTK_M2_SFT … /* SoundWire reference clk (0x008d) */ #define RT5682_PLL2_OUT_MASK … #define RT5682_PLL2_OUT_98M … #define RT5682_PLL2_OUT_49M … #define RT5682_SDW_REF_2_MASK … #define RT5682_SDW_REF_2_SFT … #define RT5682_SDW_REF_2_48K … #define RT5682_SDW_REF_2_96K … #define RT5682_SDW_REF_2_192K … #define RT5682_SDW_REF_2_32K … #define RT5682_SDW_REF_2_24K … #define RT5682_SDW_REF_2_16K … #define RT5682_SDW_REF_2_12K … #define RT5682_SDW_REF_2_8K … #define RT5682_SDW_REF_2_44K … #define RT5682_SDW_REF_2_88K … #define RT5682_SDW_REF_2_176K … #define RT5682_SDW_REF_2_353K … #define RT5682_SDW_REF_2_22K … #define RT5682_SDW_REF_2_384K … #define RT5682_SDW_REF_2_11K … #define RT5682_SDW_REF_1_MASK … #define RT5682_SDW_REF_1_SFT … #define RT5682_SDW_REF_1_48K … #define RT5682_SDW_REF_1_96K … #define RT5682_SDW_REF_1_192K … #define RT5682_SDW_REF_1_32K … #define RT5682_SDW_REF_1_24K … #define RT5682_SDW_REF_1_16K … #define RT5682_SDW_REF_1_12K … #define RT5682_SDW_REF_1_8K … #define RT5682_SDW_REF_1_44K … #define RT5682_SDW_REF_1_88K … #define RT5682_SDW_REF_1_176K … #define RT5682_SDW_REF_1_353K … #define RT5682_SDW_REF_1_22K … #define RT5682_SDW_REF_1_384K … #define RT5682_SDW_REF_1_11K … /* Depop Mode Control 1 (0x008e) */ #define RT5682_PUMP_EN … #define RT5682_PUMP_EN_SFT … #define RT5682_CAPLESS_EN … #define RT5682_CAPLESS_EN_SFT … /* Depop Mode Control 2 (0x8f) */ #define RT5682_RAMP_MASK … #define RT5682_RAMP_SFT … #define RT5682_RAMP_DIS … #define RT5682_RAMP_EN … #define RT5682_BPS_MASK … #define RT5682_BPS_SFT … #define RT5682_BPS_DIS … #define RT5682_BPS_EN … #define RT5682_FAST_UPDN_MASK … #define RT5682_FAST_UPDN_SFT … #define RT5682_FAST_UPDN_DIS … #define RT5682_FAST_UPDN_EN … #define RT5682_VLO_MASK … #define RT5682_VLO_SFT … #define RT5682_VLO_3V … #define RT5682_VLO_33V … /* HPOUT charge pump 1 (0x0091) */ #define RT5682_OSW_L_MASK … #define RT5682_OSW_L_SFT … #define RT5682_OSW_L_DIS … #define RT5682_OSW_L_EN … #define RT5682_OSW_R_MASK … #define RT5682_OSW_R_SFT … #define RT5682_OSW_R_DIS … #define RT5682_OSW_R_EN … #define RT5682_PM_HP_MASK … #define RT5682_PM_HP_SFT … #define RT5682_PM_HP_LV … #define RT5682_PM_HP_MV … #define RT5682_PM_HP_HV … #define RT5682_IB_HP_MASK … #define RT5682_IB_HP_SFT … #define RT5682_IB_HP_125IL … #define RT5682_IB_HP_25IL … #define RT5682_IB_HP_5IL … #define RT5682_IB_HP_1IL … /* Micbias Control1 (0x93) */ #define RT5682_MIC1_OV_MASK … #define RT5682_MIC1_OV_SFT … #define RT5682_MIC1_OV_2V7 … #define RT5682_MIC1_OV_2V4 … #define RT5682_MIC1_OV_2V25 … #define RT5682_MIC1_OV_1V8 … #define RT5682_MIC1_CLK_MASK … #define RT5682_MIC1_CLK_SFT … #define RT5682_MIC1_CLK_DIS … #define RT5682_MIC1_CLK_EN … #define RT5682_MIC1_OVCD_MASK … #define RT5682_MIC1_OVCD_SFT … #define RT5682_MIC1_OVCD_DIS … #define RT5682_MIC1_OVCD_EN … #define RT5682_MIC1_OVTH_MASK … #define RT5682_MIC1_OVTH_SFT … #define RT5682_MIC1_OVTH_768UA … #define RT5682_MIC1_OVTH_960UA … #define RT5682_MIC1_OVTH_1152UA … #define RT5682_MIC1_OVTH_1960UA … #define RT5682_MIC2_OV_MASK … #define RT5682_MIC2_OV_SFT … #define RT5682_MIC2_OV_2V7 … #define RT5682_MIC2_OV_2V4 … #define RT5682_MIC2_OV_2V25 … #define RT5682_MIC2_OV_1V8 … #define RT5682_MIC2_CLK_MASK … #define RT5682_MIC2_CLK_SFT … #define RT5682_MIC2_CLK_DIS … #define RT5682_MIC2_CLK_EN … #define RT5682_MIC2_OVTH_MASK … #define RT5682_MIC2_OVTH_SFT … #define RT5682_MIC2_OVTH_768UA … #define RT5682_MIC2_OVTH_960UA … #define RT5682_MIC2_OVTH_1152UA … #define RT5682_MIC2_OVTH_1960UA … #define RT5682_PWR_MB_MASK … #define RT5682_PWR_MB_SFT … #define RT5682_PWR_MB_PD … #define RT5682_PWR_MB_PU … /* Micbias Control2 (0x0094) */ #define RT5682_PWR_CLK25M_MASK … #define RT5682_PWR_CLK25M_SFT … #define RT5682_PWR_CLK25M_PD … #define RT5682_PWR_CLK25M_PU … #define RT5682_PWR_CLK1M_MASK … #define RT5682_PWR_CLK1M_SFT … #define RT5682_PWR_CLK1M_PD … #define RT5682_PWR_CLK1M_PU … /* PLL2 M/N/K Code Control 1 (0x009b) */ #define RT5682_PLL2F_K_MASK … #define RT5682_PLL2F_K_SFT … #define RT5682_PLL2B_K_MASK … #define RT5682_PLL2B_K_SFT … #define RT5682_PLL2B_M_MASK … /* PLL2 M/N/K Code Control 2 (0x009c) */ #define RT5682_PLL2F_M_MASK … #define RT5682_PLL2F_M_SFT … #define RT5682_PLL2B_N_MASK … /* PLL2 M/N/K Code Control 2 (0x009d) */ #define RT5682_PLL2F_N_MASK … #define RT5682_PLL2F_N_SFT … /* PLL2 M/N/K Code Control 2 (0x009e) */ #define RT5682_PLL2B_SEL_PS_MASK … #define RT5682_PLL2B_SEL_PS_SFT … #define RT5682_PLL2B_PS_BYP_MASK … #define RT5682_PLL2B_PS_BYP_SFT … #define RT5682_PLL2B_M_BP_MASK … #define RT5682_PLL2B_M_BP_SFT … #define RT5682_PLL2F_M_BP_MASK … #define RT5682_PLL2F_M_BP_SFT … /* RC Clock Control (0x009f) */ #define RT5682_POW_IRQ … #define RT5682_POW_JDH … #define RT5682_POW_JDL … #define RT5682_POW_ANA … /* I2S Master Mode Clock Control 1 (0x00a0) */ #define RT5682_CLK_SRC_MCLK … #define RT5682_CLK_SRC_PLL1 … #define RT5682_CLK_SRC_PLL2 … #define RT5682_CLK_SRC_SDW … #define RT5682_CLK_SRC_RCCLK … #define RT5682_I2S_PD_1 … #define RT5682_I2S_PD_2 … #define RT5682_I2S_PD_3 … #define RT5682_I2S_PD_4 … #define RT5682_I2S_PD_6 … #define RT5682_I2S_PD_8 … #define RT5682_I2S_PD_12 … #define RT5682_I2S_PD_16 … #define RT5682_I2S_PD_24 … #define RT5682_I2S_PD_32 … #define RT5682_I2S_PD_48 … #define RT5682_I2S2_SRC_MASK … #define RT5682_I2S2_SRC_SFT … #define RT5682_I2S2_M_PD_MASK … #define RT5682_I2S2_M_PD_SFT … /* IRQ Control 1 (0x00b6) */ #define RT5682_JD1_PULSE_EN_MASK … #define RT5682_JD1_PULSE_EN_SFT … #define RT5682_JD1_PULSE_DIS … #define RT5682_JD1_PULSE_EN … /* IRQ Control 2 (0x00b7) */ #define RT5682_JD1_EN_MASK … #define RT5682_JD1_EN_SFT … #define RT5682_JD1_DIS … #define RT5682_JD1_EN … #define RT5682_JD1_POL_MASK … #define RT5682_JD1_POL_NOR … #define RT5682_JD1_POL_INV … #define RT5682_JD1_IRQ_MASK … #define RT5682_JD1_IRQ_LEV … #define RT5682_JD1_IRQ_PUL … /* IRQ Control 3 (0x00b8) */ #define RT5682_IL_IRQ_MASK … #define RT5682_IL_IRQ_DIS … #define RT5682_IL_IRQ_EN … #define RT5682_IL_IRQ_TYPE_MASK … #define RT5682_IL_IRQ_LEV … #define RT5682_IL_IRQ_PUL … /* GPIO Control 1 (0x00c0) */ #define RT5682_GP1_PIN_MASK … #define RT5682_GP1_PIN_SFT … #define RT5682_GP1_PIN_GPIO1 … #define RT5682_GP1_PIN_IRQ … #define RT5682_GP1_PIN_DMIC_CLK … #define RT5682_GP2_PIN_MASK … #define RT5682_GP2_PIN_SFT … #define RT5682_GP2_PIN_GPIO2 … #define RT5682_GP2_PIN_LRCK2 … #define RT5682_GP2_PIN_DMIC_SDA … #define RT5682_GP3_PIN_MASK … #define RT5682_GP3_PIN_SFT … #define RT5682_GP3_PIN_GPIO3 … #define RT5682_GP3_PIN_BCLK2 … #define RT5682_GP3_PIN_DMIC_CLK … #define RT5682_GP4_PIN_MASK … #define RT5682_GP4_PIN_SFT … #define RT5682_GP4_PIN_GPIO4 … #define RT5682_GP4_PIN_ADCDAT1 … #define RT5682_GP4_PIN_DMIC_CLK … #define RT5682_GP4_PIN_ADCDAT2 … #define RT5682_GP5_PIN_MASK … #define RT5682_GP5_PIN_SFT … #define RT5682_GP5_PIN_GPIO5 … #define RT5682_GP5_PIN_DACDAT1 … #define RT5682_GP5_PIN_DMIC_SDA … #define RT5682_GP6_PIN_MASK … #define RT5682_GP6_PIN_SFT … #define RT5682_GP6_PIN_GPIO6 … #define RT5682_GP6_PIN_LRCK1 … /* GPIO Control 2 (0x00c1)*/ #define RT5682_GP1_PF_MASK … #define RT5682_GP1_PF_IN … #define RT5682_GP1_PF_OUT … #define RT5682_GP1_OUT_MASK … #define RT5682_GP1_OUT_L … #define RT5682_GP1_OUT_H … #define RT5682_GP2_PF_MASK … #define RT5682_GP2_PF_IN … #define RT5682_GP2_PF_OUT … #define RT5682_GP2_OUT_MASK … #define RT5682_GP2_OUT_L … #define RT5682_GP2_OUT_H … #define RT5682_GP3_PF_MASK … #define RT5682_GP3_PF_IN … #define RT5682_GP3_PF_OUT … #define RT5682_GP3_OUT_MASK … #define RT5682_GP3_OUT_L … #define RT5682_GP3_OUT_H … #define RT5682_GP4_PF_MASK … #define RT5682_GP4_PF_IN … #define RT5682_GP4_PF_OUT … #define RT5682_GP4_OUT_MASK … #define RT5682_GP4_OUT_L … #define RT5682_GP4_OUT_H … #define RT5682_GP5_PF_MASK … #define RT5682_GP5_PF_IN … #define RT5682_GP5_PF_OUT … #define RT5682_GP5_OUT_MASK … #define RT5682_GP5_OUT_L … #define RT5682_GP5_OUT_H … #define RT5682_GP6_PF_MASK … #define RT5682_GP6_PF_IN … #define RT5682_GP6_PF_OUT … #define RT5682_GP6_OUT_MASK … #define RT5682_GP6_OUT_L … #define RT5682_GP6_OUT_H … /* GPIO Status (0x00c2) */ #define RT5682_GP6_STA … #define RT5682_GP5_STA … #define RT5682_GP4_STA … #define RT5682_GP3_STA … #define RT5682_GP2_STA … #define RT5682_GP1_STA … /* Soft volume and zero cross control 1 (0x00d9) */ #define RT5682_SV_MASK … #define RT5682_SV_SFT … #define RT5682_SV_DIS … #define RT5682_SV_EN … #define RT5682_ZCD_MASK … #define RT5682_ZCD_SFT … #define RT5682_ZCD_PD … #define RT5682_ZCD_PU … #define RT5682_SV_DLY_MASK … #define RT5682_SV_DLY_SFT … /* Soft volume and zero cross control 2 (0x00da) */ #define RT5682_ZCD_BST1_CBJ_MASK … #define RT5682_ZCD_BST1_CBJ_SFT … #define RT5682_ZCD_BST1_CBJ_DIS … #define RT5682_ZCD_BST1_CBJ_EN … #define RT5682_ZCD_RECMIX_MASK … #define RT5682_ZCD_RECMIX_SFT … #define RT5682_ZCD_RECMIX_DIS … #define RT5682_ZCD_RECMIX_EN … /* 4 Button Inline Command Control 2 (0x00e3) */ #define RT5682_4BTN_IL_MASK … #define RT5682_4BTN_IL_EN … #define RT5682_4BTN_IL_DIS … #define RT5682_4BTN_IL_RST_MASK … #define RT5682_4BTN_IL_NOR … #define RT5682_4BTN_IL_RST … /* Analog JD Control (0x00f0) */ #define RT5682_JDH_RS_MASK … #define RT5682_JDH_NO_PLUG … #define RT5682_JDH_PLUG … /* Bias current control 8 (0x0111) */ #define RT5682_HPA_CP_BIAS_CTRL_MASK … #define RT5682_HPA_CP_BIAS_2UA … #define RT5682_HPA_CP_BIAS_3UA … #define RT5682_HPA_CP_BIAS_4UA … #define RT5682_HPA_CP_BIAS_6UA … /* Charge Pump Internal Register1 (0x0125) */ #define RT5682_CP_SW_SIZE_MASK … #define RT5682_CP_SW_SIZE_L … #define RT5682_CP_SW_SIZE_M … #define RT5682_CP_SW_SIZE_S … #define RT5682_CP_CLK_HP_MASK … #define RT5682_CP_CLK_HP_100KHZ … #define RT5682_CP_CLK_HP_200KHZ … #define RT5682_CP_CLK_HP_300KHZ … #define RT5682_CP_CLK_HP_600KHZ … /* Pad Driving Control (0x0136) */ #define RT5682_PAD_DRV_GP1_MASK … #define RT5682_PAD_DRV_GP1_SFT … #define RT5682_PAD_DRV_GP2_MASK … #define RT5682_PAD_DRV_GP2_SFT … #define RT5682_PAD_DRV_GP3_MASK … #define RT5682_PAD_DRV_GP3_SFT … #define RT5682_PAD_DRV_GP4_MASK … #define RT5682_PAD_DRV_GP4_SFT … #define RT5682_PAD_DRV_GP5_MASK … #define RT5682_PAD_DRV_GP5_SFT … #define RT5682_PAD_DRV_GP6_MASK … #define RT5682_PAD_DRV_GP6_SFT … /* Chopper and Clock control for DAC (0x013a)*/ #define RT5682_CKXEN_DAC1_MASK … #define RT5682_CKXEN_DAC1_SFT … #define RT5682_CKGEN_DAC1_MASK … #define RT5682_CKGEN_DAC1_SFT … /* Chopper and Clock control for ADC (0x013b)*/ #define RT5682_CKXEN_ADC1_MASK … #define RT5682_CKXEN_ADC1_SFT … #define RT5682_CKGEN_ADC1_MASK … #define RT5682_CKGEN_ADC1_SFT … /* Volume test (0x013f)*/ #define RT5682_SEL_CLK_VOL_MASK … #define RT5682_SEL_CLK_VOL_EN … #define RT5682_SEL_CLK_VOL_DIS … /* Test Mode Control 1 (0x0145) */ #define RT5682_AD2DA_LB_MASK … #define RT5682_AD2DA_LB_SFT … /* Stereo Noise Gate Control 1 (0x0160) */ #define RT5682_NG2_EN_MASK … #define RT5682_NG2_EN … #define RT5682_NG2_DIS … /* Stereo1 DAC Silence Detection Control (0x0190) */ #define RT5682_DEB_STO_DAC_MASK … #define RT5682_DEB_80_MS … /* HP Behavior Logic Control 2 (0x01db) */ #define RT5682_HP_LC2_SIG_SOUR2_MASK … #define RT5682_HP_LC2_SIG_SOUR2_REG … #define RT5682_HP_LC2_SIG_SOUR2_DC_CAL … #define RT5682_HP_LC2_SIG_SOUR1_MASK … #define RT5682_HP_LC2_SIG_SOUR1_1BIT … #define RT5682_HP_LC2_SIG_SOUR1_LEGA … /* SAR ADC Inline Command Control 1 (0x0210) */ #define RT5682_SAR_BUTT_DET_MASK … #define RT5682_SAR_BUTT_DET_EN … #define RT5682_SAR_BUTT_DET_DIS … #define RT5682_SAR_BUTDET_MODE_MASK … #define RT5682_SAR_BUTDET_POW_SAV … #define RT5682_SAR_BUTDET_POW_NORM … #define RT5682_SAR_BUTDET_RST_MASK … #define RT5682_SAR_BUTDET_RST_NORMAL … #define RT5682_SAR_BUTDET_RST … #define RT5682_SAR_POW_MASK … #define RT5682_SAR_POW_EN … #define RT5682_SAR_POW_DIS … #define RT5682_SAR_RST_MASK … #define RT5682_SAR_RST_NORMAL … #define RT5682_SAR_RST … #define RT5682_SAR_BYPASS_MASK … #define RT5682_SAR_BYPASS_EN … #define RT5682_SAR_BYPASS_DIS … #define RT5682_SAR_SEL_MB1_MASK … #define RT5682_SAR_SEL_MB1_SEL … #define RT5682_SAR_SEL_MB1_NOSEL … #define RT5682_SAR_SEL_MB2_MASK … #define RT5682_SAR_SEL_MB2_SEL … #define RT5682_SAR_SEL_MB2_NOSEL … #define RT5682_SAR_SEL_MODE_MASK … #define RT5682_SAR_SEL_MODE_CMP … #define RT5682_SAR_SEL_MODE_ADC … #define RT5682_SAR_SEL_MB1_MB2_MASK … #define RT5682_SAR_SEL_MB1_MB2_AUTO … #define RT5682_SAR_SEL_MB1_MB2_MANU … #define RT5682_SAR_SEL_SIGNAL_MASK … #define RT5682_SAR_SEL_SIGNAL_AUTO … #define RT5682_SAR_SEL_SIGNAL_MANU … /* SAR ADC Inline Command Control 13 (0x021c) */ #define RT5682_SAR_SOUR_MASK … #define RT5682_SAR_SOUR_BTN … #define RT5682_SAR_SOUR_TYPE … /* soundwire timeout */ #define RT5682_PROBE_TIMEOUT … #define RT5682_STEREO_RATES … #define RT5682_FORMATS … /* System Clock Source */ enum { … }; /* PLL Source */ enum { … }; enum { … }; enum { … }; /* filter mask */ enum { … }; enum { … }; #define RT5682_NUM_SUPPLIES … struct rt5682_priv { … }; extern const char *rt5682_supply_names[RT5682_NUM_SUPPLIES]; int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, unsigned int filter_mask, unsigned int clk_src); void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev); void rt5682_jack_detect_handler(struct work_struct *work); bool rt5682_volatile_register(struct device *dev, unsigned int reg); bool rt5682_readable_register(struct device *dev, unsigned int reg); int rt5682_register_component(struct device *dev); void rt5682_calibrate(struct rt5682_priv *rt5682); void rt5682_reset(struct rt5682_priv *rt5682); int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev); int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev); int rt5682_register_dai_clks(struct rt5682_priv *rt5682); #define RT5682_REG_NUM … extern const struct reg_default rt5682_reg[RT5682_REG_NUM]; extern const struct snd_soc_dai_ops rt5682_aif1_dai_ops; extern const struct snd_soc_dai_ops rt5682_aif2_dai_ops; extern const struct snd_soc_component_driver rt5682_soc_component_dev; #endif /* __RT5682_H__ */
Codebase Browser
linux