/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt722-sdca.h -- RT722 SDCA ALSA SoC audio driver header * * Copyright(c) 2023 Realtek Semiconductor Corp. */ #ifndef __RT722_H__ #define __RT722_H__ #include <linux/pm.h> #include <linux/regmap.h> #include <linux/soundwire/sdw.h> #include <linux/soundwire/sdw_type.h> #include <sound/soc.h> #include <linux/workqueue.h> struct rt722_sdca_priv { … }; struct rt722_sdca_dmic_kctrl_priv { … }; /* NID */ #define RT722_VENDOR_REG … #define RT722_VENDOR_CALI … #define RT722_VENDOR_SPK_EFUSE … #define RT722_VENDOR_IMS_DRE … #define RT722_VENDOR_ANALOG_CTL … #define RT722_VENDOR_HDA_CTL … /* Index (NID:20h) */ #define RT722_JD_PRODUCT_NUM … #define RT722_ANALOG_BIAS_CTL3 … #define RT722_JD_CTRL1 … #define RT722_LDO2_3_CTL1 … #define RT722_LDO1_CTL … #define RT722_HP_JD_CTRL … #define RT722_CLSD_CTRL6 … #define RT722_COMBO_JACK_AUTO_CTL1 … #define RT722_COMBO_JACK_AUTO_CTL2 … #define RT722_COMBO_JACK_AUTO_CTL3 … #define RT722_DIGITAL_MISC_CTRL4 … #define RT722_VREFO_GAT … #define RT722_FSM_CTL … #define RT722_SDCA_INTR_REC … #define RT722_SW_CONFIG1 … #define RT722_SW_CONFIG2 … /* Index (NID:58h) */ #define RT722_DAC_DC_CALI_CTL0 … #define RT722_DAC_DC_CALI_CTL1 … #define RT722_DAC_DC_CALI_CTL2 … #define RT722_DAC_DC_CALI_CTL3 … /* Index (NID:59h) */ #define RT722_ULTRA_SOUND_DETECTOR6 … /* Index (NID:5bh) */ #define RT722_IMS_DIGITAL_CTL1 … #define RT722_IMS_DIGITAL_CTL5 … #define RT722_HP_DETECT_RLDET_CTL1 … #define RT722_HP_DETECT_RLDET_CTL2 … /* Index (NID:5fh) */ #define RT722_MISC_POWER_CTL0 … #define RT722_MISC_POWER_CTL7 … /* Index (NID:61h) */ #define RT722_HDA_LEGACY_MUX_CTL0 … #define RT722_HDA_LEGACY_UNSOL_CTL … #define RT722_HDA_LEGACY_CONFIG_CTL0 … #define RT722_HDA_LEGACY_RESET_CTL … #define RT722_HDA_LEGACY_GPIO_WAKE_EN_CTL … #define RT722_DMIC_ENT_FLOAT_CTL … #define RT722_DMIC_GAIN_ENT_FLOAT_CTL0 … #define RT722_DMIC_GAIN_ENT_FLOAT_CTL2 … #define RT722_ADC_ENT_FLOAT_CTL … #define RT722_ADC_VOL_CH_FLOAT_CTL … #define RT722_ADC_SAMPLE_RATE_FLOAT … #define RT722_DAC03_HP_PDE_FLOAT_CTL … #define RT722_MIC2_LINE2_PDE_FLOAT_CTL … #define RT722_ET41_LINE2_PDE_FLOAT_CTL … #define RT722_ADC0A_08_PDE_FLOAT_CTL … #define RT722_ADC10_PDE_FLOAT_CTL … #define RT722_DMIC1_2_PDE_FLOAT_CTL … #define RT722_AMP_PDE_FLOAT_CTL … #define RT722_I2S_IN_OUT_PDE_FLOAT_CTL … #define RT722_GE_RELATED_CTL1 … #define RT722_GE_RELATED_CTL2 … #define RT722_MIXER_CTL0 … #define RT722_MIXER_CTL1 … #define RT722_EAPD_CTL … #define RT722_UMP_HID_CTL0 … #define RT722_UMP_HID_CTL1 … #define RT722_UMP_HID_CTL2 … #define RT722_UMP_HID_CTL3 … #define RT722_UMP_HID_CTL4 … #define RT722_UMP_HID_CTL5 … #define RT722_UMP_HID_CTL6 … #define RT722_UMP_HID_CTL7 … #define RT722_UMP_HID_CTL8 … #define RT722_FLOAT_CTRL_1 … #define RT722_ENT_FLOAT_CTRL_1 … /* Parameter & Verb control 01 (0x1a)(NID:20h) */ #define RT722_HIDDEN_REG_SW_RESET … /* combo jack auto switch control 2 (0x46)(NID:20h) */ #define RT722_COMBOJACK_AUTO_DET_STATUS … #define RT722_COMBOJACK_AUTO_DET_TRS … #define RT722_COMBOJACK_AUTO_DET_CTIA … #define RT722_COMBOJACK_AUTO_DET_OMTP … /* DAC calibration control (0x00)(NID:58h) */ #define RT722_DC_CALIB_CTRL … /* DAC DC offset calibration control-1 (0x01)(NID:58h) */ #define RT722_PDM_DC_CALIB_STATUS … #define RT722_EAPD_HIGH … #define RT722_EAPD_LOW … /* Buffer address for HID */ #define RT722_BUF_ADDR_HID1 … #define RT722_BUF_ADDR_HID2 … /* RT722 SDCA Control - function number */ #define FUNC_NUM_JACK_CODEC … #define FUNC_NUM_MIC_ARRAY … #define FUNC_NUM_HID … #define FUNC_NUM_AMP … /* RT722 SDCA entity */ #define RT722_SDCA_ENT_HID01 … #define RT722_SDCA_ENT_GE49 … #define RT722_SDCA_ENT_USER_FU05 … #define RT722_SDCA_ENT_USER_FU06 … #define RT722_SDCA_ENT_USER_FU0F … #define RT722_SDCA_ENT_USER_FU10 … #define RT722_SDCA_ENT_USER_FU1E … #define RT722_SDCA_ENT_FU15 … #define RT722_SDCA_ENT_PDE23 … #define RT722_SDCA_ENT_PDE40 … #define RT722_SDCA_ENT_PDE11 … #define RT722_SDCA_ENT_PDE12 … #define RT722_SDCA_ENT_PDE2A … #define RT722_SDCA_ENT_CS01 … #define RT722_SDCA_ENT_CS11 … #define RT722_SDCA_ENT_CS1F … #define RT722_SDCA_ENT_CS1C … #define RT722_SDCA_ENT_CS31 … #define RT722_SDCA_ENT_OT23 … #define RT722_SDCA_ENT_IT26 … #define RT722_SDCA_ENT_IT09 … #define RT722_SDCA_ENT_PLATFORM_FU15 … #define RT722_SDCA_ENT_PLATFORM_FU44 … #define RT722_SDCA_ENT_XU03 … #define RT722_SDCA_ENT_XU0D … /* RT722 SDCA control */ #define RT722_SDCA_CTL_SAMPLE_FREQ_INDEX … #define RT722_SDCA_CTL_FU_MUTE … #define RT722_SDCA_CTL_FU_VOLUME … #define RT722_SDCA_CTL_HIDTX_CURRENT_OWNER … #define RT722_SDCA_CTL_HIDTX_SET_OWNER_TO_DEVICE … #define RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET … #define RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH … #define RT722_SDCA_CTL_SELECTED_MODE … #define RT722_SDCA_CTL_DETECTED_MODE … #define RT722_SDCA_CTL_REQ_POWER_STATE … #define RT722_SDCA_CTL_VENDOR_DEF … #define RT722_SDCA_CTL_FU_CH_GAIN … /* RT722 SDCA channel */ #define CH_L … #define CH_R … #define CH_01 … #define CH_02 … #define CH_03 … #define CH_04 … #define CH_08 … /* sample frequency index */ #define RT722_SDCA_RATE_16000HZ … #define RT722_SDCA_RATE_32000HZ … #define RT722_SDCA_RATE_44100HZ … #define RT722_SDCA_RATE_48000HZ … #define RT722_SDCA_RATE_96000HZ … #define RT722_SDCA_RATE_192000HZ … enum { … }; enum rt722_sdca_jd_src { … }; int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave); int rt722_sdca_init(struct device *dev, struct regmap *regmap, struct regmap *mbq_regmap, struct sdw_slave *slave); int rt722_sdca_index_write(struct rt722_sdca_priv *rt722, unsigned int nid, unsigned int reg, unsigned int value); int rt722_sdca_index_read(struct rt722_sdca_priv *rt722, unsigned int nid, unsigned int reg, unsigned int *value); int rt722_sdca_jack_detect(struct rt722_sdca_priv *rt722, bool *hp, bool *mic); #endif /* __RT722_H__ */
Codebase Browser
linux