/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * sma1303.h -- sma1303 ALSA SoC Audio driver * * Copyright 2023 Iron Device Corporation * * Author: Kiseok Jo <[email protected]> * */ #ifndef _SMA1303_H #define _SMA1303_H #define SMA1303_I2C_ADDR_00 … #define SMA1303_I2C_ADDR_01 … #define SMA1303_I2C_ADDR_10 … #define SMA1303_I2C_ADDR_11 … #define SMA1303_EXTERNAL_CLOCK_19_2 … #define SMA1303_EXTERNAL_CLOCK_24_576 … #define SMA1303_PLL_CLKIN_MCLK … #define SMA1303_PLL_CLKIN_BCLK … #define SMA1303_MONO … #define SMA1303_STEREO … #define SMA1303_I2C_RETRY_COUNT … /* * SMA1303 Register Definition */ /* SMA1303 Register Addresses */ #define SMA1303_00_SYSTEM_CTRL … #define SMA1303_01_INPUT1_CTRL1 … #define SMA1303_02_INPUT1_CTRL2 … #define SMA1303_03_INPUT1_CTRL3 … #define SMA1303_04_INPUT1_CTRL4 … /* 0x05 ~ 0x08 : Reserved */ #define SMA1303_09_OUTPUT_CTRL … #define SMA1303_0A_SPK_VOL … #define SMA1303_0B_BST_TEST … #define SMA1303_0C_BST_TEST1 … #define SMA1303_0D_SPK_TEST … #define SMA1303_0E_MUTE_VOL_CTRL … /* 0x0F : Reserved */ #define SMA1303_10_SYSTEM_CTRL1 … #define SMA1303_11_SYSTEM_CTRL2 … #define SMA1303_12_SYSTEM_CTRL3 … /* 0x13 : Reserved */ #define SMA1303_14_MODULATOR … #define SMA1303_15_BASS_SPK1 … #define SMA1303_16_BASS_SPK2 … #define SMA1303_17_BASS_SPK3 … #define SMA1303_18_BASS_SPK4 … #define SMA1303_19_BASS_SPK5 … #define SMA1303_1A_BASS_SPK6 … #define SMA1303_1B_BASS_SPK7 … /* 0x1C ~ 0x22 : Reserved */ #define SMA1303_23_COMP_LIM1 … #define SMA1303_24_COMP_LIM2 … #define SMA1303_25_COMP_LIM3 … #define SMA1303_26_COMP_LIM4 … /* 0x27 ~ 0x32 : Reserved */ #define SMA1303_33_SDM_CTRL … #define SMA1303_34_OTP_DATA1 … /* 0x35 : Reserved */ #define SMA1303_36_PROTECTION … #define SMA1303_37_SLOPE_CTRL … #define SMA1303_38_OTP_TRM0 … /* 0x39 ~ 0x3A : Reserved */ #define SMA1303_3B_TEST1 … #define SMA1303_3C_TEST2 … #define SMA1303_3D_TEST3 … #define SMA1303_3E_ATEST1 … #define SMA1303_3F_ATEST2 … /* 0x40 ~ 0x8A : Reserved */ #define SMA1303_8B_PLL_POST_N … #define SMA1303_8C_PLL_N … #define SMA1303_8D_PLL_A_SETTING … #define SMA1303_8E_PLL_CTRL … #define SMA1303_8F_PLL_P_CP … #define SMA1303_90_POSTSCALER … #define SMA1303_91_CLASS_G_CTRL … #define SMA1303_92_FDPEC_CTRL … /* 0x93 : Reserved */ #define SMA1303_94_BOOST_CTRL1 … #define SMA1303_95_BOOST_CTRL2 … #define SMA1303_96_BOOST_CTRL3 … #define SMA1303_97_BOOST_CTRL4 … /* 0x98 ~ 0x9F : Reserved */ #define SMA1303_A0_PAD_CTRL0 … #define SMA1303_A1_PAD_CTRL1 … #define SMA1303_A2_TOP_MAN1 … #define SMA1303_A3_TOP_MAN2 … #define SMA1303_A4_TOP_MAN3 … #define SMA1303_A5_TDM1 … #define SMA1303_A6_TDM2 … #define SMA1303_A7_CLK_MON … /* 0xA8 ~ 0xF9 : Reserved */ #define SMA1303_FA_STATUS1 … #define SMA1303_FB_STATUS2 … /* 0xFC ~ 0xFE : Reserved */ #define SMA1303_FF_DEVICE_INDEX … /* SMA1303 Registers Bit Fields */ /* SYSTEM_CTRL : 0x00 */ #define SMA1303_RESETBYI2C_MASK … #define SMA1303_RESETBYI2C_NORMAL … #define SMA1303_RESETBYI2C_RESET … #define SMA1303_POWER_MASK … #define SMA1303_POWER_OFF … #define SMA1303_POWER_ON … /* INTPUT CTRL1 : 0x01 */ #define SMA1303_CONTROLLER_DEVICE_MASK … #define SMA1303_DEVICE_MODE … #define SMA1303_CONTROLLER_MODE … #define SMA1303_I2S_MODE_MASK … #define SMA1303_STANDARD_I2S … #define SMA1303_LJ … #define SMA1303_RJ_16BIT … #define SMA1303_RJ_18BIT … #define SMA1303_RJ_20BIT … #define SMA1303_RJ_24BIT … #define SMA1303_LEFTPOL_MASK … #define SMA1303_LOW_FIRST_CH … #define SMA1303_HIGH_FIRST_CH … #define SMA1303_SCK_RISING_MASK … #define SMA1303_SCK_FALLING_EDGE … #define SMA1303_SCK_RISING_EDGE … /* INTPUT CTRL2 : 0x02 */ #define SMA1303_IMODE_MASK … #define SMA1303_I2S … #define SMA1303_PCM_SHORT … #define SMA1303_PCM_LONG … #define RSMA1303_IGHT_FIRST_MASK … #define SMA1303_LEFT_NORMAL … #define SMA1303_RIGHT_INVERTED … #define SMA1303_PCM_ALAW_MASK … #define SMA1303_PCM_U_DECODING … #define SMA1303_PCM_A_DECODING … #define SMA1303_PCM_COMP_MASK … #define SMA1303_PCM_LINEAR … #define SMA1303_PCM_COMPANDING … #define SMA1303_INPUTSEL_MASK … #define SMA1303_PCM_8KHZ … #define SMA1303_PCM_16KHZ … #define SMA1303_PCM_STEREO_MASK … #define SMA1303_PCM_MONO … #define SMA1303_PCM_STEREO … #define SMA1303_PCM_DL_MASK … #define SMA1303_PCM_8BIT … #define SMA1303_PCM_16BIT … /* INTPUT CTRL3 : 0x03 */ #define SMA1303_PCM_N_SLOT_MASK … #define SMA1303_PCM_N_SLOT1 … #define SMA1303_PCM_N_SLOT2 … #define SMA1303_PCM_N_SLOT3 … #define SMA1303_PCM_N_SLOT4 … #define SMA1303_PCM_N_SLOT5 … #define SMA1303_PCM_N_SLOT6 … #define SMA1303_PCM_N_SLOT7 … #define SMA1303_PCM_N_SLOT8 … #define SMA1303_PCM_N_SLOT9 … #define SMA1303_PCM_N_SLOT10 … #define SMA1303_PCM_N_SLOT11 … #define SMA1303_PCM_N_SLOT12 … #define SMA1303_PCM_N_SLOT13 … #define SMA1303_PCM_N_SLOT14 … #define SMA1303_PCM_N_SLOT15 … #define SMA1303_PCM_N_SLOT16 … /* INTPUT CTRL4 : 0x04 */ #define SMA1303_PCM1_SLOT_MASK … #define SMA1303_PCM1_SLOT1 … #define SMA1303_PCM1_SLOT2 … #define SMA1303_PCM1_SLOT3 … #define SMA1303_PCM1_SLOT4 … #define SMA1303_PCM1_SLOT5 … #define SMA1303_PCM1_SLOT6 … #define SMA1303_PCM1_SLOT7 … #define SMA1303_PCM1_SLOT8 … #define SMA1303_PCM1_SLOT9 … #define SMA1303_PCM1_SLOT10 … #define SMA1303_PCM1_SLOT11 … #define SMA1303_PCM1_SLOT12 … #define SMA1303_PCM1_SLOT13 … #define SMA1303_PCM1_SLOT14 … #define SMA1303_PCM1_SLOT15 … #define SMA1303_PCM1_SLOT16 … #define SMA1303_PCM2_SLOT_MASK … #define SMA1303_PCM2_SLOT1 … #define SMA1303_PCM2_SLOT2 … #define SMA1303_PCM2_SLOT3 … #define SMA1303_PCM2_SLOT4 … #define SMA1303_PCM2_SLOT5 … #define SMA1303_PCM2_SLOT6 … #define SMA1303_PCM2_SLOT7 … #define SMA1303_PCM2_SLOT8 … #define SMA1303_PCM2_SLOT9 … #define SMA1303_PCM2_SLOT10 … #define SMA1303_PCM2_SLOT11 … #define SMA1303_PCM2_SLOT12 … #define SMA1303_PCM2_SLOT13 … #define SMA1303_PCM2_SLOT14 … #define SMA1303_PCM2_SLOT15 … #define SMA1303_PCM2_SLOT16 … /* OUTPUT CTRL : 0x09 */ #define SMA1303_PORT_CONFIG_MASK … #define SMA1303_INPUT_PORT_ONLY … #define SMA1303_OUTPUT_PORT_ENABLE … #define SMA1303_PORT_OUT_SEL_MASK … #define SMA1303_OUT_SEL_DISABLE … #define SMA1303_FORMAT_CONVERTER … #define SMA1303_MIXER_OUTPUT … #define SMA1303_SPEAKER_PATH … #define SMA1303_POSTSCALER_OUTPUT … /* BST_TEST : 0x0B */ #define SMA1303_BST_OFF_SLOPE_MASK … #define SMA1303_BST_OFF_SLOPE_6_7ns … #define SMA1303_BST_OFF_SLOPE_4_8ns … #define SMA1303_BST_OFF_SLOPE_2_6ns … #define SMA1303_BST_OFF_SLOPE_1_2ns … #define SMA1303_OCP_TEST_MASK … #define SMA1303_OCP_NORMAL_MODE … #define SMA1303_OCP_TEST_MODE … #define SMA1303_BST_FAST_LEBN_MASK … #define SMA1303_BST_SHORT_LEB … #define SMA1303_BST_LONG_LEB … #define SMA1303_HIGH_PGAIN_MASK … #define SMA1303_NORMAL_P_GAIN … #define SMA1303_HIGH_P_GAIN … #define SMA1303_VCOMP_MASK … #define SMA1303_VCOMP_NORMAL_MODE … #define SMA1303_VCOMP_V_MON_MODE … #define SMA1303_PMOS_ON_MASK … #define SMA1303_PMOS_NORMAL_MODE … #define SMA1303_PMOS_TEST_MODE … #define SMA1303_NMOS_ON_MASK … #define SMA1303_NMOS_NORMAL_MODE … #define SMA1303_NMOS_TEST_MODE … /* BST_TEST1 : 0x0C */ #define SMA1303_SET_OCP_H_MASK … #define SMA1303_HIGH_OCP_4_5_LVL … #define SMA1303_HIGH_OCP_3_2_LVL … #define SMA1303_HIGH_OCP_2_1_LVL … #define SMA1303_HIGH_OCP_0_9_LVL … #define SMA1303_OCL_TEST_MASK … #define SMA1303_OCL_NORMAL_MODE … #define SMA1303_OCL_TEST_MODE … #define SMA1303_LOOP_CHECK_MASK … #define SMA1303_BST_LOOP_NORMAL_MODE … #define SMA1303_BST_LOOP_CHECK_MODE … #define SMA1303_EN_SH_PRT_MASK … #define SMA1303_EN_SH_PRT_DISABLE … #define SMA1303_EN_SH_PRT_ENABLE … /* SPK_TEST : 0x0D */ #define SMA1303_VREF_MON_MASK … #define SMA1303_VREF_NORMAL_MODE … #define SMA1303_VREF_V_MON_MODE … #define SMA1303_SPK_OCP_DLYN_MASK … #define SMA1303_SPK_OCP_LONG_DELAY … #define SMA1303_SPK_OCP_NORMAL … #define SMA1303_SPK_OFF_SLOPE_MASK … #define SMA1303_SPK_OFF_SLOPE_SLOW … #define SMA1303_SPK_OFF_SLOPE_FAST … /* MUTE_VOL_CTRL : 0x0E */ #define SMA1303_VOL_SLOPE_MASK … #define SMA1303_VOL_SLOPE_OFF … #define SMA1303_VOL_SLOPE_SLOW … #define SMA1303_VOL_SLOPE_MID … #define SMA1303_VOL_SLOPE_FAST … #define SMA1303_MUTE_SLOPE_MASK … #define SMA1303_MUTE_SLOPE_OFF … #define SMA1303_MUTE_SLOPE_SLOW … #define SMA1303_MUTE_SLOPE_MID … #define SMA1303_MUTE_SLOPE_FAST … #define SMA1303_SPK_MUTE_MASK … #define SMA1303_SPK_UNMUTE … #define SMA1303_SPK_MUTE … /* SYSTEM_CTRL1 :0x10 */ #define SMA1303_SPK_MODE_MASK … #define SMA1303_SPK_OFF … #define SMA1303_SPK_MONO … #define SMA1303_SPK_STEREO … /* SYSTEM_CTRL2 : 0x11 */ #define SMA1303_SPK_BS_MASK … #define SMA1303_SPK_BS_BYP … #define SMA1303_SPK_BS_EN … #define SMA1303_SPK_LIM_MASK … #define SMA1303_SPK_LIM_BYP … #define SMA1303_SPK_LIM_EN … #define SMA1303_LR_DATA_SW_MASK … #define SMA1303_LR_DATA_SW_NORMAL … #define SMA1303_LR_DATA_SW_SWAP … #define SMA1303_MONOMIX_MASK … #define SMA1303_MONOMIX_OFF … #define SMA1303_MONOMIX_ON … /* SYSTEM_CTRL3 : 0x12 */ #define SMA1303_INPUT_MASK … #define SMA1303_INPUT_0_DB … #define SMA1303_INPUT_M6_DB … #define SMA1303_INPUT_M12_DB … #define SMA1303_INPUT_INFI_DB … #define SMA1303_INPUT_R_MASK … #define SMA1303_INPUT_R_0_DB … #define SMA1303_INPUT_R_M6_DB … #define SMA1303_INPUT_R_M12_DB … #define SMA1303_INPUT_R_INFI_DB … /* Modulator : 0x14 */ #define SMA1303_SPK_HYSFB_MASK … #define SMA1303_HYSFB_625K … #define SMA1303_HYSFB_414K … #define SMA1303_HYSFB_297K … #define SMA1303_HYSFB_226K … #define SMA1303_SPK_BDELAY_MASK … /* SDM CONTROL : 0x33 */ #define SMA1303_SDM_Q_SEL_MASK … #define SMA1303_QUART_SEL_1_DIV_4 … #define SMA1303_QUART_SEL_1_DIV_8 … /* OTP_DATA1 : 0x34 */ #define SMA1303_OTP_LVL_MASK … #define SMA1303_OTP_LVL_NORMAL … #define SMA1303_OTP_LVL_LOW … /* PROTECTION : 0x36 */ #define SMA1303_EDGE_DIS_MASK … #define SMA1303_EDGE_DIS_ENABLE … #define SMA1303_EDGE_DIS_DISABLE … #define SMA1303_SPK_OCP_DIS_MASK … #define SMA1303_SPK_OCP_ENABLE … #define SMA1303_SPK_OCP_DISABLE … #define SMA1303_OCP_MODE_MASK … #define SMA1303_AUTO_RECOVER … #define SMA1303_SHUT_DOWN_PERMANENT … #define SMA1303_OTP_MODE_MASK … #define SMA1303_OTP_MODE_DISABLE … #define SMA1303_IG_THR1_SHUT_THR2 … #define SMA1303_REC_THR1_SHUT_THR2 … #define SMA1303_SHUT_THR1_SHUT_THR2 … /* TEST2 : 0x3C */ #define SMA1303_SPK_HSDM_BP_MASK … #define SMA1303_SPK_HSDM_ENABLE … #define SMA1303_SPK_HSDM_BYPASS … #define SMA1303_SDM_SYNC_DIS_MASK … #define SMA1303_SDM_SYNC_NORMAL … #define SMA1303_SDM_SYNC_DISABLE … /* ATEST2 : 0x3F */ #define SMA1303_SPK_OUT_FREQ_MASK … #define SMA1303_SPK_OUT_FREQ_360K … #define SMA1303_SPK_OUT_FREQ_410K … #define SMA1303_LOW_POWER_MODE_MASK … #define SMA1303_LOW_POWER_MODE_DISABLE … #define SMA1303_LOW_POWER_MODE_ENABLE … #define SMA1303_THERMAL_ADJUST_MASK … #define SMA1303_THERMAL_150_110 … #define SMA1303_THERMAL_160_120 … #define SMA1303_THERMAL_140_100 … #define SMA1303_FAST_OFF_DRIVE_SPK_MASK … #define SMA1303_FAST_OFF_DRIVE_SPK_DISABLE … #define SMA1303_FAST_OFF_DRIVE_SPK_ENABLE … /* PLL_CTRL : 0x8E */ #define SMA1303_TRM_LVL_MASK … #define SMA1303_TRM_LVL_NORMAL … #define SMA1303_TRM_LVL_LOW … #define SMA1303_LOW_OCL_MODE_MASK … #define SMA1303_LOW_OCL_MODE … #define SMA1303_NORMAL_OCL_MODE … #define SMA1303_PLL_PD2_MASK … #define SMA1303_PLL_PD2 … #define SMA1303_PLL_OPERATION2 … /* POSTSCALER : 0x90 */ #define SMA1303_BYP_POST_MASK … #define SMA1303_EN_POST_SCALER … #define SMA1303_BYP_POST_SCALER … /* FDPEC CONTROL : 0x92 */ #define SMA1303_FLT_VDD_GAIN_MASK … #define SMA1303_FLT_VDD_GAIN_2P40 … #define SMA1303_FLT_VDD_GAIN_2P45 … #define SMA1303_FLT_VDD_GAIN_2P50 … #define SMA1303_FLT_VDD_GAIN_2P55 … #define SMA1303_FLT_VDD_GAIN_2P60 … #define SMA1303_FLT_VDD_GAIN_2P65 … #define SMA1303_FLT_VDD_GAIN_2P70 … #define SMA1303_FLT_VDD_GAIN_2P75 … #define SMA1303_FLT_VDD_GAIN_2P80 … #define SMA1303_FLT_VDD_GAIN_2P85 … #define SMA1303_FLT_VDD_GAIN_2P90 … #define SMA1303_FLT_VDD_GAIN_2P95 … #define SMA1303_FLT_VDD_GAIN_3P00 … #define SMA1303_FLT_VDD_GAIN_3P05 … #define SMA1303_FLT_VDD_GAIN_3P10 … #define SMA1303_FLT_VDD_GAIN_3P15 … #define SMA1303_DIS_FCHG_MASK … #define SMA1303_EN_FAST_CHARGE … #define SMA1303_DIS_FAST_CHARGE … /* BOOST_CONTROL4 : 0x97 */ #define SMA1303_TRM_VBST_MASK … #define SMA1303_TRM_VBST_5P5 … #define SMA1303_TRM_VBST_5P6 … #define SMA1303_TRM_VBST_5P7 … #define SMA1303_TRM_VBST_5P8 … #define SMA1303_TRM_VBST_5P9 … #define SMA1303_TRM_VBST_6P0 … #define SMA1303_TRM_VBST_6P1 … #define SMA1303_TRM_VBST_6P2 … /* TOP_MAN1 : 0xA2 */ #define SMA1303_PLL_LOCK_SKIP_MASK … #define SMA1303_PLL_LOCK_ENABLE … #define SMA1303_PLL_LOCK_DISABLE … #define SMA1303_PLL_PD_MASK … #define SMA1303_PLL_OPERATION … #define SMA1303_PLL_PD … #define SMA1303_PLL_DIV_MASK … #define SMA1303_PLL_OUT … #define SMA1303_PLL_OUT_2 … #define SMA1303_PLL_OUT_4 … #define SMA1303_PLL_OUT_8 … #define SMA1303_PLL_REF_CLK_MASK … #define SMA1303_PLL_REF_CLK1 … #define SMA1303_PLL_SCK … #define SMA1303_DAC_DN_CONV_MASK … #define SMA1303_DAC_DN_CONV_DISABLE … #define SMA1303_DAC_DN_CONV_ENABLE … #define SMA1303_SDO_IO_MASK … #define SMA1303_HIGH_Z_LRCK_H … #define SMA1303_HIGH_Z_LRCK_L … #define SMA1303_SDO_OUTPUT2_MASK … #define SMA1303_SDO_NORMAL … #define SMA1303_SDO_OUTPUT_ONLY … /* TOP_MAN2 : 0xA3 */ #define SMA1303_MON_OSC_PLL_MASK … #define SMA1303_PLL_SDO … #define SMA1303_OSC_SDO … #define SMA1303_TEST_CLKO_EN_MASK … #define SMA1303_NORMAL_SDO … #define SMA1303_CLK_OUT_SDO … #define SMA1303_SDO_OUTPUT_MASK … #define SMA1303_NORMAL_OUT … #define SMA1303_HIGH_Z_OUT … #define SMA1303_CLOCK_MON_MASK … #define SMA1303_CLOCK_MON … #define SMA1303_CLOCK_NOT_MON … #define SMA1303_OSC_PD_MASK … #define SMA1303_NORMAL_OPERATION_OSC … #define SMA1303_POWER_DOWN_OSC … /* TOP_MAN3 0xA4 */ #define SMA1303_O_FORMAT_MASK … #define SMA1303_O_FMT_LJ … #define SMA1303_O_FMT_I2S … #define SMA1303_O_FMT_TDM … #define SMA1303_SCK_RATE_MASK … #define SMA1303_SCK_64FS … #define SMA1303_SCK_32FS … #define SMA1303_LRCK_POL_MASK … #define SMA1303_L_VALID … #define SMA1303_R_VALID … /* TDM1 FORMAT : 0xA5 */ #define SMA1303_TDM_CLK_POL_MASK … #define SMA1303_TDM_CLK_POL_RISE … #define SMA1303_TDM_CLK_POL_FALL … #define SMA1303_TDM_TX_MODE_MASK … #define SMA1303_TDM_TX_MONO … #define SMA1303_TDM_TX_STEREO … #define SMA1303_TDM_SLOT1_RX_POS_MASK … #define SMA1303_TDM_SLOT1_RX_POS_0 … #define SMA1303_TDM_SLOT1_RX_POS_1 … #define SMA1303_TDM_SLOT1_RX_POS_2 … #define SMA1303_TDM_SLOT1_RX_POS_3 … #define SMA1303_TDM_SLOT1_RX_POS_4 … #define SMA1303_TDM_SLOT1_RX_POS_5 … #define SMA1303_TDM_SLOT1_RX_POS_6 … #define SMA1303_TDM_SLOT1_RX_POS_7 … #define SMA1303_TDM_SLOT2_RX_POS_MASK … #define SMA1303_TDM_SLOT2_RX_POS_0 … #define SMA1303_TDM_SLOT2_RX_POS_1 … #define SMA1303_TDM_SLOT2_RX_POS_2 … #define SMA1303_TDM_SLOT2_RX_POS_3 … #define SMA1303_TDM_SLOT2_RX_POS_4 … #define SMA1303_TDM_SLOT2_RX_POS_5 … #define SMA1303_TDM_SLOT2_RX_POS_6 … #define SMA1303_TDM_SLOT2_RX_POS_7 … /* TDM2 FORMAT : 0xA6 */ #define SMA1303_TDM_DL_MASK … #define SMA1303_TDM_DL_16 … #define SMA1303_TDM_DL_32 … #define SMA1303_TDM_N_SLOT_MASK … #define SMA1303_TDM_N_SLOT_4 … #define SMA1303_TDM_N_SLOT_8 … #define SMA1303_TDM_SLOT1_TX_POS_MASK … #define SMA1303_TDM_SLOT1_TX_POS_0 … #define SMA1303_TDM_SLOT1_TX_POS_1 … #define SMA1303_TDM_SLOT1_TX_POS_2 … #define SMA1303_TDM_SLOT1_TX_POS_3 … #define SMA1303_TDM_SLOT1_TX_POS_4 … #define SMA1303_TDM_SLOT1_TX_POS_5 … #define SMA1303_TDM_SLOT1_TX_POS_6 … #define SMA1303_TDM_SLOT1_TX_POS_7 … #define SMA1303_TDM_SLOT2_TX_POS_MASK … #define SMA1303_TDM_SLOT2_TX_POS_0 … #define SMA1303_TDM_SLOT2_TX_POS_1 … #define SMA1303_TDM_SLOT2_TX_POS_2 … #define SMA1303_TDM_SLOT2_TX_POS_3 … #define SMA1303_TDM_SLOT2_TX_POS_4 … #define SMA1303_TDM_SLOT2_TX_POS_5 … #define SMA1303_TDM_SLOT2_TX_POS_6 … #define SMA1303_TDM_SLOT2_TX_POS_7 … /* STATUS1 : 0xFA */ #define SMA1303_OT1_OK_STATUS … #define SMA1303_OT2_OK_STATUS … /* STATUS2 : 0xFB */ #define SMA1303_OCP_SPK_STATUS … #define SMA1303_OCP_BST_STATUS … #define SMA1303_OTP_STAT_OK_0 … #define SMA1303_OTP_STAT_OK_1 … #define SMA1303_CLK_MON_STATUS … /* DEVICE_INFO : 0xFF */ #define SMA1303_DEVICE_ID … #define SMA1303_UVLO_BST_STATUS … #define SMA1303_REV_NUM_STATUS … #define SMA1303_REV_NUM_TV0 … #define SMA1303_REV_NUM_TV1 … #endif
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