// SPDX-License-Identifier: GPL-2.0 // // src4xxx.h -- SRC4XXX ALSA SoC audio driver // // Copyright 2021-2022 Deqx Pty Ltd // Author: Matt R Flax <[email protected]> #ifndef __SRC4XXX_H__ #define __SRC4XXX_H__ #define SRC4XXX_RES_00 … #define SRC4XXX_PWR_RST_01 … #define SRC4XXX_RESET … #define SRC4XXX_POWER_DOWN … #define SRC4XXX_POWER_ENABLE … #define SRC4XXX_ENABLE_SRC … #define SRC4XXX_ENABLE_SRC_SHIFT … #define SRC4XXX_ENABLE_DIR … #define SRC4XXX_ENABLE_DIR_SHIFT … #define SRC4XXX_ENABLE_DIT … #define SRC4XXX_ENABLE_DIT_SHIFT … #define SRC4XXX_ENABLE_PORT_B … #define SRC4XXX_ENABLE_PORT_B_SHIFT … #define SRC4XXX_ENABLE_PORT_A … #define SRC4XXX_ENABLE_PORT_A_SHIFT … #define SRC4XXX_PORTA_CTL_03 … #define SRC4XXX_BUS_MASTER … #define SRC4XXX_BUS_LEFT_J … #define SRC4XXX_BUS_I2S … #define SRC4XXX_BUS_RIGHT_J_16 … #define SRC4XXX_BUS_RIGHT_J_18 … #define SRC4XXX_BUS_RIGHT_J_20 … #define SRC4XXX_BUS_RIGHT_J_24 … #define SRC4XXX_BUS_FMT_MS_MASK … #define SRC4XXX_PORTA_CTL_04 … #define SRC4XXX_MCLK_DIV_MASK … #define SRC4XXX_BUS_FMT(id) … #define SRC4XXX_BUS_CLK(id) … #define SRC4XXX_PORTB_CTL_05 … #define SRC4XXX_PORTB_CTL_06 … #define SRC4XXX_TX_CTL_07 … #define SRC4XXX_TX_MCLK_DIV_MASK … #define SRC4XXX_TX_MCLK_DIV_SHIFT … #define SRC4XXX_TX_CTL_08 … #define SRC4XXX_TX_CTL_09 … #define SRC4XXX_SRC_DIT_IRQ_MSK_0B … #define SRC4XXX_SRC_BTI_EN … #define SRC4XXX_SRC_TSLIP_EN … #define SRC4XXX_SRC_DIT_IRQ_MODE_0C … #define SRC4XXX_RCV_CTL_0D … #define SRC4XXX_RXCLK_RXCKI … #define SRC4XXX_RXCLK_MCLK … #define SRC4XXX_RCV_CTL_0E … #define SRC4XXX_REC_MCLK_EN … #define SRC4XXX_PLL2_DIV_0 … #define SRC4XXX_PLL2_DIV_2 … #define SRC4XXX_PLL2_DIV_4 … #define SRC4XXX_PLL2_DIV_8 … #define SRC4XXX_PLL2_LOL … #define SRC4XXX_RCV_PLL_0F … #define SRC4XXX_RCV_PLL_10 … #define SRC4XXX_RCV_PLL_11 … #define SRC4XXX_RVC_IRQ_MSK_16 … #define SRC4XXX_RVC_IRQ_MSK_17 … #define SRC4XXX_RVC_IRQ_MODE_18 … #define SRC4XXX_RVC_IRQ_MODE_19 … #define SRC4XXX_RVC_IRQ_MODE_1A … #define SRC4XXX_GPIO_1_1B … #define SRC4XXX_GPIO_2_1C … #define SRC4XXX_GPIO_3_1D … #define SRC4XXX_GPIO_4_1E … #define SRC4XXX_SCR_CTL_2D … #define SRC4XXX_SCR_CTL_2E … #define SRC4XXX_SCR_CTL_2F … #define SRC4XXX_SCR_CTL_30 … #define SRC4XXX_SCR_CTL_31 … #define SRC4XXX_PAGE_SEL_7F … // read only registers #define SRC4XXX_GLOBAL_ITR_STS_02 … #define SRC4XXX_SRC_DIT_STS_0A … #define SRC4XXX_NON_AUDIO_D_12 … #define SRC4XXX_RVC_STS_13 … #define SRC4XXX_RVC_STS_14 … #define SRC4XXX_RVC_STS_15 … #define SRC4XXX_SUB_CODE_1F … #define SRC4XXX_SUB_CODE_20 … #define SRC4XXX_SUB_CODE_21 … #define SRC4XXX_SUB_CODE_22 … #define SRC4XXX_SUB_CODE_23 … #define SRC4XXX_SUB_CODE_24 … #define SRC4XXX_SUB_CODE_25 … #define SRC4XXX_SUB_CODE_26 … #define SRC4XXX_SUB_CODE_27 … #define SRC4XXX_SUB_CODE_28 … #define SRC4XXX_PC_PREAMBLE_HI_29 … #define SRC4XXX_PC_PREAMBLE_LO_2A … #define SRC4XXX_PD_PREAMBLE_HI_2B … #define SRC4XXX_PC_PREAMBLE_LO_2C … #define SRC4XXX_IO_RATIO_32 … #define SRC4XXX_IO_RATIO_33 … int src4xxx_probe(struct device *dev, struct regmap *regmap, void (*switch_mode)(struct device *dev)); extern const struct regmap_config src4xxx_regmap_config; #endif /* __SRC4XXX_H__ */
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