#ifndef _TLV320AIC26_H_
#define _TLV320AIC26_H_
#define AIC26_PAGE_ADDR(page, offset) …
#define AIC26_REG_BAT1 …
#define AIC26_REG_BAT2 …
#define AIC26_REG_AUX …
#define AIC26_REG_TEMP1 …
#define AIC26_REG_TEMP2 …
#define AIC26_REG_AUX_ADC …
#define AIC26_REG_STATUS …
#define AIC26_REG_REFERENCE …
#define AIC26_REG_RESET …
#define AIC26_REG_AUDIO_CTRL1 …
#define AIC26_REG_ADC_GAIN …
#define AIC26_REG_DAC_GAIN …
#define AIC26_REG_SIDETONE …
#define AIC26_REG_AUDIO_CTRL2 …
#define AIC26_REG_POWER_CTRL …
#define AIC26_REG_AUDIO_CTRL3 …
#define AIC26_REG_FILTER_COEFF_L_N0 …
#define AIC26_REG_FILTER_COEFF_L_N1 …
#define AIC26_REG_FILTER_COEFF_L_N2 …
#define AIC26_REG_FILTER_COEFF_L_N3 …
#define AIC26_REG_FILTER_COEFF_L_N4 …
#define AIC26_REG_FILTER_COEFF_L_N5 …
#define AIC26_REG_FILTER_COEFF_L_D1 …
#define AIC26_REG_FILTER_COEFF_L_D2 …
#define AIC26_REG_FILTER_COEFF_L_D4 …
#define AIC26_REG_FILTER_COEFF_L_D5 …
#define AIC26_REG_FILTER_COEFF_R_N0 …
#define AIC26_REG_FILTER_COEFF_R_N1 …
#define AIC26_REG_FILTER_COEFF_R_N2 …
#define AIC26_REG_FILTER_COEFF_R_N3 …
#define AIC26_REG_FILTER_COEFF_R_N4 …
#define AIC26_REG_FILTER_COEFF_R_N5 …
#define AIC26_REG_FILTER_COEFF_R_D1 …
#define AIC26_REG_FILTER_COEFF_R_D2 …
#define AIC26_REG_FILTER_COEFF_R_D4 …
#define AIC26_REG_FILTER_COEFF_R_D5 …
#define AIC26_REG_PLL_PROG1 …
#define AIC26_REG_PLL_PROG2 …
#define AIC26_REG_AUDIO_CTRL4 …
#define AIC26_REG_AUDIO_CTRL5 …
enum aic26_divisors { … };
enum aic26_datfm { … };
enum aic26_wlen { … };
#endif