/* SPDX-License-Identifier: GPL-2.0-only */ /* * tlv320aic32x4.h */ #ifndef _TLV320AIC32X4_H #define _TLV320AIC32X4_H struct device; struct regmap_config; enum aic32x4_type { … }; extern const struct regmap_config aic32x4_regmap_config; int aic32x4_probe(struct device *dev, struct regmap *regmap, enum aic32x4_type type); void aic32x4_remove(struct device *dev); int aic32x4_register_clocks(struct device *dev, const char *mclk_name); /* tlv320aic32x4 register space (in decimal to match datasheet) */ #define AIC32X4_REG(page, reg) … #define AIC32X4_PSEL … #define AIC32X4_RESET … #define AIC32X4_CLKMUX … #define AIC32X4_PLLPR … #define AIC32X4_PLLJ … #define AIC32X4_PLLDMSB … #define AIC32X4_PLLDLSB … #define AIC32X4_NDAC … #define AIC32X4_MDAC … #define AIC32X4_DOSRMSB … #define AIC32X4_DOSRLSB … #define AIC32X4_NADC … #define AIC32X4_MADC … #define AIC32X4_AOSR … #define AIC32X4_CLKMUX2 … #define AIC32X4_CLKOUTM … #define AIC32X4_IFACE1 … #define AIC32X4_IFACE2 … #define AIC32X4_IFACE3 … #define AIC32X4_BCLKN … #define AIC32X4_IFACE4 … #define AIC32X4_IFACE5 … #define AIC32X4_IFACE6 … #define AIC32X4_GPIOCTL … #define AIC32X4_DOUTCTL … #define AIC32X4_DINCTL … #define AIC32X4_MISOCTL … #define AIC32X4_SCLKCTL … #define AIC32X4_DACSPB … #define AIC32X4_ADCSPB … #define AIC32X4_DACSETUP … #define AIC32X4_DACMUTE … #define AIC32X4_LDACVOL … #define AIC32X4_RDACVOL … #define AIC32X4_ADCSETUP … #define AIC32X4_ADCFGA … #define AIC32X4_LADCVOL … #define AIC32X4_RADCVOL … #define AIC32X4_LAGC1 … #define AIC32X4_LAGC2 … #define AIC32X4_LAGC3 … #define AIC32X4_LAGC4 … #define AIC32X4_LAGC5 … #define AIC32X4_LAGC6 … #define AIC32X4_LAGC7 … #define AIC32X4_RAGC1 … #define AIC32X4_RAGC2 … #define AIC32X4_RAGC3 … #define AIC32X4_RAGC4 … #define AIC32X4_RAGC5 … #define AIC32X4_RAGC6 … #define AIC32X4_RAGC7 … #define AIC32X4_PWRCFG … #define AIC32X4_LDOCTL … #define AIC32X4_LPLAYBACK … #define AIC32X4_RPLAYBACK … #define AIC32X4_OUTPWRCTL … #define AIC32X4_CMMODE … #define AIC32X4_HPLROUTE … #define AIC32X4_HPRROUTE … #define AIC32X4_LOLROUTE … #define AIC32X4_LORROUTE … #define AIC32X4_HPLGAIN … #define AIC32X4_HPRGAIN … #define AIC32X4_LOLGAIN … #define AIC32X4_LORGAIN … #define AIC32X4_HEADSTART … #define TAS2505_SPK … #define TAS2505_SPKVOL1 … #define TAS2505_SPKVOL2 … #define AIC32X4_MICBIAS … #define AIC32X4_LMICPGAPIN … #define AIC32X4_LMICPGANIN … #define AIC32X4_RMICPGAPIN … #define AIC32X4_RMICPGANIN … #define AIC32X4_FLOATINGINPUT … #define AIC32X4_LMICPGAVOL … #define AIC32X4_RMICPGAVOL … #define TAS2505_REFPOWERUP … #define AIC32X4_REFPOWERUP … /* Bits, masks, and shifts */ /* AIC32X4_CLKMUX */ #define AIC32X4_PLL_CLKIN_MASK … #define AIC32X4_PLL_CLKIN_SHIFT … #define AIC32X4_PLL_CLKIN_MCLK … #define AIC32X4_PLL_CLKIN_BCKL … #define AIC32X4_PLL_CLKIN_GPIO1 … #define AIC32X4_PLL_CLKIN_DIN … #define AIC32X4_CODEC_CLKIN_MASK … #define AIC32X4_CODEC_CLKIN_SHIFT … #define AIC32X4_CODEC_CLKIN_MCLK … #define AIC32X4_CODEC_CLKIN_BCLK … #define AIC32X4_CODEC_CLKIN_GPIO1 … #define AIC32X4_CODEC_CLKIN_PLL … /* AIC32X4_PLLPR */ #define AIC32X4_PLLEN … #define AIC32X4_PLL_P_MASK … #define AIC32X4_PLL_P_SHIFT … #define AIC32X4_PLL_R_MASK … /* AIC32X4_NDAC */ #define AIC32X4_NDACEN … #define AIC32X4_NDAC_MASK … /* AIC32X4_MDAC */ #define AIC32X4_MDACEN … #define AIC32X4_MDAC_MASK … /* AIC32X4_NADC */ #define AIC32X4_NADCEN … #define AIC32X4_NADC_MASK … /* AIC32X4_MADC */ #define AIC32X4_MADCEN … #define AIC32X4_MADC_MASK … /* AIC32X4_BCLKN */ #define AIC32X4_BCLKEN … #define AIC32X4_BCLK_MASK … /* AIC32X4_IFACE1 */ #define AIC32X4_IFACE1_DATATYPE_MASK … #define AIC32X4_IFACE1_DATATYPE_SHIFT … #define AIC32X4_I2S_MODE … #define AIC32X4_DSP_MODE … #define AIC32X4_RIGHT_JUSTIFIED_MODE … #define AIC32X4_LEFT_JUSTIFIED_MODE … #define AIC32X4_IFACE1_DATALEN_MASK … #define AIC32X4_IFACE1_DATALEN_SHIFT … #define AIC32X4_WORD_LEN_16BITS … #define AIC32X4_WORD_LEN_20BITS … #define AIC32X4_WORD_LEN_24BITS … #define AIC32X4_WORD_LEN_32BITS … #define AIC32X4_IFACE1_MASTER_MASK … #define AIC32X4_BCLKMASTER … #define AIC32X4_WCLKMASTER … /* AIC32X4_IFACE2 */ #define AIC32X4_DATA_OFFSET_MASK … /* AIC32X4_IFACE3 */ #define AIC32X4_BCLKINV_MASK … #define AIC32X4_BDIVCLK_MASK … #define AIC32X4_BDIVCLK_SHIFT … #define AIC32X4_DAC2BCLK … #define AIC32X4_DACMOD2BCLK … #define AIC32X4_ADC2BCLK … #define AIC32X4_ADCMOD2BCLK … /* AIC32X4_DACSETUP */ #define AIC32X4_DAC_CHAN_MASK … #define AIC32X4_LDAC2RCHN … #define AIC32X4_LDAC2LCHN … #define AIC32X4_RDAC2LCHN … #define AIC32X4_RDAC2RCHN … /* AIC32X4_DACMUTE */ #define AIC32X4_MUTEON … /* AIC32X4_ADCSETUP */ #define AIC32X4_LADC_EN … #define AIC32X4_RADC_EN … /* AIC32X4_PWRCFG */ #define AIC32X4_AVDDWEAKDISABLE … /* AIC32X4_LDOCTL */ #define AIC32X4_LDOCTLEN … /* AIC32X4_CMMODE */ #define AIC32X4_LDOIN_18_36 … #define AIC32X4_LDOIN2HP … /* AIC32X4_MICBIAS */ #define AIC32X4_MICBIAS_LDOIN … #define AIC32X4_MICBIAS_2075V … #define AIC32x4_MICBIAS_MASK … /* AIC32X4_LMICPGANIN */ #define AIC32X4_LMICPGANIN_IN2R_10K … #define AIC32X4_LMICPGANIN_CM1L_10K … /* AIC32X4_RMICPGANIN */ #define AIC32X4_RMICPGANIN_IN1L_10K … #define AIC32X4_RMICPGANIN_CM1R_10K … /* AIC32X4_REFPOWERUP */ #define AIC32X4_REFPOWERUP_SLOW … #define AIC32X4_REFPOWERUP_40MS … #define AIC32X4_REFPOWERUP_80MS … #define AIC32X4_REFPOWERUP_120MS … /* Common mask and enable for all of the dividers */ #define AIC32X4_DIVEN … #define AIC32X4_DIV_MASK … #define AIC32X4_DIV_MAX … /* Clock Limits */ #define AIC32X4_MAX_DOSR_FREQ … #define AIC32X4_MIN_DOSR_FREQ … #define AIC32X4_MAX_CODEC_CLKIN_FREQ … #define AIC32X4_MAX_PLL_CLKIN … #endif /* _TLV320AIC32X4_H */
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