// SPDX-License-Identifier: GPL-2.0 /* * ALSA SoC TLV320AIC31xx CODEC Driver Definitions * * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _TLV320AIC31XX_H #define _TLV320AIC31XX_H #define AIC31XX_RATES … #define AIC31XX_FORMATS … #define AIC31XX_STEREO_CLASS_D_BIT … #define AIC31XX_MINIDSP_BIT … #define DAC31XX_BIT … #define AIC31XX_JACK_MASK … enum aic31xx_type { … }; struct aic31xx_pdata { … }; #define AIC31XX_REG(page, reg) … #define AIC31XX_PAGECTL … /* Page 0 Registers */ #define AIC31XX_RESET … #define AIC31XX_OT_FLAG … #define AIC31XX_CLKMUX … #define AIC31XX_PLLPR … #define AIC31XX_PLLJ … #define AIC31XX_PLLDMSB … #define AIC31XX_PLLDLSB … #define AIC31XX_NDAC … #define AIC31XX_MDAC … #define AIC31XX_DOSRMSB … #define AIC31XX_DOSRLSB … #define AIC31XX_MINI_DSP_INPOL … #define AIC31XX_NADC … #define AIC31XX_MADC … #define AIC31XX_AOSR … #define AIC31XX_CLKOUTMUX … #define AIC31XX_CLKOUTMVAL … #define AIC31XX_IFACE1 … #define AIC31XX_DATA_OFFSET … #define AIC31XX_IFACE2 … #define AIC31XX_BCLKN … #define AIC31XX_IFACESEC1 … #define AIC31XX_IFACESEC2 … #define AIC31XX_IFACESEC3 … #define AIC31XX_I2C … #define AIC31XX_ADCFLAG … #define AIC31XX_DACFLAG1 … #define AIC31XX_DACFLAG2 … #define AIC31XX_OFFLAG … #define AIC31XX_INTRDACFLAG … #define AIC31XX_INTRADCFLAG … #define AIC31XX_INTRDACFLAG2 … #define AIC31XX_INTRADCFLAG2 … #define AIC31XX_INT1CTRL … #define AIC31XX_INT2CTRL … #define AIC31XX_GPIO1 … #define AIC31XX_DACPRB … #define AIC31XX_ADCPRB … #define AIC31XX_DACSETUP … #define AIC31XX_DACMUTE … #define AIC31XX_LDACVOL … #define AIC31XX_RDACVOL … #define AIC31XX_HSDETECT … #define AIC31XX_ADCSETUP … #define AIC31XX_ADCFGA … #define AIC31XX_ADCVOL … /* Page 1 Registers */ #define AIC31XX_HPDRIVER … #define AIC31XX_SPKAMP … #define AIC31XX_HPPOP … #define AIC31XX_SPPGARAMP … #define AIC31XX_DACMIXERROUTE … #define AIC31XX_LANALOGHPL … #define AIC31XX_RANALOGHPR … #define AIC31XX_LANALOGSPL … #define AIC31XX_RANALOGSPR … #define AIC31XX_HPLGAIN … #define AIC31XX_HPRGAIN … #define AIC31XX_SPLGAIN … #define AIC31XX_SPRGAIN … #define AIC31XX_HPCONTROL … #define AIC31XX_MICBIAS … #define AIC31XX_MICPGA … #define AIC31XX_MICPGAPI … #define AIC31XX_MICPGAMI … #define AIC31XX_MICPGACM … /* Bits, masks, and shifts */ /* AIC31XX_CLKMUX */ #define AIC31XX_PLL_CLKIN_MASK … #define AIC31XX_PLL_CLKIN_SHIFT … #define AIC31XX_PLL_CLKIN_MCLK … #define AIC31XX_PLL_CLKIN_BCLK … #define AIC31XX_PLL_CLKIN_GPIO1 … #define AIC31XX_PLL_CLKIN_DIN … #define AIC31XX_CODEC_CLKIN_MASK … #define AIC31XX_CODEC_CLKIN_SHIFT … #define AIC31XX_CODEC_CLKIN_MCLK … #define AIC31XX_CODEC_CLKIN_BCLK … #define AIC31XX_CODEC_CLKIN_GPIO1 … #define AIC31XX_CODEC_CLKIN_PLL … /* AIC31XX_PLLPR */ /* AIC31XX_NDAC */ /* AIC31XX_MDAC */ /* AIC31XX_NADC */ /* AIC31XX_MADC */ /* AIC31XX_BCLKN */ #define AIC31XX_PLL_MASK … #define AIC31XX_PM_MASK … /* AIC31XX_IFACE1 */ #define AIC31XX_IFACE1_DATATYPE_MASK … #define AIC31XX_IFACE1_DATATYPE_SHIFT … #define AIC31XX_I2S_MODE … #define AIC31XX_DSP_MODE … #define AIC31XX_RIGHT_JUSTIFIED_MODE … #define AIC31XX_LEFT_JUSTIFIED_MODE … #define AIC31XX_IFACE1_DATALEN_MASK … #define AIC31XX_IFACE1_DATALEN_SHIFT … #define AIC31XX_WORD_LEN_16BITS … #define AIC31XX_WORD_LEN_20BITS … #define AIC31XX_WORD_LEN_24BITS … #define AIC31XX_WORD_LEN_32BITS … #define AIC31XX_IFACE1_MASTER_MASK … #define AIC31XX_BCLK_MASTER … #define AIC31XX_WCLK_MASTER … /* AIC31XX_DATA_OFFSET */ #define AIC31XX_DATA_OFFSET_MASK … /* AIC31XX_IFACE2 */ #define AIC31XX_BCLKINV_MASK … #define AIC31XX_BDIVCLK_MASK … #define AIC31XX_DAC2BCLK … #define AIC31XX_DACMOD2BCLK … #define AIC31XX_ADC2BCLK … #define AIC31XX_ADCMOD2BCLK … #define AIC31XX_KEEP_I2SCLK … /* AIC31XX_ADCFLAG */ #define AIC31XX_ADCPWRSTATUS_MASK … /* AIC31XX_DACFLAG1 */ #define AIC31XX_LDACPWRSTATUS_MASK … #define AIC31XX_HPLDRVPWRSTATUS_MASK … #define AIC31XX_SPLDRVPWRSTATUS_MASK … #define AIC31XX_RDACPWRSTATUS_MASK … #define AIC31XX_HPRDRVPWRSTATUS_MASK … #define AIC31XX_SPRDRVPWRSTATUS_MASK … /* AIC31XX_OFFLAG */ #define AIC31XX_DAC_OF_LEFT … #define AIC31XX_DAC_OF_RIGHT … #define AIC31XX_DAC_OF_SHIFTER … #define AIC31XX_ADC_OF … #define AIC31XX_ADC_OF_SHIFTER … /* AIC31XX_INTRDACFLAG */ #define AIC31XX_HPLSCDETECT … #define AIC31XX_HPRSCDETECT … #define AIC31XX_BUTTONPRESS … #define AIC31XX_HSPLUG … #define AIC31XX_LDRCTHRES … #define AIC31XX_RDRCTHRES … #define AIC31XX_DACSINT … #define AIC31XX_DACAINT … /* AIC31XX_INT1CTRL */ #define AIC31XX_HSPLUGDET … #define AIC31XX_BUTTONPRESSDET … #define AIC31XX_DRCTHRES … #define AIC31XX_AGCNOISE … #define AIC31XX_SC … #define AIC31XX_ENGINE … /* AIC31XX_GPIO1 */ #define AIC31XX_GPIO1_FUNC_MASK … #define AIC31XX_GPIO1_FUNC_SHIFT … #define AIC31XX_GPIO1_DISABLED … #define AIC31XX_GPIO1_INPUT … #define AIC31XX_GPIO1_GPI … #define AIC31XX_GPIO1_GPO … #define AIC31XX_GPIO1_CLKOUT … #define AIC31XX_GPIO1_INT1 … #define AIC31XX_GPIO1_INT2 … #define AIC31XX_GPIO1_ADC_WCLK … #define AIC31XX_GPIO1_SBCLK … #define AIC31XX_GPIO1_SWCLK … #define AIC31XX_GPIO1_ADC_MOD_CLK … #define AIC31XX_GPIO1_SDOUT … /* AIC31XX_DACMUTE */ #define AIC31XX_DACMUTE_MASK … /* AIC31XX_HSDETECT */ #define AIC31XX_HSD_ENABLE … #define AIC31XX_HSD_TYPE_MASK … #define AIC31XX_HSD_TYPE_SHIFT … #define AIC31XX_HSD_NONE … #define AIC31XX_HSD_HP … #define AIC31XX_HSD_HS … /* AIC31XX_HPDRIVER */ #define AIC31XX_HPD_OCMV_MASK … #define AIC31XX_HPD_OCMV_SHIFT … #define AIC31XX_HPD_OCMV_1_35V … #define AIC31XX_HPD_OCMV_1_5V … #define AIC31XX_HPD_OCMV_1_65V … #define AIC31XX_HPD_OCMV_1_8V … /* AIC31XX_MICBIAS */ #define AIC31XX_MICBIAS_MASK … #define AIC31XX_MICBIAS_SHIFT … #endif /* _TLV320AIC31XX_H */
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