/* SPDX-License-Identifier: GPL-2.0-only */ /* * ALSA SoC TLV320AIC3X codec driver * * Author: Vladimir Barinov, <[email protected]> * Copyright: (C) 2007 MontaVista Software, Inc., <[email protected]> */ #ifndef _AIC3X_H #define _AIC3X_H struct device; struct regmap_config; extern const struct regmap_config aic3x_regmap; int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data); void aic3x_remove(struct device *dev); #define AIC3X_MODEL_3X … #define AIC3X_MODEL_33 … #define AIC3X_MODEL_3007 … #define AIC3X_MODEL_3104 … #define AIC3X_MODEL_3106 … /* AIC3X register space */ #define AIC3X_CACHEREGNUM … /* Page select register */ #define AIC3X_PAGE_SELECT … /* Software reset register */ #define AIC3X_RESET … /* Codec Sample rate select register */ #define AIC3X_SAMPLE_RATE_SEL_REG … /* PLL progrramming register A */ #define AIC3X_PLL_PROGA_REG … /* PLL progrramming register B */ #define AIC3X_PLL_PROGB_REG … /* PLL progrramming register C */ #define AIC3X_PLL_PROGC_REG … /* PLL progrramming register D */ #define AIC3X_PLL_PROGD_REG … /* Codec datapath setup register */ #define AIC3X_CODEC_DATAPATH_REG … /* Audio serial data interface control register A */ #define AIC3X_ASD_INTF_CTRLA … /* Audio serial data interface control register B */ #define AIC3X_ASD_INTF_CTRLB … /* Audio serial data interface control register C */ #define AIC3X_ASD_INTF_CTRLC … /* Audio overflow status and PLL R value programming register */ #define AIC3X_OVRF_STATUS_AND_PLLR_REG … /* Audio codec digital filter control register */ #define AIC3X_CODEC_DFILT_CTRL … /* Headset/button press detection register */ #define AIC3X_HEADSET_DETECT_CTRL_A … #define AIC3X_HEADSET_DETECT_CTRL_B … /* ADC PGA Gain control registers */ #define LADC_VOL … #define RADC_VOL … /* MIC3 control registers */ #define MIC3LR_2_LADC_CTRL … #define MIC3LR_2_RADC_CTRL … /* Line1 Input control registers */ #define LINE1L_2_LADC_CTRL … #define LINE1R_2_LADC_CTRL … #define LINE1R_2_RADC_CTRL … #define LINE1L_2_RADC_CTRL … /* Line2 Input control registers */ #define LINE2L_2_LADC_CTRL … #define LINE2R_2_RADC_CTRL … /* MICBIAS Control Register */ #define MICBIAS_CTRL … /* AGC Control Registers A, B, C */ #define LAGC_CTRL_A … #define LAGC_CTRL_B … #define LAGC_CTRL_C … #define RAGC_CTRL_A … #define RAGC_CTRL_B … #define RAGC_CTRL_C … /* DAC Power and Left High Power Output control registers */ #define DAC_PWR … #define HPLCOM_CFG … /* Right High Power Output control registers */ #define HPRCOM_CFG … /* High Power Output Stage Control Register */ #define HPOUT_SC … /* DAC Output Switching control registers */ #define DAC_LINE_MUX … /* High Power Output Driver Pop Reduction registers */ #define HPOUT_POP_REDUCTION … /* DAC Digital control registers */ #define LDAC_VOL … #define RDAC_VOL … /* Left High Power Output control registers */ #define LINE2L_2_HPLOUT_VOL … #define PGAL_2_HPLOUT_VOL … #define DACL1_2_HPLOUT_VOL … #define LINE2R_2_HPLOUT_VOL … #define PGAR_2_HPLOUT_VOL … #define DACR1_2_HPLOUT_VOL … #define HPLOUT_CTRL … /* Left High Power COM control registers */ #define LINE2L_2_HPLCOM_VOL … #define PGAL_2_HPLCOM_VOL … #define DACL1_2_HPLCOM_VOL … #define LINE2R_2_HPLCOM_VOL … #define PGAR_2_HPLCOM_VOL … #define DACR1_2_HPLCOM_VOL … #define HPLCOM_CTRL … /* Right High Power Output control registers */ #define LINE2L_2_HPROUT_VOL … #define PGAL_2_HPROUT_VOL … #define DACL1_2_HPROUT_VOL … #define LINE2R_2_HPROUT_VOL … #define PGAR_2_HPROUT_VOL … #define DACR1_2_HPROUT_VOL … #define HPROUT_CTRL … /* Right High Power COM control registers */ #define LINE2L_2_HPRCOM_VOL … #define PGAL_2_HPRCOM_VOL … #define DACL1_2_HPRCOM_VOL … #define LINE2R_2_HPRCOM_VOL … #define PGAR_2_HPRCOM_VOL … #define DACR1_2_HPRCOM_VOL … #define HPRCOM_CTRL … /* Mono Line Output Plus/Minus control registers */ #define LINE2L_2_MONOLOPM_VOL … #define PGAL_2_MONOLOPM_VOL … #define DACL1_2_MONOLOPM_VOL … #define LINE2R_2_MONOLOPM_VOL … #define PGAR_2_MONOLOPM_VOL … #define DACR1_2_MONOLOPM_VOL … #define MONOLOPM_CTRL … /* Class-D speaker driver on tlv320aic3007 */ #define CLASSD_CTRL … /* Left Line Output Plus/Minus control registers */ #define LINE2L_2_LLOPM_VOL … #define PGAL_2_LLOPM_VOL … #define DACL1_2_LLOPM_VOL … #define LINE2R_2_LLOPM_VOL … #define PGAR_2_LLOPM_VOL … #define DACR1_2_LLOPM_VOL … #define LLOPM_CTRL … /* Right Line Output Plus/Minus control registers */ #define LINE2L_2_RLOPM_VOL … #define PGAL_2_RLOPM_VOL … #define DACL1_2_RLOPM_VOL … #define LINE2R_2_RLOPM_VOL … #define PGAR_2_RLOPM_VOL … #define DACR1_2_RLOPM_VOL … #define RLOPM_CTRL … /* GPIO/IRQ registers */ #define AIC3X_STICKY_IRQ_FLAGS_REG … #define AIC3X_RT_IRQ_FLAGS_REG … #define AIC3X_GPIO1_REG … #define AIC3X_GPIO2_REG … #define AIC3X_GPIOA_REG … #define AIC3X_GPIOB_REG … /* Clock generation control register */ #define AIC3X_CLKGEN_CTRL_REG … /* New AGC registers */ #define LAGCN_ATTACK … #define LAGCN_DECAY … #define RAGCN_ATTACK … #define RAGCN_DECAY … /* New Programmable ADC Digital Path and I2C Bus Condition Register */ #define NEW_ADC_DIGITALPATH … /* Passive Analog Signal Bypass Selection During Powerdown Register */ #define PASSIVE_BYPASS … /* DAC Quiescent Current Adjustment Register */ #define DAC_ICC_ADJ … /* Page select register bits */ #define PAGE0_SELECT … #define PAGE1_SELECT … /* Audio serial data interface control register A bits */ #define BIT_CLK_MASTER … #define WORD_CLK_MASTER … #define DOUT_TRISTATE … /* Codec Datapath setup register 7 */ #define FSREF_44100 … #define FSREF_48000 … #define DUAL_RATE_MODE … #define LDAC2LCH … #define RDAC2RCH … #define LDAC2RCH … #define RDAC2LCH … #define LDAC2MONOMIX … #define RDAC2MONOMIX … /* PLL registers bitfields */ #define PLLP_SHIFT … #define PLLP_MASK … #define PLLQ_SHIFT … #define PLLR_SHIFT … #define PLLJ_SHIFT … #define PLLD_MSB_SHIFT … #define PLLD_LSB_SHIFT … /* Clock generation register bits */ #define CODEC_CLKIN_PLLDIV … #define CODEC_CLKIN_CLKDIV … #define PLL_CLKIN_SHIFT … #define MCLK_SOURCE … #define PLL_CLKDIV_SHIFT … #define PLLCLK_IN_MASK … #define PLLCLK_IN_SHIFT … #define CLKDIV_IN_MASK … #define CLKDIV_IN_SHIFT … /* clock in source */ #define CLKIN_MCLK … #define CLKIN_GPIO2 … #define CLKIN_BCLK … /* Software reset register bits */ #define SOFT_RESET … /* PLL progrramming register A bits */ #define PLL_ENABLE … /* Route bits */ #define ROUTE_ON … /* Mute bits */ #define UNMUTE … #define MUTE_ON … /* Power bits */ #define LADC_PWR_ON … #define RADC_PWR_ON … #define LDAC_PWR_ON … #define RDAC_PWR_ON … #define HPLOUT_PWR_ON … #define HPROUT_PWR_ON … #define HPLCOM_PWR_ON … #define HPRCOM_PWR_ON … #define MONOLOPM_PWR_ON … #define LLOPM_PWR_ON … #define RLOPM_PWR_ON … #define INVERT_VOL(val) … /* Default output volume (inverted) */ #define DEFAULT_VOL … /* Default input volume */ #define DEFAULT_GAIN … /* MICBIAS Control Register */ #define MICBIAS_LEVEL_SHIFT … #define MICBIAS_LEVEL_MASK … /* HPOUT_SC */ #define HPOUT_SC_OCMV_MASK … #define HPOUT_SC_OCMV_SHIFT … #define HPOUT_SC_OCMV_1_35V … #define HPOUT_SC_OCMV_1_5V … #define HPOUT_SC_OCMV_1_65V … #define HPOUT_SC_OCMV_1_8V … /* headset detection / button API */ /* The AIC3x supports detection of stereo headsets (GND + left + right signal) * and cellular headsets (GND + speaker output + microphone input). * It is recommended to enable MIC bias for this function to work properly. * For more information, please refer to the datasheet. */ enum { … }; enum { … }; enum { … }; #define AIC3X_HEADSET_DETECT_ENABLED … #define AIC3X_HEADSET_DETECT_SHIFT … #define AIC3X_HEADSET_DETECT_MASK … #define AIC3X_HEADSET_DEBOUNCE_SHIFT … #define AIC3X_HEADSET_DEBOUNCE_MASK … #define AIC3X_BUTTON_DEBOUNCE_SHIFT … #define AIC3X_BUTTON_DEBOUNCE_MASK … /* GPIO API */ enum { … }; enum { … }; enum aic3x_micbias_voltage { … }; #endif /* _AIC3X_H */
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