// SPDX-License-Identifier: GPL-2.0 // tscs42xx.h -- TSCS42xx ALSA SoC Audio driver // Copyright 2017 Tempo Semiconductor, Inc. // Author: Steven Eckhoff <[email protected]> #ifndef __WOOKIE_H__ #define __WOOKIE_H__ enum { … }; #define R_HPVOLL … #define R_HPVOLR … #define R_SPKVOLL … #define R_SPKVOLR … #define R_DACVOLL … #define R_DACVOLR … #define R_ADCVOLL … #define R_ADCVOLR … #define R_INVOLL … #define R_INVOLR … #define R_INMODE … #define R_INSELL … #define R_INSELR … #define R_AIC1 … #define R_AIC2 … #define R_CNVRTR0 … #define R_ADCSR … #define R_CNVRTR1 … #define R_DACSR … #define R_PWRM1 … #define R_PWRM2 … #define R_CTL … #define R_CONFIG0 … #define R_CONFIG1 … #define R_DMICCTL … #define R_CLECTL … #define R_MUGAIN … #define R_COMPTH … #define R_CMPRAT … #define R_CATKTCL … #define R_CATKTCH … #define R_CRELTCL … #define R_CRELTCH … #define R_LIMTH … #define R_LIMTGT … #define R_LATKTCL … #define R_LATKTCH … #define R_LRELTCL … #define R_LRELTCH … #define R_EXPTH … #define R_EXPRAT … #define R_XATKTCL … #define R_XATKTCH … #define R_XRELTCL … #define R_XRELTCH … #define R_FXCTL … #define R_DACCRWRL … #define R_DACCRWRM … #define R_DACCRWRH … #define R_DACCRRDL … #define R_DACCRRDM … #define R_DACCRRDH … #define R_DACCRADDR … #define R_DCOFSEL … #define R_PLLCTL9 … #define R_PLLCTLA … #define R_PLLCTLB … #define R_PLLCTLC … #define R_PLLCTLD … #define R_PLLCTLE … #define R_PLLCTLF … #define R_PLLCTL10 … #define R_PLLCTL11 … #define R_PLLCTL12 … #define R_PLLCTL1B … #define R_PLLCTL1C … #define R_TIMEBASE … #define R_DEVIDL … #define R_DEVIDH … #define R_RESET … #define R_DACCRSTAT … #define R_PLLCTL0 … #define R_PLLREFSEL … #define R_DACMBCEN … #define R_DACMBCCTL … #define R_DACMBCMUG1 … #define R_DACMBCTHR1 … #define R_DACMBCRAT1 … #define R_DACMBCATK1L … #define R_DACMBCATK1H … #define R_DACMBCREL1L … #define R_DACMBCREL1H … #define R_DACMBCMUG2 … #define R_DACMBCTHR2 … #define R_DACMBCRAT2 … #define R_DACMBCATK2L … #define R_DACMBCATK2H … #define R_DACMBCREL2L … #define R_DACMBCREL2H … #define R_DACMBCMUG3 … #define R_DACMBCTHR3 … #define R_DACMBCRAT3 … #define R_DACMBCATK3L … #define R_DACMBCATK3H … #define R_DACMBCREL3L … #define R_DACMBCREL3H … /* Helpers */ #define RM(m, b) … #define RV(v, b) … /**************************** * R_HPVOLL (0x0) * ****************************/ /* Field Offsets */ #define FB_HPVOLL … /* Field Masks */ #define FM_HPVOLL … /* Field Values */ #define FV_HPVOLL_P6DB … #define FV_HPVOLL_N88PT5DB … #define FV_HPVOLL_MUTE … /* Register Masks */ #define RM_HPVOLL … /* Register Values */ #define RV_HPVOLL_P6DB … #define RV_HPVOLL_N88PT5DB … #define RV_HPVOLL_MUTE … /**************************** * R_HPVOLR (0x1) * ****************************/ /* Field Offsets */ #define FB_HPVOLR … /* Field Masks */ #define FM_HPVOLR … /* Field Values */ #define FV_HPVOLR_P6DB … #define FV_HPVOLR_N88PT5DB … #define FV_HPVOLR_MUTE … /* Register Masks */ #define RM_HPVOLR … /* Register Values */ #define RV_HPVOLR_P6DB … #define RV_HPVOLR_N88PT5DB … #define RV_HPVOLR_MUTE … /***************************** * R_SPKVOLL (0x2) * *****************************/ /* Field Offsets */ #define FB_SPKVOLL … /* Field Masks */ #define FM_SPKVOLL … /* Field Values */ #define FV_SPKVOLL_P12DB … #define FV_SPKVOLL_N77PT25DB … #define FV_SPKVOLL_MUTE … /* Register Masks */ #define RM_SPKVOLL … /* Register Values */ #define RV_SPKVOLL_P12DB … #define RV_SPKVOLL_N77PT25DB … #define RV_SPKVOLL_MUTE … /***************************** * R_SPKVOLR (0x3) * *****************************/ /* Field Offsets */ #define FB_SPKVOLR … /* Field Masks */ #define FM_SPKVOLR … /* Field Values */ #define FV_SPKVOLR_P12DB … #define FV_SPKVOLR_N77PT25DB … #define FV_SPKVOLR_MUTE … /* Register Masks */ #define RM_SPKVOLR … /* Register Values */ #define RV_SPKVOLR_P12DB … #define RV_SPKVOLR_N77PT25DB … #define RV_SPKVOLR_MUTE … /***************************** * R_DACVOLL (0x4) * *****************************/ /* Field Offsets */ #define FB_DACVOLL … /* Field Masks */ #define FM_DACVOLL … /* Field Values */ #define FV_DACVOLL_0DB … #define FV_DACVOLL_N95PT625DB … #define FV_DACVOLL_MUTE … /* Register Masks */ #define RM_DACVOLL … /* Register Values */ #define RV_DACVOLL_0DB … #define RV_DACVOLL_N95PT625DB … #define RV_DACVOLL_MUTE … /***************************** * R_DACVOLR (0x5) * *****************************/ /* Field Offsets */ #define FB_DACVOLR … /* Field Masks */ #define FM_DACVOLR … /* Field Values */ #define FV_DACVOLR_0DB … #define FV_DACVOLR_N95PT625DB … #define FV_DACVOLR_MUTE … /* Register Masks */ #define RM_DACVOLR … /* Register Values */ #define RV_DACVOLR_0DB … #define RV_DACVOLR_N95PT625DB … #define RV_DACVOLR_MUTE … /***************************** * R_ADCVOLL (0x6) * *****************************/ /* Field Offsets */ #define FB_ADCVOLL … /* Field Masks */ #define FM_ADCVOLL … /* Field Values */ #define FV_ADCVOLL_P24DB … #define FV_ADCVOLL_N71PT25DB … #define FV_ADCVOLL_MUTE … /* Register Masks */ #define RM_ADCVOLL … /* Register Values */ #define RV_ADCVOLL_P24DB … #define RV_ADCVOLL_N71PT25DB … #define RV_ADCVOLL_MUTE … /***************************** * R_ADCVOLR (0x7) * *****************************/ /* Field Offsets */ #define FB_ADCVOLR … /* Field Masks */ #define FM_ADCVOLR … /* Field Values */ #define FV_ADCVOLR_P24DB … #define FV_ADCVOLR_N71PT25DB … #define FV_ADCVOLR_MUTE … /* Register Masks */ #define RM_ADCVOLR … /* Register Values */ #define RV_ADCVOLR_P24DB … #define RV_ADCVOLR_N71PT25DB … #define RV_ADCVOLR_MUTE … /**************************** * R_INVOLL (0x8) * ****************************/ /* Field Offsets */ #define FB_INVOLL_INMUTEL … #define FB_INVOLL_IZCL … #define FB_INVOLL … /* Field Masks */ #define FM_INVOLL_INMUTEL … #define FM_INVOLL_IZCL … #define FM_INVOLL … /* Field Values */ #define FV_INVOLL_INMUTEL_ENABLE … #define FV_INVOLL_INMUTEL_DISABLE … #define FV_INVOLL_IZCL_ENABLE … #define FV_INVOLL_IZCL_DISABLE … #define FV_INVOLL_P30DB … #define FV_INVOLL_N17PT25DB … /* Register Masks */ #define RM_INVOLL_INMUTEL … #define RM_INVOLL_IZCL … #define RM_INVOLL … /* Register Values */ #define RV_INVOLL_INMUTEL_ENABLE … #define RV_INVOLL_INMUTEL_DISABLE … #define RV_INVOLL_IZCL_ENABLE … #define RV_INVOLL_IZCL_DISABLE … #define RV_INVOLL_P30DB … #define RV_INVOLL_N17PT25DB … /**************************** * R_INVOLR (0x9) * ****************************/ /* Field Offsets */ #define FB_INVOLR_INMUTER … #define FB_INVOLR_IZCR … #define FB_INVOLR … /* Field Masks */ #define FM_INVOLR_INMUTER … #define FM_INVOLR_IZCR … #define FM_INVOLR … /* Field Values */ #define FV_INVOLR_INMUTER_ENABLE … #define FV_INVOLR_INMUTER_DISABLE … #define FV_INVOLR_IZCR_ENABLE … #define FV_INVOLR_IZCR_DISABLE … #define FV_INVOLR_P30DB … #define FV_INVOLR_N17PT25DB … /* Register Masks */ #define RM_INVOLR_INMUTER … #define RM_INVOLR_IZCR … #define RM_INVOLR … /* Register Values */ #define RV_INVOLR_INMUTER_ENABLE … #define RV_INVOLR_INMUTER_DISABLE … #define RV_INVOLR_IZCR_ENABLE … #define RV_INVOLR_IZCR_DISABLE … #define RV_INVOLR_P30DB … #define RV_INVOLR_N17PT25DB … /***************************** * R_INMODE (0x0B) * *****************************/ /* Field Offsets */ #define FB_INMODE_DS … /* Field Masks */ #define FM_INMODE_DS … /* Field Values */ #define FV_INMODE_DS_LRIN1 … #define FV_INMODE_DS_LRIN2 … /* Register Masks */ #define RM_INMODE_DS … /* Register Values */ #define RV_INMODE_DS_LRIN1 … #define RV_INMODE_DS_LRIN2 … /***************************** * R_INSELL (0x0C) * *****************************/ /* Field Offsets */ #define FB_INSELL … #define FB_INSELL_MICBSTL … /* Field Masks */ #define FM_INSELL … #define FM_INSELL_MICBSTL … /* Field Values */ #define FV_INSELL_IN1 … #define FV_INSELL_IN2 … #define FV_INSELL_IN3 … #define FV_INSELL_D2S … #define FV_INSELL_MICBSTL_OFF … #define FV_INSELL_MICBSTL_10DB … #define FV_INSELL_MICBSTL_20DB … #define FV_INSELL_MICBSTL_30DB … /* Register Masks */ #define RM_INSELL … #define RM_INSELL_MICBSTL … /* Register Values */ #define RV_INSELL_IN1 … #define RV_INSELL_IN2 … #define RV_INSELL_IN3 … #define RV_INSELL_D2S … #define RV_INSELL_MICBSTL_OFF … #define RV_INSELL_MICBSTL_10DB … #define RV_INSELL_MICBSTL_20DB … #define RV_INSELL_MICBSTL_30DB … /***************************** * R_INSELR (0x0D) * *****************************/ /* Field Offsets */ #define FB_INSELR … #define FB_INSELR_MICBSTR … /* Field Masks */ #define FM_INSELR … #define FM_INSELR_MICBSTR … /* Field Values */ #define FV_INSELR_IN1 … #define FV_INSELR_IN2 … #define FV_INSELR_IN3 … #define FV_INSELR_D2S … #define FV_INSELR_MICBSTR_OFF … #define FV_INSELR_MICBSTR_10DB … #define FV_INSELR_MICBSTR_20DB … #define FV_INSELR_MICBSTR_30DB … /* Register Masks */ #define RM_INSELR … #define RM_INSELR_MICBSTR … /* Register Values */ #define RV_INSELR_IN1 … #define RV_INSELR_IN2 … #define RV_INSELR_IN3 … #define RV_INSELR_D2S … #define RV_INSELR_MICBSTR_OFF … #define RV_INSELR_MICBSTR_10DB … #define RV_INSELR_MICBSTR_20DB … #define RV_INSELR_MICBSTR_30DB … /*************************** * R_AIC1 (0x13) * ***************************/ /* Field Offsets */ #define FB_AIC1_BCLKINV … #define FB_AIC1_MS … #define FB_AIC1_LRP … #define FB_AIC1_WL … #define FB_AIC1_FORMAT … /* Field Masks */ #define FM_AIC1_BCLKINV … #define FM_AIC1_MS … #define FM_AIC1_LRP … #define FM_AIC1_WL … #define FM_AIC1_FORMAT … /* Field Values */ #define FV_AIC1_BCLKINV_ENABLE … #define FV_AIC1_BCLKINV_DISABLE … #define FV_AIC1_MS_MASTER … #define FV_AIC1_MS_SLAVE … #define FV_AIC1_LRP_INVERT … #define FV_AIC1_LRP_NORMAL … #define FV_AIC1_WL_16 … #define FV_AIC1_WL_20 … #define FV_AIC1_WL_24 … #define FV_AIC1_WL_32 … #define FV_AIC1_FORMAT_RIGHT … #define FV_AIC1_FORMAT_LEFT … #define FV_AIC1_FORMAT_I2S … /* Register Masks */ #define RM_AIC1_BCLKINV … #define RM_AIC1_MS … #define RM_AIC1_LRP … #define RM_AIC1_WL … #define RM_AIC1_FORMAT … /* Register Values */ #define RV_AIC1_BCLKINV_ENABLE … #define RV_AIC1_BCLKINV_DISABLE … #define RV_AIC1_MS_MASTER … #define RV_AIC1_MS_SLAVE … #define RV_AIC1_LRP_INVERT … #define RV_AIC1_LRP_NORMAL … #define RV_AIC1_WL_16 … #define RV_AIC1_WL_20 … #define RV_AIC1_WL_24 … #define RV_AIC1_WL_32 … #define RV_AIC1_FORMAT_RIGHT … #define RV_AIC1_FORMAT_LEFT … #define RV_AIC1_FORMAT_I2S … /*************************** * R_AIC2 (0x14) * ***************************/ /* Field Offsets */ #define FB_AIC2_DACDSEL … #define FB_AIC2_ADCDSEL … #define FB_AIC2_TRI … #define FB_AIC2_BLRCM … /* Field Masks */ #define FM_AIC2_DACDSEL … #define FM_AIC2_ADCDSEL … #define FM_AIC2_TRI … #define FM_AIC2_BLRCM … /* Field Values */ #define FV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED … /* Register Masks */ #define RM_AIC2_DACDSEL … #define RM_AIC2_ADCDSEL … #define RM_AIC2_TRI … #define RM_AIC2_BLRCM … /* Register Values */ #define RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED … /****************************** * R_CNVRTR0 (0x16) * ******************************/ /* Field Offsets */ #define FB_CNVRTR0_ADCPOLR … #define FB_CNVRTR0_ADCPOLL … #define FB_CNVRTR0_AMONOMIX … #define FB_CNVRTR0_ADCMU … #define FB_CNVRTR0_HPOR … #define FB_CNVRTR0_ADCHPDR … #define FB_CNVRTR0_ADCHPDL … /* Field Masks */ #define FM_CNVRTR0_ADCPOLR … #define FM_CNVRTR0_ADCPOLL … #define FM_CNVRTR0_AMONOMIX … #define FM_CNVRTR0_ADCMU … #define FM_CNVRTR0_HPOR … #define FM_CNVRTR0_ADCHPDR … #define FM_CNVRTR0_ADCHPDL … /* Field Values */ #define FV_CNVRTR0_ADCPOLR_INVERT … #define FV_CNVRTR0_ADCPOLR_NORMAL … #define FV_CNVRTR0_ADCPOLL_INVERT … #define FV_CNVRTR0_ADCPOLL_NORMAL … #define FV_CNVRTR0_ADCMU_ENABLE … #define FV_CNVRTR0_ADCMU_DISABLE … #define FV_CNVRTR0_ADCHPDR_ENABLE … #define FV_CNVRTR0_ADCHPDR_DISABLE … #define FV_CNVRTR0_ADCHPDL_ENABLE … #define FV_CNVRTR0_ADCHPDL_DISABLE … /* Register Masks */ #define RM_CNVRTR0_ADCPOLR … #define RM_CNVRTR0_ADCPOLL … #define RM_CNVRTR0_AMONOMIX … #define RM_CNVRTR0_ADCMU … #define RM_CNVRTR0_HPOR … #define RM_CNVRTR0_ADCHPDR … #define RM_CNVRTR0_ADCHPDL … /* Register Values */ #define RV_CNVRTR0_ADCPOLR_INVERT … #define RV_CNVRTR0_ADCPOLR_NORMAL … #define RV_CNVRTR0_ADCPOLL_INVERT … #define RV_CNVRTR0_ADCPOLL_NORMAL … #define RV_CNVRTR0_ADCMU_ENABLE … #define RV_CNVRTR0_ADCMU_DISABLE … #define RV_CNVRTR0_ADCHPDR_ENABLE … #define RV_CNVRTR0_ADCHPDR_DISABLE … #define RV_CNVRTR0_ADCHPDL_ENABLE … #define RV_CNVRTR0_ADCHPDL_DISABLE … /**************************** * R_ADCSR (0x17) * ****************************/ /* Field Offsets */ #define FB_ADCSR_ABCM … #define FB_ADCSR_ABR … #define FB_ADCSR_ABM … /* Field Masks */ #define FM_ADCSR_ABCM … #define FM_ADCSR_ABR … #define FM_ADCSR_ABM … /* Field Values */ #define FV_ADCSR_ABCM_AUTO … #define FV_ADCSR_ABCM_32 … #define FV_ADCSR_ABCM_40 … #define FV_ADCSR_ABCM_64 … #define FV_ADCSR_ABR_32 … #define FV_ADCSR_ABR_44_1 … #define FV_ADCSR_ABR_48 … #define FV_ADCSR_ABM_PT25 … #define FV_ADCSR_ABM_PT5 … #define FV_ADCSR_ABM_1 … #define FV_ADCSR_ABM_2 … /* Register Masks */ #define RM_ADCSR_ABCM … #define RM_ADCSR_ABR … #define RM_ADCSR_ABM … /* Register Values */ #define RV_ADCSR_ABCM_AUTO … #define RV_ADCSR_ABCM_32 … #define RV_ADCSR_ABCM_40 … #define RV_ADCSR_ABCM_64 … #define RV_ADCSR_ABR_32 … #define RV_ADCSR_ABR_44_1 … #define RV_ADCSR_ABR_48 … #define RV_ADCSR_ABR_ … #define RV_ADCSR_ABM_PT25 … #define RV_ADCSR_ABM_PT5 … #define RV_ADCSR_ABM_1 … #define RV_ADCSR_ABM_2 … /****************************** * R_CNVRTR1 (0x18) * ******************************/ /* Field Offsets */ #define FB_CNVRTR1_DACPOLR … #define FB_CNVRTR1_DACPOLL … #define FB_CNVRTR1_DMONOMIX … #define FB_CNVRTR1_DACMU … #define FB_CNVRTR1_DEEMPH … #define FB_CNVRTR1_DACDITH … /* Field Masks */ #define FM_CNVRTR1_DACPOLR … #define FM_CNVRTR1_DACPOLL … #define FM_CNVRTR1_DMONOMIX … #define FM_CNVRTR1_DACMU … #define FM_CNVRTR1_DEEMPH … #define FM_CNVRTR1_DACDITH … /* Field Values */ #define FV_CNVRTR1_DACPOLR_INVERT … #define FV_CNVRTR1_DACPOLR_NORMAL … #define FV_CNVRTR1_DACPOLL_INVERT … #define FV_CNVRTR1_DACPOLL_NORMAL … #define FV_CNVRTR1_DMONOMIX_ENABLE … #define FV_CNVRTR1_DMONOMIX_DISABLE … #define FV_CNVRTR1_DACMU_ENABLE … #define FV_CNVRTR1_DACMU_DISABLE … /* Register Masks */ #define RM_CNVRTR1_DACPOLR … #define RM_CNVRTR1_DACPOLL … #define RM_CNVRTR1_DMONOMIX … #define RM_CNVRTR1_DACMU … #define RM_CNVRTR1_DEEMPH … #define RM_CNVRTR1_DACDITH … /* Register Values */ #define RV_CNVRTR1_DACPOLR_INVERT … #define RV_CNVRTR1_DACPOLR_NORMAL … #define RV_CNVRTR1_DACPOLL_INVERT … #define RV_CNVRTR1_DACPOLL_NORMAL … #define RV_CNVRTR1_DMONOMIX_ENABLE … #define RV_CNVRTR1_DMONOMIX_DISABLE … #define RV_CNVRTR1_DACMU_ENABLE … #define RV_CNVRTR1_DACMU_DISABLE … /**************************** * R_DACSR (0x19) * ****************************/ /* Field Offsets */ #define FB_DACSR_DBCM … #define FB_DACSR_DBR … #define FB_DACSR_DBM … /* Field Masks */ #define FM_DACSR_DBCM … #define FM_DACSR_DBR … #define FM_DACSR_DBM … /* Field Values */ #define FV_DACSR_DBCM_AUTO … #define FV_DACSR_DBCM_32 … #define FV_DACSR_DBCM_40 … #define FV_DACSR_DBCM_64 … #define FV_DACSR_DBR_32 … #define FV_DACSR_DBR_44_1 … #define FV_DACSR_DBR_48 … #define FV_DACSR_DBM_PT25 … #define FV_DACSR_DBM_PT5 … #define FV_DACSR_DBM_1 … #define FV_DACSR_DBM_2 … /* Register Masks */ #define RM_DACSR_DBCM … #define RM_DACSR_DBR … #define RM_DACSR_DBM … /* Register Values */ #define RV_DACSR_DBCM_AUTO … #define RV_DACSR_DBCM_32 … #define RV_DACSR_DBCM_40 … #define RV_DACSR_DBCM_64 … #define RV_DACSR_DBR_32 … #define RV_DACSR_DBR_44_1 … #define RV_DACSR_DBR_48 … #define RV_DACSR_DBM_PT25 … #define RV_DACSR_DBM_PT5 … #define RV_DACSR_DBM_1 … #define RV_DACSR_DBM_2 … /**************************** * R_PWRM1 (0x1A) * ****************************/ /* Field Offsets */ #define FB_PWRM1_BSTL … #define FB_PWRM1_BSTR … #define FB_PWRM1_PGAL … #define FB_PWRM1_PGAR … #define FB_PWRM1_ADCL … #define FB_PWRM1_ADCR … #define FB_PWRM1_MICB … #define FB_PWRM1_DIGENB … /* Field Masks */ #define FM_PWRM1_BSTL … #define FM_PWRM1_BSTR … #define FM_PWRM1_PGAL … #define FM_PWRM1_PGAR … #define FM_PWRM1_ADCL … #define FM_PWRM1_ADCR … #define FM_PWRM1_MICB … #define FM_PWRM1_DIGENB … /* Field Values */ #define FV_PWRM1_BSTL_ENABLE … #define FV_PWRM1_BSTL_DISABLE … #define FV_PWRM1_BSTR_ENABLE … #define FV_PWRM1_BSTR_DISABLE … #define FV_PWRM1_PGAL_ENABLE … #define FV_PWRM1_PGAL_DISABLE … #define FV_PWRM1_PGAR_ENABLE … #define FV_PWRM1_PGAR_DISABLE … #define FV_PWRM1_ADCL_ENABLE … #define FV_PWRM1_ADCL_DISABLE … #define FV_PWRM1_ADCR_ENABLE … #define FV_PWRM1_ADCR_DISABLE … #define FV_PWRM1_MICB_ENABLE … #define FV_PWRM1_MICB_DISABLE … #define FV_PWRM1_DIGENB_DISABLE … #define FV_PWRM1_DIGENB_ENABLE … /* Register Masks */ #define RM_PWRM1_BSTL … #define RM_PWRM1_BSTR … #define RM_PWRM1_PGAL … #define RM_PWRM1_PGAR … #define RM_PWRM1_ADCL … #define RM_PWRM1_ADCR … #define RM_PWRM1_MICB … #define RM_PWRM1_DIGENB … /* Register Values */ #define RV_PWRM1_BSTL_ENABLE … #define RV_PWRM1_BSTL_DISABLE … #define RV_PWRM1_BSTR_ENABLE … #define RV_PWRM1_BSTR_DISABLE … #define RV_PWRM1_PGAL_ENABLE … #define RV_PWRM1_PGAL_DISABLE … #define RV_PWRM1_PGAR_ENABLE … #define RV_PWRM1_PGAR_DISABLE … #define RV_PWRM1_ADCL_ENABLE … #define RV_PWRM1_ADCL_DISABLE … #define RV_PWRM1_ADCR_ENABLE … #define RV_PWRM1_ADCR_DISABLE … #define RV_PWRM1_MICB_ENABLE … #define RV_PWRM1_MICB_DISABLE … #define RV_PWRM1_DIGENB_DISABLE … #define RV_PWRM1_DIGENB_ENABLE … /**************************** * R_PWRM2 (0x1B) * ****************************/ /* Field Offsets */ #define FB_PWRM2_D2S … #define FB_PWRM2_HPL … #define FB_PWRM2_HPR … #define FB_PWRM2_SPKL … #define FB_PWRM2_SPKR … #define FB_PWRM2_INSELL … #define FB_PWRM2_INSELR … #define FB_PWRM2_VREF … /* Field Masks */ #define FM_PWRM2_D2S … #define FM_PWRM2_HPL … #define FM_PWRM2_HPR … #define FM_PWRM2_SPKL … #define FM_PWRM2_SPKR … #define FM_PWRM2_INSELL … #define FM_PWRM2_INSELR … #define FM_PWRM2_VREF … /* Field Values */ #define FV_PWRM2_D2S_ENABLE … #define FV_PWRM2_D2S_DISABLE … #define FV_PWRM2_HPL_ENABLE … #define FV_PWRM2_HPL_DISABLE … #define FV_PWRM2_HPR_ENABLE … #define FV_PWRM2_HPR_DISABLE … #define FV_PWRM2_SPKL_ENABLE … #define FV_PWRM2_SPKL_DISABLE … #define FV_PWRM2_SPKR_ENABLE … #define FV_PWRM2_SPKR_DISABLE … #define FV_PWRM2_INSELL_ENABLE … #define FV_PWRM2_INSELL_DISABLE … #define FV_PWRM2_INSELR_ENABLE … #define FV_PWRM2_INSELR_DISABLE … #define FV_PWRM2_VREF_ENABLE … #define FV_PWRM2_VREF_DISABLE … /* Register Masks */ #define RM_PWRM2_D2S … #define RM_PWRM2_HPL … #define RM_PWRM2_HPR … #define RM_PWRM2_SPKL … #define RM_PWRM2_SPKR … #define RM_PWRM2_INSELL … #define RM_PWRM2_INSELR … #define RM_PWRM2_VREF … /* Register Values */ #define RV_PWRM2_D2S_ENABLE … #define RV_PWRM2_D2S_DISABLE … #define RV_PWRM2_HPL_ENABLE … #define RV_PWRM2_HPL_DISABLE … #define RV_PWRM2_HPR_ENABLE … #define RV_PWRM2_HPR_DISABLE … #define RV_PWRM2_SPKL_ENABLE … #define RV_PWRM2_SPKL_DISABLE … #define RV_PWRM2_SPKR_ENABLE … #define RV_PWRM2_SPKR_DISABLE … #define RV_PWRM2_INSELL_ENABLE … #define RV_PWRM2_INSELL_DISABLE … #define RV_PWRM2_INSELR_ENABLE … #define RV_PWRM2_INSELR_DISABLE … #define RV_PWRM2_VREF_ENABLE … #define RV_PWRM2_VREF_DISABLE … /****************************** * R_CTL (0x1C) * ******************************/ /* Fiel Offsets */ #define FB_CTL_HPSWEN … #define FB_CTL_HPSWPOL … /****************************** * R_CONFIG0 (0x1F) * ******************************/ /* Field Offsets */ #define FB_CONFIG0_ASDM … #define FB_CONFIG0_DSDM … #define FB_CONFIG0_DC_BYPASS … #define FB_CONFIG0_SD_FORCE_ON … /* Field Masks */ #define FM_CONFIG0_ASDM … #define FM_CONFIG0_DSDM … #define FM_CONFIG0_DC_BYPASS … #define FM_CONFIG0_SD_FORCE_ON … /* Field Values */ #define FV_CONFIG0_ASDM_HALF … #define FV_CONFIG0_ASDM_FULL … #define FV_CONFIG0_ASDM_AUTO … #define FV_CONFIG0_DSDM_HALF … #define FV_CONFIG0_DSDM_FULL … #define FV_CONFIG0_DSDM_AUTO … #define FV_CONFIG0_DC_BYPASS_ENABLE … #define FV_CONFIG0_DC_BYPASS_DISABLE … #define FV_CONFIG0_SD_FORCE_ON_ENABLE … #define FV_CONFIG0_SD_FORCE_ON_DISABLE … /* Register Masks */ #define RM_CONFIG0_ASDM … #define RM_CONFIG0_DSDM … #define RM_CONFIG0_DC_BYPASS … #define RM_CONFIG0_SD_FORCE_ON … /* Register Values */ #define RV_CONFIG0_ASDM_HALF … #define RV_CONFIG0_ASDM_FULL … #define RV_CONFIG0_ASDM_AUTO … #define RV_CONFIG0_DSDM_HALF … #define RV_CONFIG0_DSDM_FULL … #define RV_CONFIG0_DSDM_AUTO … #define RV_CONFIG0_DC_BYPASS_ENABLE … #define RV_CONFIG0_DC_BYPASS_DISABLE … #define RV_CONFIG0_SD_FORCE_ON_ENABLE … #define RV_CONFIG0_SD_FORCE_ON_DISABLE … /****************************** * R_CONFIG1 (0x20) * ******************************/ /* Field Offsets */ #define FB_CONFIG1_EQ2_EN … #define FB_CONFIG1_EQ2_BE … #define FB_CONFIG1_EQ1_EN … #define FB_CONFIG1_EQ1_BE … /* Field Masks */ #define FM_CONFIG1_EQ2_EN … #define FM_CONFIG1_EQ2_BE … #define FM_CONFIG1_EQ1_EN … #define FM_CONFIG1_EQ1_BE … /* Field Values */ #define FV_CONFIG1_EQ2_EN_ENABLE … #define FV_CONFIG1_EQ2_EN_DISABLE … #define FV_CONFIG1_EQ2_BE_PRE … #define FV_CONFIG1_EQ2_BE_PRE_EQ_0 … #define FV_CONFIG1_EQ2_BE_PRE_EQ0_1 … #define FV_CONFIG1_EQ2_BE_PRE_EQ0_2 … #define FV_CONFIG1_EQ2_BE_PRE_EQ0_3 … #define FV_CONFIG1_EQ2_BE_PRE_EQ0_4 … #define FV_CONFIG1_EQ2_BE_PRE_EQ0_5 … #define FV_CONFIG1_EQ1_EN_ENABLE … #define FV_CONFIG1_EQ1_EN_DISABLE … #define FV_CONFIG1_EQ1_BE_PRE … #define FV_CONFIG1_EQ1_BE_PRE_EQ_0 … #define FV_CONFIG1_EQ1_BE_PRE_EQ0_1 … #define FV_CONFIG1_EQ1_BE_PRE_EQ0_2 … #define FV_CONFIG1_EQ1_BE_PRE_EQ0_3 … #define FV_CONFIG1_EQ1_BE_PRE_EQ0_4 … #define FV_CONFIG1_EQ1_BE_PRE_EQ0_5 … /* Register Masks */ #define RM_CONFIG1_EQ2_EN … #define RM_CONFIG1_EQ2_BE … #define RM_CONFIG1_EQ1_EN … #define RM_CONFIG1_EQ1_BE … /* Register Values */ #define RV_CONFIG1_EQ2_EN_ENABLE … #define RV_CONFIG1_EQ2_EN_DISABLE … #define RV_CONFIG1_EQ2_BE_PRE … #define RV_CONFIG1_EQ2_BE_PRE_EQ_0 … #define RV_CONFIG1_EQ2_BE_PRE_EQ0_1 … #define RV_CONFIG1_EQ2_BE_PRE_EQ0_2 … #define RV_CONFIG1_EQ2_BE_PRE_EQ0_3 … #define RV_CONFIG1_EQ2_BE_PRE_EQ0_4 … #define RV_CONFIG1_EQ2_BE_PRE_EQ0_5 … #define RV_CONFIG1_EQ1_EN_ENABLE … #define RV_CONFIG1_EQ1_EN_DISABLE … #define RV_CONFIG1_EQ1_BE_PRE … #define RV_CONFIG1_EQ1_BE_PRE_EQ_0 … #define RV_CONFIG1_EQ1_BE_PRE_EQ0_1 … #define RV_CONFIG1_EQ1_BE_PRE_EQ0_2 … #define RV_CONFIG1_EQ1_BE_PRE_EQ0_3 … #define RV_CONFIG1_EQ1_BE_PRE_EQ0_4 … #define RV_CONFIG1_EQ1_BE_PRE_EQ0_5 … /****************************** * R_DMICCTL (0x24) * ******************************/ /* Field Offsets */ #define FB_DMICCTL_DMICEN … #define FB_DMICCTL_DMONO … #define FB_DMICCTL_DMPHADJ … #define FB_DMICCTL_DMRATE … /* Field Masks */ #define FM_DMICCTL_DMICEN … #define FM_DMICCTL_DMONO … #define FM_DMICCTL_DMPHADJ … #define FM_DMICCTL_DMRATE … /* Field Values */ #define FV_DMICCTL_DMICEN_ENABLE … #define FV_DMICCTL_DMICEN_DISABLE … #define FV_DMICCTL_DMONO_STEREO … #define FV_DMICCTL_DMONO_MONO … /* Register Masks */ #define RM_DMICCTL_DMICEN … #define RM_DMICCTL_DMONO … #define RM_DMICCTL_DMPHADJ … #define RM_DMICCTL_DMRATE … /* Register Values */ #define RV_DMICCTL_DMICEN_ENABLE … #define RV_DMICCTL_DMICEN_DISABLE … #define RV_DMICCTL_DMONO_STEREO … #define RV_DMICCTL_DMONO_MONO … /***************************** * R_CLECTL (0x25) * *****************************/ /* Field Offsets */ #define FB_CLECTL_LVL_MODE … #define FB_CLECTL_WINDOWSEL … #define FB_CLECTL_EXP_EN … #define FB_CLECTL_LIMIT_EN … #define FB_CLECTL_COMP_EN … /* Field Masks */ #define FM_CLECTL_LVL_MODE … #define FM_CLECTL_WINDOWSEL … #define FM_CLECTL_EXP_EN … #define FM_CLECTL_LIMIT_EN … #define FM_CLECTL_COMP_EN … /* Field Values */ #define FV_CLECTL_LVL_MODE_AVG … #define FV_CLECTL_LVL_MODE_PEAK … #define FV_CLECTL_WINDOWSEL_512 … #define FV_CLECTL_WINDOWSEL_64 … #define FV_CLECTL_EXP_EN_ENABLE … #define FV_CLECTL_EXP_EN_DISABLE … #define FV_CLECTL_LIMIT_EN_ENABLE … #define FV_CLECTL_LIMIT_EN_DISABLE … #define FV_CLECTL_COMP_EN_ENABLE … #define FV_CLECTL_COMP_EN_DISABLE … /* Register Masks */ #define RM_CLECTL_LVL_MODE … #define RM_CLECTL_WINDOWSEL … #define RM_CLECTL_EXP_EN … #define RM_CLECTL_LIMIT_EN … #define RM_CLECTL_COMP_EN … /* Register Values */ #define RV_CLECTL_LVL_MODE_AVG … #define RV_CLECTL_LVL_MODE_PEAK … #define RV_CLECTL_WINDOWSEL_512 … #define RV_CLECTL_WINDOWSEL_64 … #define RV_CLECTL_EXP_EN_ENABLE … #define RV_CLECTL_EXP_EN_DISABLE … #define RV_CLECTL_LIMIT_EN_ENABLE … #define RV_CLECTL_LIMIT_EN_DISABLE … #define RV_CLECTL_COMP_EN_ENABLE … #define RV_CLECTL_COMP_EN_DISABLE … /***************************** * R_MUGAIN (0x26) * *****************************/ /* Field Offsets */ #define FB_MUGAIN_CLEMUG … /* Field Masks */ #define FM_MUGAIN_CLEMUG … /* Field Values */ #define FV_MUGAIN_CLEMUG_46PT5DB … #define FV_MUGAIN_CLEMUG_0DB … /* Register Masks */ #define RM_MUGAIN_CLEMUG … /* Register Values */ #define RV_MUGAIN_CLEMUG_46PT5DB … #define RV_MUGAIN_CLEMUG_0DB … /***************************** * R_COMPTH (0x27) * *****************************/ /* Field Offsets */ #define FB_COMPTH … /* Field Masks */ #define FM_COMPTH … /* Field Values */ #define FV_COMPTH_0DB … #define FV_COMPTH_N95PT625DB … /* Register Masks */ #define RM_COMPTH … /* Register Values */ #define RV_COMPTH_0DB … #define RV_COMPTH_N95PT625DB … /***************************** * R_CMPRAT (0x28) * *****************************/ /* Field Offsets */ #define FB_CMPRAT … /* Field Masks */ #define FM_CMPRAT … /* Register Masks */ #define RM_CMPRAT … /****************************** * R_CATKTCL (0x29) * ******************************/ /* Field Offsets */ #define FB_CATKTCL … /* Field Masks */ #define FM_CATKTCL … /* Register Masks */ #define RM_CATKTCL … /****************************** * R_CATKTCH (0x2A) * ******************************/ /* Field Offsets */ #define FB_CATKTCH … /* Field Masks */ #define FM_CATKTCH … /* Register Masks */ #define RM_CATKTCH … /****************************** * R_CRELTCL (0x2B) * ******************************/ /* Field Offsets */ #define FB_CRELTCL … /* Field Masks */ #define FM_CRELTCL … /* Register Masks */ #define RM_CRELTCL … /****************************** * R_CRELTCH (0x2C) * ******************************/ /* Field Offsets */ #define FB_CRELTCH … /* Field Masks */ #define FM_CRELTCH … /* Register Masks */ #define RM_CRELTCH … /**************************** * R_LIMTH (0x2D) * ****************************/ /* Field Offsets */ #define FB_LIMTH … /* Field Masks */ #define FM_LIMTH … /* Field Values */ #define FV_LIMTH_0DB … #define FV_LIMTH_N95PT625DB … /* Register Masks */ #define RM_LIMTH … /* Register Values */ #define RV_LIMTH_0DB … #define RV_LIMTH_N95PT625DB … /***************************** * R_LIMTGT (0x2E) * *****************************/ /* Field Offsets */ #define FB_LIMTGT … /* Field Masks */ #define FM_LIMTGT … /* Field Values */ #define FV_LIMTGT_0DB … #define FV_LIMTGT_N95PT625DB … /* Register Masks */ #define RM_LIMTGT … /* Register Values */ #define RV_LIMTGT_0DB … #define RV_LIMTGT_N95PT625DB … /****************************** * R_LATKTCL (0x2F) * ******************************/ /* Field Offsets */ #define FB_LATKTCL … /* Field Masks */ #define FM_LATKTCL … /* Register Masks */ #define RM_LATKTCL … /****************************** * R_LATKTCH (0x30) * ******************************/ /* Field Offsets */ #define FB_LATKTCH … /* Field Masks */ #define FM_LATKTCH … /* Register Masks */ #define RM_LATKTCH … /****************************** * R_LRELTCL (0x31) * ******************************/ /* Field Offsets */ #define FB_LRELTCL … /* Field Masks */ #define FM_LRELTCL … /* Register Masks */ #define RM_LRELTCL … /****************************** * R_LRELTCH (0x32) * ******************************/ /* Field Offsets */ #define FB_LRELTCH … /* Field Masks */ #define FM_LRELTCH … /* Register Masks */ #define RM_LRELTCH … /**************************** * R_EXPTH (0x33) * ****************************/ /* Field Offsets */ #define FB_EXPTH … /* Field Masks */ #define FM_EXPTH … /* Field Values */ #define FV_EXPTH_0DB … #define FV_EXPTH_N95PT625DB … /* Register Masks */ #define RM_EXPTH … /* Register Values */ #define RV_EXPTH_0DB … #define RV_EXPTH_N95PT625DB … /***************************** * R_EXPRAT (0x34) * *****************************/ /* Field Offsets */ #define FB_EXPRAT … /* Field Masks */ #define FM_EXPRAT … /* Register Masks */ #define RM_EXPRAT … /****************************** * R_XATKTCL (0x35) * ******************************/ /* Field Offsets */ #define FB_XATKTCL … /* Field Masks */ #define FM_XATKTCL … /* Register Masks */ #define RM_XATKTCL … /****************************** * R_XATKTCH (0x36) * ******************************/ /* Field Offsets */ #define FB_XATKTCH … /* Field Masks */ #define FM_XATKTCH … /* Register Masks */ #define RM_XATKTCH … /****************************** * R_XRELTCL (0x37) * ******************************/ /* Field Offsets */ #define FB_XRELTCL … /* Field Masks */ #define FM_XRELTCL … /* Register Masks */ #define RM_XRELTCL … /****************************** * R_XRELTCH (0x38) * ******************************/ /* Field Offsets */ #define FB_XRELTCH … /* Field Masks */ #define FM_XRELTCH … /* Register Masks */ #define RM_XRELTCH … /**************************** * R_FXCTL (0x39) * ****************************/ /* Field Offsets */ #define FB_FXCTL_3DEN … #define FB_FXCTL_TEEN … #define FB_FXCTL_TNLFBYPASS … #define FB_FXCTL_BEEN … #define FB_FXCTL_BNLFBYPASS … /* Field Masks */ #define FM_FXCTL_3DEN … #define FM_FXCTL_TEEN … #define FM_FXCTL_TNLFBYPASS … #define FM_FXCTL_BEEN … #define FM_FXCTL_BNLFBYPASS … /* Field Values */ #define FV_FXCTL_3DEN_ENABLE … #define FV_FXCTL_3DEN_DISABLE … #define FV_FXCTL_TEEN_ENABLE … #define FV_FXCTL_TEEN_DISABLE … #define FV_FXCTL_TNLFBYPASS_ENABLE … #define FV_FXCTL_TNLFBYPASS_DISABLE … #define FV_FXCTL_BEEN_ENABLE … #define FV_FXCTL_BEEN_DISABLE … #define FV_FXCTL_BNLFBYPASS_ENABLE … #define FV_FXCTL_BNLFBYPASS_DISABLE … /* Register Masks */ #define RM_FXCTL_3DEN … #define RM_FXCTL_TEEN … #define RM_FXCTL_TNLFBYPASS … #define RM_FXCTL_BEEN … #define RM_FXCTL_BNLFBYPASS … /* Register Values */ #define RV_FXCTL_3DEN_ENABLE … #define RV_FXCTL_3DEN_DISABLE … #define RV_FXCTL_TEEN_ENABLE … #define RV_FXCTL_TEEN_DISABLE … #define RV_FXCTL_TNLFBYPASS_ENABLE … #define RV_FXCTL_TNLFBYPASS_DISABLE … #define RV_FXCTL_BEEN_ENABLE … #define RV_FXCTL_BEEN_DISABLE … #define RV_FXCTL_BNLFBYPASS_ENABLE … #define RV_FXCTL_BNLFBYPASS_DISABLE … /******************************* * R_DACCRWRL (0x3A) * *******************************/ /* Field Offsets */ #define FB_DACCRWRL_DACCRWDL … /* Field Masks */ #define FM_DACCRWRL_DACCRWDL … /* Register Masks */ #define RM_DACCRWRL_DACCRWDL … /******************************* * R_DACCRWRM (0x3B) * *******************************/ /* Field Offsets */ #define FB_DACCRWRM_DACCRWDM … /* Field Masks */ #define FM_DACCRWRM_DACCRWDM … /* Register Masks */ #define RM_DACCRWRM_DACCRWDM … /******************************* * R_DACCRWRH (0x3C) * *******************************/ /* Field Offsets */ #define FB_DACCRWRH_DACCRWDH … /* Field Masks */ #define FM_DACCRWRH_DACCRWDH … /* Register Masks */ #define RM_DACCRWRH_DACCRWDH … /******************************* * R_DACCRRDL (0x3D) * *******************************/ /* Field Offsets */ #define FB_DACCRRDL … /* Field Masks */ #define FM_DACCRRDL … /* Register Masks */ #define RM_DACCRRDL … /******************************* * R_DACCRRDM (0x3E) * *******************************/ /* Field Offsets */ #define FB_DACCRRDM … /* Field Masks */ #define FM_DACCRRDM … /* Register Masks */ #define RM_DACCRRDM … /******************************* * R_DACCRRDH (0x3F) * *******************************/ /* Field Offsets */ #define FB_DACCRRDH … /* Field Masks */ #define FM_DACCRRDH … /* Register Masks */ #define RM_DACCRRDH … /******************************** * R_DACCRADDR (0x40) * ********************************/ /* Field Offsets */ #define FB_DACCRADDR_DACCRADD … /* Field Masks */ #define FM_DACCRADDR_DACCRADD … /* Register Masks */ #define RM_DACCRADDR_DACCRADD … /****************************** * R_DCOFSEL (0x41) * ******************************/ /* Field Offsets */ #define FB_DCOFSEL_DC_COEF_SEL … /* Field Masks */ #define FM_DCOFSEL_DC_COEF_SEL … /* Field Values */ #define FV_DCOFSEL_DC_COEF_SEL_2_N8 … #define FV_DCOFSEL_DC_COEF_SEL_2_N9 … #define FV_DCOFSEL_DC_COEF_SEL_2_N10 … #define FV_DCOFSEL_DC_COEF_SEL_2_N11 … #define FV_DCOFSEL_DC_COEF_SEL_2_N12 … #define FV_DCOFSEL_DC_COEF_SEL_2_N13 … #define FV_DCOFSEL_DC_COEF_SEL_2_N14 … #define FV_DCOFSEL_DC_COEF_SEL_2_N15 … /* Register Masks */ #define RM_DCOFSEL_DC_COEF_SEL … /* Register Values */ #define RV_DCOFSEL_DC_COEF_SEL_2_N8 … #define RV_DCOFSEL_DC_COEF_SEL_2_N9 … #define RV_DCOFSEL_DC_COEF_SEL_2_N10 … #define RV_DCOFSEL_DC_COEF_SEL_2_N11 … #define RV_DCOFSEL_DC_COEF_SEL_2_N12 … #define RV_DCOFSEL_DC_COEF_SEL_2_N13 … #define RV_DCOFSEL_DC_COEF_SEL_2_N14 … #define RV_DCOFSEL_DC_COEF_SEL_2_N15 … /****************************** * R_PLLCTL9 (0x4E) * ******************************/ /* Field Offsets */ #define FB_PLLCTL9_REFDIV_PLL1 … /* Field Masks */ #define FM_PLLCTL9_REFDIV_PLL1 … /* Register Masks */ #define RM_PLLCTL9_REFDIV_PLL1 … /****************************** * R_PLLCTLA (0x4F) * ******************************/ /* Field Offsets */ #define FB_PLLCTLA_OUTDIV_PLL1 … /* Field Masks */ #define FM_PLLCTLA_OUTDIV_PLL1 … /* Register Masks */ #define RM_PLLCTLA_OUTDIV_PLL1 … /****************************** * R_PLLCTLB (0x50) * ******************************/ /* Field Offsets */ #define FB_PLLCTLB_FBDIV_PLL1L … /* Field Masks */ #define FM_PLLCTLB_FBDIV_PLL1L … /* Register Masks */ #define RM_PLLCTLB_FBDIV_PLL1L … /****************************** * R_PLLCTLC (0x51) * ******************************/ /* Field Offsets */ #define FB_PLLCTLC_FBDIV_PLL1H … /* Field Masks */ #define FM_PLLCTLC_FBDIV_PLL1H … /* Register Masks */ #define RM_PLLCTLC_FBDIV_PLL1H … /****************************** * R_PLLCTLD (0x52) * ******************************/ /* Field Offsets */ #define FB_PLLCTLD_RZ_PLL1 … #define FB_PLLCTLD_CP_PLL1 … /* Field Masks */ #define FM_PLLCTLD_RZ_PLL1 … #define FM_PLLCTLD_CP_PLL1 … /* Register Masks */ #define RM_PLLCTLD_RZ_PLL1 … #define RM_PLLCTLD_CP_PLL1 … /****************************** * R_PLLCTLE (0x53) * ******************************/ /* Field Offsets */ #define FB_PLLCTLE_REFDIV_PLL2 … /* Field Masks */ #define FM_PLLCTLE_REFDIV_PLL2 … /* Register Masks */ #define RM_PLLCTLE_REFDIV_PLL2 … /****************************** * R_PLLCTLF (0x54) * ******************************/ /* Field Offsets */ #define FB_PLLCTLF_OUTDIV_PLL2 … /* Field Masks */ #define FM_PLLCTLF_OUTDIV_PLL2 … /* Register Masks */ #define RM_PLLCTLF_OUTDIV_PLL2 … /******************************* * R_PLLCTL10 (0x55) * *******************************/ /* Field Offsets */ #define FB_PLLCTL10_FBDIV_PLL2L … /* Field Masks */ #define FM_PLLCTL10_FBDIV_PLL2L … /* Register Masks */ #define RM_PLLCTL10_FBDIV_PLL2L … /******************************* * R_PLLCTL11 (0x56) * *******************************/ /* Field Offsets */ #define FB_PLLCTL11_FBDIV_PLL2H … /* Field Masks */ #define FM_PLLCTL11_FBDIV_PLL2H … /* Register Masks */ #define RM_PLLCTL11_FBDIV_PLL2H … /******************************* * R_PLLCTL12 (0x57) * *******************************/ /* Field Offsets */ #define FB_PLLCTL12_RZ_PLL2 … #define FB_PLLCTL12_CP_PLL2 … /* Field Masks */ #define FM_PLLCTL12_RZ_PLL2 … #define FM_PLLCTL12_CP_PLL2 … /* Register Masks */ #define RM_PLLCTL12_RZ_PLL2 … #define RM_PLLCTL12_CP_PLL2 … /******************************* * R_PLLCTL1B (0x60) * *******************************/ /* Field Offsets */ #define FB_PLLCTL1B_VCOI_PLL2 … #define FB_PLLCTL1B_VCOI_PLL1 … /* Field Masks */ #define FM_PLLCTL1B_VCOI_PLL2 … #define FM_PLLCTL1B_VCOI_PLL1 … /* Register Masks */ #define RM_PLLCTL1B_VCOI_PLL2 … #define RM_PLLCTL1B_VCOI_PLL1 … /******************************* * R_PLLCTL1C (0x61) * *******************************/ /* Field Offsets */ #define FB_PLLCTL1C_PDB_PLL2 … #define FB_PLLCTL1C_PDB_PLL1 … /* Field Masks */ #define FM_PLLCTL1C_PDB_PLL2 … #define FM_PLLCTL1C_PDB_PLL1 … /* Field Values */ #define FV_PLLCTL1C_PDB_PLL2_ENABLE … #define FV_PLLCTL1C_PDB_PLL2_DISABLE … #define FV_PLLCTL1C_PDB_PLL1_ENABLE … #define FV_PLLCTL1C_PDB_PLL1_DISABLE … /* Register Masks */ #define RM_PLLCTL1C_PDB_PLL2 … #define RM_PLLCTL1C_PDB_PLL1 … /* Register Values */ #define RV_PLLCTL1C_PDB_PLL2_ENABLE … #define RV_PLLCTL1C_PDB_PLL2_DISABLE … #define RV_PLLCTL1C_PDB_PLL1_ENABLE … #define RV_PLLCTL1C_PDB_PLL1_DISABLE … /******************************* * R_TIMEBASE (0x77) * *******************************/ /* Field Offsets */ #define FB_TIMEBASE_DIVIDER … /* Field Masks */ #define FM_TIMEBASE_DIVIDER … /* Register Masks */ #define RM_TIMEBASE_DIVIDER … /***************************** * R_DEVIDL (0x7D) * *****************************/ /* Field Offsets */ #define FB_DEVIDL_DIDL … /* Field Masks */ #define FM_DEVIDL_DIDL … /* Register Masks */ #define RM_DEVIDL_DIDL … /***************************** * R_DEVIDH (0x7E) * *****************************/ /* Field Offsets */ #define FB_DEVIDH_DIDH … /* Field Masks */ #define FM_DEVIDH_DIDH … /* Register Masks */ #define RM_DEVIDH_DIDH … /**************************** * R_RESET (0x80) * ****************************/ /* Field Offsets */ #define FB_RESET … /* Field Masks */ #define FM_RESET … /* Field Values */ #define FV_RESET_ENABLE … /* Register Masks */ #define RM_RESET … /* Register Values */ #define RV_RESET_ENABLE … /******************************** * R_DACCRSTAT (0x8A) * ********************************/ /* Field Offsets */ #define FB_DACCRSTAT_DACCR_BUSY … /* Field Masks */ #define FM_DACCRSTAT_DACCR_BUSY … /* Register Masks */ #define RM_DACCRSTAT_DACCR_BUSY … /****************************** * R_PLLCTL0 (0x8E) * ******************************/ /* Field Offsets */ #define FB_PLLCTL0_PLL2_LOCK … #define FB_PLLCTL0_PLL1_LOCK … /* Field Masks */ #define FM_PLLCTL0_PLL2_LOCK … #define FM_PLLCTL0_PLL1_LOCK … /* Register Masks */ #define RM_PLLCTL0_PLL2_LOCK … #define RM_PLLCTL0_PLL1_LOCK … /******************************** * R_PLLREFSEL (0x8F) * ********************************/ /* Field Offsets */ #define FB_PLLREFSEL_PLL2_REF_SEL … #define FB_PLLREFSEL_PLL1_REF_SEL … /* Field Masks */ #define FM_PLLREFSEL_PLL2_REF_SEL … #define FM_PLLREFSEL_PLL1_REF_SEL … /* Field Values */ #define FV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1 … #define FV_PLLREFSEL_PLL2_REF_SEL_MCLK2 … #define FV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 … #define FV_PLLREFSEL_PLL1_REF_SEL_MCLK2 … /* Register Masks */ #define RM_PLLREFSEL_PLL2_REF_SEL … #define RM_PLLREFSEL_PLL1_REF_SEL … /* Register Values */ #define RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1 … #define RV_PLLREFSEL_PLL2_REF_SEL_MCLK2 … #define RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 … #define RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 … /******************************* * R_DACMBCEN (0xC7) * *******************************/ /* Field Offsets */ #define FB_DACMBCEN_MBCEN3 … #define FB_DACMBCEN_MBCEN2 … #define FB_DACMBCEN_MBCEN1 … /* Field Masks */ #define FM_DACMBCEN_MBCEN3 … #define FM_DACMBCEN_MBCEN2 … #define FM_DACMBCEN_MBCEN1 … /* Register Masks */ #define RM_DACMBCEN_MBCEN3 … #define RM_DACMBCEN_MBCEN2 … #define RM_DACMBCEN_MBCEN1 … /******************************** * R_DACMBCCTL (0xC8) * ********************************/ /* Field Offsets */ #define FB_DACMBCCTL_LVLMODE3 … #define FB_DACMBCCTL_WINSEL3 … #define FB_DACMBCCTL_LVLMODE2 … #define FB_DACMBCCTL_WINSEL2 … #define FB_DACMBCCTL_LVLMODE1 … #define FB_DACMBCCTL_WINSEL1 … /* Field Masks */ #define FM_DACMBCCTL_LVLMODE3 … #define FM_DACMBCCTL_WINSEL3 … #define FM_DACMBCCTL_LVLMODE2 … #define FM_DACMBCCTL_WINSEL2 … #define FM_DACMBCCTL_LVLMODE1 … #define FM_DACMBCCTL_WINSEL1 … /* Register Masks */ #define RM_DACMBCCTL_LVLMODE3 … #define RM_DACMBCCTL_WINSEL3 … #define RM_DACMBCCTL_LVLMODE2 … #define RM_DACMBCCTL_WINSEL2 … #define RM_DACMBCCTL_LVLMODE1 … #define RM_DACMBCCTL_WINSEL1 … /********************************* * R_DACMBCMUG1 (0xC9) * *********************************/ /* Field Offsets */ #define FB_DACMBCMUG1_PHASE … #define FB_DACMBCMUG1_MUGAIN … /* Field Masks */ #define FM_DACMBCMUG1_PHASE … #define FM_DACMBCMUG1_MUGAIN … /* Register Masks */ #define RM_DACMBCMUG1_PHASE … #define RM_DACMBCMUG1_MUGAIN … /********************************* * R_DACMBCTHR1 (0xCA) * *********************************/ /* Field Offsets */ #define FB_DACMBCTHR1_THRESH … /* Field Masks */ #define FM_DACMBCTHR1_THRESH … /* Register Masks */ #define RM_DACMBCTHR1_THRESH … /********************************* * R_DACMBCRAT1 (0xCB) * *********************************/ /* Field Offsets */ #define FB_DACMBCRAT1_RATIO … /* Field Masks */ #define FM_DACMBCRAT1_RATIO … /* Register Masks */ #define RM_DACMBCRAT1_RATIO … /********************************** * R_DACMBCATK1L (0xCC) * **********************************/ /* Field Offsets */ #define FB_DACMBCATK1L_TCATKL … /* Field Masks */ #define FM_DACMBCATK1L_TCATKL … /* Register Masks */ #define RM_DACMBCATK1L_TCATKL … /********************************** * R_DACMBCATK1H (0xCD) * **********************************/ /* Field Offsets */ #define FB_DACMBCATK1H_TCATKH … /* Field Masks */ #define FM_DACMBCATK1H_TCATKH … /* Register Masks */ #define RM_DACMBCATK1H_TCATKH … /********************************** * R_DACMBCREL1L (0xCE) * **********************************/ /* Field Offsets */ #define FB_DACMBCREL1L_TCRELL … /* Field Masks */ #define FM_DACMBCREL1L_TCRELL … /* Register Masks */ #define RM_DACMBCREL1L_TCRELL … /********************************** * R_DACMBCREL1H (0xCF) * **********************************/ /* Field Offsets */ #define FB_DACMBCREL1H_TCRELH … /* Field Masks */ #define FM_DACMBCREL1H_TCRELH … /* Register Masks */ #define RM_DACMBCREL1H_TCRELH … /********************************* * R_DACMBCMUG2 (0xD0) * *********************************/ /* Field Offsets */ #define FB_DACMBCMUG2_PHASE … #define FB_DACMBCMUG2_MUGAIN … /* Field Masks */ #define FM_DACMBCMUG2_PHASE … #define FM_DACMBCMUG2_MUGAIN … /* Register Masks */ #define RM_DACMBCMUG2_PHASE … #define RM_DACMBCMUG2_MUGAIN … /********************************* * R_DACMBCTHR2 (0xD1) * *********************************/ /* Field Offsets */ #define FB_DACMBCTHR2_THRESH … /* Field Masks */ #define FM_DACMBCTHR2_THRESH … /* Register Masks */ #define RM_DACMBCTHR2_THRESH … /********************************* * R_DACMBCRAT2 (0xD2) * *********************************/ /* Field Offsets */ #define FB_DACMBCRAT2_RATIO … /* Field Masks */ #define FM_DACMBCRAT2_RATIO … /* Register Masks */ #define RM_DACMBCRAT2_RATIO … /********************************** * R_DACMBCATK2L (0xD3) * **********************************/ /* Field Offsets */ #define FB_DACMBCATK2L_TCATKL … /* Field Masks */ #define FM_DACMBCATK2L_TCATKL … /* Register Masks */ #define RM_DACMBCATK2L_TCATKL … /********************************** * R_DACMBCATK2H (0xD4) * **********************************/ /* Field Offsets */ #define FB_DACMBCATK2H_TCATKH … /* Field Masks */ #define FM_DACMBCATK2H_TCATKH … /* Register Masks */ #define RM_DACMBCATK2H_TCATKH … /********************************** * R_DACMBCREL2L (0xD5) * **********************************/ /* Field Offsets */ #define FB_DACMBCREL2L_TCRELL … /* Field Masks */ #define FM_DACMBCREL2L_TCRELL … /* Register Masks */ #define RM_DACMBCREL2L_TCRELL … /********************************** * R_DACMBCREL2H (0xD6) * **********************************/ /* Field Offsets */ #define FB_DACMBCREL2H_TCRELH … /* Field Masks */ #define FM_DACMBCREL2H_TCRELH … /* Register Masks */ #define RM_DACMBCREL2H_TCRELH … /********************************* * R_DACMBCMUG3 (0xD7) * *********************************/ /* Field Offsets */ #define FB_DACMBCMUG3_PHASE … #define FB_DACMBCMUG3_MUGAIN … /* Field Masks */ #define FM_DACMBCMUG3_PHASE … #define FM_DACMBCMUG3_MUGAIN … /* Register Masks */ #define RM_DACMBCMUG3_PHASE … #define RM_DACMBCMUG3_MUGAIN … /********************************* * R_DACMBCTHR3 (0xD8) * *********************************/ /* Field Offsets */ #define FB_DACMBCTHR3_THRESH … /* Field Masks */ #define FM_DACMBCTHR3_THRESH … /* Register Masks */ #define RM_DACMBCTHR3_THRESH … /********************************* * R_DACMBCRAT3 (0xD9) * *********************************/ /* Field Offsets */ #define FB_DACMBCRAT3_RATIO … /* Field Masks */ #define FM_DACMBCRAT3_RATIO … /* Register Masks */ #define RM_DACMBCRAT3_RATIO … /********************************** * R_DACMBCATK3L (0xDA) * **********************************/ /* Field Offsets */ #define FB_DACMBCATK3L_TCATKL … /* Field Masks */ #define FM_DACMBCATK3L_TCATKL … /* Register Masks */ #define RM_DACMBCATK3L_TCATKL … /********************************** * R_DACMBCATK3H (0xDB) * **********************************/ /* Field Offsets */ #define FB_DACMBCATK3H_TCATKH … /* Field Masks */ #define FM_DACMBCATK3H_TCATKH … /* Register Masks */ #define RM_DACMBCATK3H_TCATKH … /********************************** * R_DACMBCREL3L (0xDC) * **********************************/ /* Field Offsets */ #define FB_DACMBCREL3L_TCRELL … /* Field Masks */ #define FM_DACMBCREL3L_TCRELL … /* Register Masks */ #define RM_DACMBCREL3L_TCRELL … /********************************** * R_DACMBCREL3H (0xDD) * **********************************/ /* Field Offsets */ #define FB_DACMBCREL3H_TCRELH … /* Field Masks */ #define FM_DACMBCREL3H_TCRELH … /* Register Masks */ #define RM_DACMBCREL3H_TCRELH … #endif /* __WOOKIE_H__ */
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