linux/sound/soc/codecs/wcd938x.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __WCD938X_H__
#define __WCD938X_H__
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>

#define WCD938X_BASE_ADDRESS
#define WCD938X_ANA_PAGE_REGISTER
#define WCD938X_ANA_BIAS
#define WCD938X_ANA_RX_SUPPLIES
#define WCD938X_RX_BIAS_EN_MASK
#define WCD938X_REGULATOR_MODE_MASK
#define WCD938X_REGULATOR_MODE_CLASS_AB
#define WCD938X_VNEG_EN_MASK
#define WCD938X_VPOS_EN_MASK
#define WCD938X_ANA_HPH
#define WCD938X_HPHR_REF_EN_MASK
#define WCD938X_HPHL_REF_EN_MASK
#define WCD938X_HPHR_EN_MASK
#define WCD938X_HPHL_EN_MASK
#define WCD938X_ANA_EAR
#define WCD938X_ANA_EAR_COMPANDER_CTL
#define WCD938X_GAIN_OVRD_REG_MASK
#define WCD938X_EAR_GAIN_MASK
#define WCD938X_ANA_TX_CH1
#define WCD938X_ANA_TX_CH2
#define WCD938X_HPF1_INIT_MASK
#define WCD938X_HPF2_INIT_MASK
#define WCD938X_ANA_TX_CH3
#define WCD938X_ANA_TX_CH4
#define WCD938X_HPF3_INIT_MASK
#define WCD938X_HPF4_INIT_MASK
#define WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC
#define WCD938X_ANA_MICB3_DSP_EN_LOGIC
#define WCD938X_ANA_MBHC_MECH
#define WCD938X_MBHC_L_DET_EN_MASK
#define WCD938X_MBHC_L_DET_EN
#define WCD938X_MBHC_GND_DET_EN_MASK
#define WCD938X_MBHC_MECH_DETECT_TYPE_MASK
#define WCD938X_MBHC_MECH_DETECT_TYPE_INS
#define WCD938X_MBHC_HPHL_PLUG_TYPE_MASK
#define WCD938X_MBHC_HPHL_PLUG_TYPE_NO
#define WCD938X_MBHC_GND_PLUG_TYPE_MASK
#define WCD938X_MBHC_GND_PLUG_TYPE_NO
#define WCD938X_MBHC_HSL_PULLUP_COMP_EN
#define WCD938X_MBHC_HSG_PULLUP_COMP_EN
#define WCD938X_MBHC_HPHL_100K_TO_GND_EN

#define WCD938X_ANA_MBHC_ELECT
#define WCD938X_ANA_MBHC_BD_ISRC_CTL_MASK
#define WCD938X_ANA_MBHC_BD_ISRC_100UA
#define WCD938X_ANA_MBHC_BD_ISRC_OFF
#define WCD938X_ANA_MBHC_BIAS_EN_MASK
#define WCD938X_ANA_MBHC_BIAS_EN
#define WCD938X_ANA_MBHC_ZDET
#define WCD938X_ANA_MBHC_RESULT_1
#define WCD938X_ANA_MBHC_RESULT_2
#define WCD938X_ANA_MBHC_RESULT_3
#define WCD938X_MBHC_BTN_RESULT_MASK
#define WCD938X_ANA_MBHC_BTN0
#define WCD938X_MBHC_BTN_VTH_MASK
#define WCD938X_ANA_MBHC_BTN1
#define WCD938X_ANA_MBHC_BTN2
#define WCD938X_ANA_MBHC_BTN3
#define WCD938X_ANA_MBHC_BTN4
#define WCD938X_ANA_MBHC_BTN5
#define WCD938X_VTH_MASK
#define WCD938X_ANA_MBHC_BTN6
#define WCD938X_ANA_MBHC_BTN7
#define WCD938X_ANA_MICB1
#define WCD938X_MICB_VOUT_MASK
#define WCD938X_MICB_EN_MASK
#define WCD938X_MICB_DISABLE
#define WCD938X_MICB_ENABLE
#define WCD938X_MICB_PULL_UP
#define WCD938X_MICB_PULL_DOWN
#define WCD938X_ANA_MICB2
#define WCD938X_ANA_MICB2_RAMP
#define WCD938X_RAMP_EN_MASK
#define WCD938X_RAMP_SHIFT_CTRL_MASK
#define WCD938X_ANA_MICB3
#define WCD938X_ANA_MICB4
#define WCD938X_BIAS_CTL
#define WCD938X_BIAS_VBG_FINE_ADJ
#define WCD938X_LDOL_VDDCX_ADJUST
#define WCD938X_LDOL_DISABLE_LDOL
#define WCD938X_MBHC_CTL_CLK
#define WCD938X_MBHC_CTL_ANA
#define WCD938X_MBHC_CTL_SPARE_1
#define WCD938X_MBHC_CTL_SPARE_2
#define WCD938X_MBHC_CTL_BCS
#define WCD938X_MBHC_MOISTURE_DET_FSM_STATUS
#define WCD938X_MBHC_TEST_CTL
#define WCD938X_LDOH_MODE
#define WCD938X_LDOH_EN_MASK
#define WCD938X_LDOH_BIAS
#define WCD938X_LDOH_STB_LOADS
#define WCD938X_LDOH_SLOWRAMP
#define WCD938X_MICB1_TEST_CTL_1
#define WCD938X_MICB1_TEST_CTL_2
#define WCD938X_MICB1_TEST_CTL_3
#define WCD938X_MICB2_TEST_CTL_1
#define WCD938X_MICB2_TEST_CTL_2
#define WCD938X_MICB2_TEST_CTL_3
#define WCD938X_MICB3_TEST_CTL_1
#define WCD938X_MICB3_TEST_CTL_2
#define WCD938X_MICB3_TEST_CTL_3
#define WCD938X_MICB4_TEST_CTL_1
#define WCD938X_MICB4_TEST_CTL_2
#define WCD938X_MICB4_TEST_CTL_3
#define WCD938X_TX_COM_ADC_VCM
#define WCD938X_TX_COM_BIAS_ATEST
#define WCD938X_TX_COM_SPARE1
#define WCD938X_TX_COM_SPARE2
#define WCD938X_TX_COM_TXFE_DIV_CTL
#define WCD938X_TX_COM_TXFE_DIV_START
#define WCD938X_TX_COM_SPARE3
#define WCD938X_TX_COM_SPARE4
#define WCD938X_TX_1_2_TEST_EN
#define WCD938X_TX_1_2_ADC_IB
#define WCD938X_TX_1_2_ATEST_REFCTL
#define WCD938X_TX_1_2_TEST_CTL
#define WCD938X_TX_1_2_TEST_BLK_EN1
#define WCD938X_TX_1_2_TXFE1_CLKDIV
#define WCD938X_TX_1_2_SAR2_ERR
#define WCD938X_TX_1_2_SAR1_ERR
#define WCD938X_TX_3_4_TEST_EN
#define WCD938X_TX_3_4_ADC_IB
#define WCD938X_TX_3_4_ATEST_REFCTL
#define WCD938X_TX_3_4_TEST_CTL
#define WCD938X_TX_3_4_TEST_BLK_EN3
#define WCD938X_TX_3_4_TXFE3_CLKDIV
#define WCD938X_TX_3_4_SAR4_ERR
#define WCD938X_TX_3_4_SAR3_ERR
#define WCD938X_TX_3_4_TEST_BLK_EN2
#define WCD938X_TX_3_4_TXFE2_CLKDIV
#define WCD938X_TX_3_4_SPARE1
#define WCD938X_TX_3_4_TEST_BLK_EN4
#define WCD938X_TX_3_4_TXFE4_CLKDIV
#define WCD938X_TX_3_4_SPARE2
#define WCD938X_CLASSH_MODE_1
#define WCD938X_CLASSH_MODE_2
#define WCD938X_CLASSH_MODE_3
#define WCD938X_CLASSH_CTRL_VCL_1
#define WCD938X_CLASSH_CTRL_VCL_2
#define WCD938X_CLASSH_CTRL_CCL_1
#define WCD938X_CLASSH_CTRL_CCL_2
#define WCD938X_CLASSH_CTRL_CCL_3
#define WCD938X_CLASSH_CTRL_CCL_4
#define WCD938X_CLASSH_CTRL_CCL_5
#define WCD938X_CLASSH_BUCK_TMUX_A_D
#define WCD938X_CLASSH_BUCK_SW_DRV_CNTL
#define WCD938X_CLASSH_SPARE
#define WCD938X_FLYBACK_EN
#define WCD938X_EN_CUR_DET_MASK
#define WCD938X_FLYBACK_VNEG_CTRL_1
#define WCD938X_FLYBACK_VNEG_CTRL_2
#define WCD938X_FLYBACK_VNEG_CTRL_3
#define WCD938X_FLYBACK_VNEG_CTRL_4
#define WCD938X_FLYBACK_VNEG_CTRL_5
#define WCD938X_FLYBACK_VNEG_CTRL_6
#define WCD938X_FLYBACK_VNEG_CTRL_7
#define WCD938X_FLYBACK_VNEG_CTRL_8
#define WCD938X_FLYBACK_VNEG_CTRL_9
#define WCD938X_FLYBACK_VNEGDAC_CTRL_1
#define WCD938X_FLYBACK_VNEGDAC_CTRL_2
#define WCD938X_FLYBACK_VNEGDAC_CTRL_3
#define WCD938X_FLYBACK_CTRL_1
#define WCD938X_FLYBACK_TEST_CTL
#define WCD938X_RX_AUX_SW_CTL
#define WCD938X_RX_PA_AUX_IN_CONN
#define WCD938X_RX_TIMER_DIV
#define WCD938X_RX_OCP_CTL
#define WCD938X_RX_OCP_COUNT
#define WCD938X_RX_BIAS_EAR_DAC
#define WCD938X_RX_BIAS_EAR_AMP
#define WCD938X_RX_BIAS_HPH_LDO
#define WCD938X_RX_BIAS_HPH_PA
#define WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2
#define WCD938X_RX_BIAS_HPH_RDAC_LDO
#define WCD938X_RX_BIAS_HPH_CNP1
#define WCD938X_RX_BIAS_HPH_LOWPOWER
#define WCD938X_RX_BIAS_AUX_DAC
#define WCD938X_RX_BIAS_AUX_AMP
#define WCD938X_RX_BIAS_VNEGDAC_BLEEDER
#define WCD938X_RX_BIAS_MISC
#define WCD938X_RX_BIAS_BUCK_RST
#define WCD938X_RX_BIAS_BUCK_VREF_ERRAMP
#define WCD938X_RX_BIAS_FLYB_ERRAMP
#define WCD938X_RX_BIAS_FLYB_BUFF
#define WCD938X_RX_BIAS_FLYB_MID_RST
#define WCD938X_HPH_L_STATUS
#define WCD938X_HPH_R_STATUS
#define WCD938X_HPH_CNP_EN
#define WCD938X_HPH_CNP_WG_CTL
#define WCD938X_HPH_CNP_WG_TIME
#define WCD938X_HPH_OCP_CTL
#define WCD938X_HPH_AUTO_CHOP
#define WCD938X_HPH_CHOP_CTL
#define WCD938X_HPH_PA_CTL1
#define WCD938X_HPH_PA_CTL2
#define WCD938X_HPHPA_GND_R_MASK
#define WCD938X_HPHPA_GND_L_MASK
#define WCD938X_HPH_L_EN
#define WCD938X_HPH_L_TEST
#define WCD938X_HPH_L_ATEST
#define WCD938X_HPH_R_EN
#define WCD938X_GAIN_SRC_SEL_MASK
#define WCD938X_GAIN_SRC_SEL_REGISTER
#define WCD938X_HPH_R_TEST
#define WCD938X_HPH_R_ATEST
#define WCD938X_HPHPA_GND_OVR_MASK
#define WCD938X_HPH_RDAC_CLK_CTL1
#define WCD938X_CHOP_CLK_EN_MASK
#define WCD938X_HPH_RDAC_CLK_CTL2
#define WCD938X_HPH_RDAC_LDO_CTL
#define WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL
#define WCD938X_HPH_REFBUFF_UHQA_CTL
#define WCD938X_HPH_REFBUFF_LP_CTL
#define WCD938X_PREREF_FLIT_BYPASS_MASK
#define WCD938X_HPH_L_DAC_CTL
#define WCD938X_HPH_R_DAC_CTL
#define WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL
#define WCD938X_HPH_SURGE_HPHLR_SURGE_EN
#define WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1
#define WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS
#define WCD938X_EAR_EAR_EN_REG
#define WCD938X_EAR_EAR_PA_CON
#define WCD938X_EAR_EAR_SP_CON
#define WCD938X_EAR_EAR_DAC_CON
#define WCD938X_DAC_SAMPLE_EDGE_SEL_MASK
#define WCD938X_EAR_EAR_CNP_FSM_CON
#define WCD938X_EAR_TEST_CTL
#define WCD938X_EAR_STATUS_REG_1
#define WCD938X_EAR_STATUS_REG_2
#define WCD938X_ANA_NEW_PAGE_REGISTER
#define WCD938X_HPH_NEW_ANA_HPH2
#define WCD938X_HPH_NEW_ANA_HPH3
#define WCD938X_SLEEP_CTL
#define WCD938X_SLEEP_WATCHDOG_CTL
#define WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL
#define WCD938X_MBHC_NEW_CTL_1
#define WCD938X_MBHC_CTL_RCO_EN_MASK
#define WCD938X_MBHC_CTL_RCO_EN
#define WCD938X_MBHC_BTN_DBNC_MASK
#define WCD938X_MBHC_BTN_DBNC_T_16_MS
#define WCD938X_MBHC_NEW_CTL_2
#define WCD938X_M_RTH_CTL_MASK
#define WCD938X_MBHC_HS_VREF_CTL_MASK
#define WCD938X_MBHC_HS_VREF_1P5_V
#define WCD938X_MBHC_NEW_PLUG_DETECT_CTL
#define WCD938X_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS

#define WCD938X_MBHC_NEW_ZDET_ANA_CTL
#define WCD938X_ZDET_RANGE_CTL_MASK
#define WCD938X_ZDET_MAXV_CTL_MASK
#define WCD938X_MBHC_NEW_ZDET_RAMP_CTL
#define WCD938X_MBHC_NEW_FSM_STATUS
#define WCD938X_MBHC_NEW_ADC_RESULT
#define WCD938X_TX_NEW_AMIC_MUX_CFG
#define WCD938X_AUX_AUXPA
#define WCD938X_AUXPA_CLK_EN_MASK
#define WCD938X_LDORXTX_MODE
#define WCD938X_LDORXTX_CONFIG
#define WCD938X_DIE_CRACK_DIE_CRK_DET_EN
#define WCD938X_DIE_CRACK_DIE_CRK_DET_OUT
#define WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L
#define WCD938X_HPH_NEW_INT_RDAC_VREF_CTL
#define WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R
#define WCD938X_HPH_RES_DIV_MASK
#define WCD938X_HPH_NEW_INT_PA_MISC1
#define WCD938X_HPH_NEW_INT_PA_MISC2
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC
#define WCD938X_HPH_NEW_INT_HPH_TIMER1
#define WCD938X_AUTOCHOP_TIMER_EN
#define WCD938X_HPH_NEW_INT_HPH_TIMER2
#define WCD938X_HPH_NEW_INT_HPH_TIMER3
#define WCD938X_HPH_NEW_INT_HPH_TIMER4
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC2
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC3
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW
#define WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI
#define WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP
#define WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP
#define WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL
#define WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL
#define WCD938X_MOISTURE_EN_POLLING_MASK
#define WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT
#define WCD938X_HSDET_PULLUP_C_MASK
#define WCD938X_MBHC_NEW_INT_SPARE_2
#define WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON
#define WCD938X_EAR_INT_NEW_CNP_VCM_CON1
#define WCD938X_EAR_INT_NEW_CNP_VCM_CON2
#define WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS
#define WCD938X_AUX_INT_EN_REG
#define WCD938X_AUX_INT_PA_CTRL
#define WCD938X_AUX_INT_SP_CTRL
#define WCD938X_AUX_INT_DAC_CTRL
#define WCD938X_AUX_INT_CLK_CTRL
#define WCD938X_AUX_INT_TEST_CTRL
#define WCD938X_AUX_INT_STATUS_REG
#define WCD938X_AUX_INT_MISC
#define WCD938X_LDORXTX_INT_BIAS
#define WCD938X_LDORXTX_INT_STB_LOADS_DTEST
#define WCD938X_LDORXTX_INT_TEST0
#define WCD938X_LDORXTX_INT_STARTUP_TIMER
#define WCD938X_LDORXTX_INT_TEST1
#define WCD938X_LDORXTX_INT_STATUS
#define WCD938X_SLEEP_INT_WATCHDOG_CTL_1
#define WCD938X_SLEEP_INT_WATCHDOG_CTL_2
#define WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1
#define WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP
#define WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1
#define WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L2
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L1
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L0
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP
#define WCD938X_DIGITAL_PAGE_REGISTER
#define WCD938X_DIGITAL_CHIP_ID0
#define WCD938X_DIGITAL_CHIP_ID1
#define WCD938X_DIGITAL_CHIP_ID2
#define WCD938X_DIGITAL_CHIP_ID3
#define WCD938X_DIGITAL_SWR_TX_CLK_RATE
#define WCD938X_DIGITAL_CDC_RST_CTL
#define WCD938X_DIGITAL_TOP_CLK_CFG
#define WCD938X_DIGITAL_CDC_ANA_CLK_CTL
#define WCD938X_ANA_RX_CLK_EN_MASK
#define WCD938X_ANA_RX_DIV2_CLK_EN_MASK
#define WCD938X_ANA_RX_DIV4_CLK_EN_MASK
#define WCD938X_ANA_TX_CLK_EN_MASK
#define WCD938X_ANA_TX_DIV2_CLK_EN_MASK
#define WCD938X_ANA_TX_DIV4_CLK_EN_MASK
#define WCD938X_DIGITAL_CDC_DIG_CLK_CTL
#define WCD938X_TXD3_CLK_EN_MASK
#define WCD938X_TXD2_CLK_EN_MASK
#define WCD938X_TXD1_CLK_EN_MASK
#define WCD938X_TXD0_CLK_EN_MASK
#define WCD938X_TX_CLK_EN_MASK
#define WCD938X_RXD2_CLK_EN_MASK
#define WCD938X_RXD1_CLK_EN_MASK
#define WCD938X_RXD0_CLK_EN_MASK
#define WCD938X_DIGITAL_SWR_RST_EN
#define WCD938X_DIGITAL_CDC_PATH_MODE
#define WCD938X_DIGITAL_CDC_RX_RST
#define WCD938X_DIGITAL_CDC_RX0_CTL
#define WCD938X_DEM_DITHER_ENABLE_MASK
#define WCD938X_DIGITAL_CDC_RX1_CTL
#define WCD938X_DIGITAL_CDC_RX2_CTL
#define WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1
#define WCD938X_TXD0_MODE_MASK
#define WCD938X_TXD1_MODE_MASK
#define WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3
#define WCD938X_TXD2_MODE_MASK
#define WCD938X_TXD3_MODE_MASK
#define WCD938X_DIGITAL_CDC_COMP_CTL_0
#define WCD938X_HPHR_COMP_EN_MASK
#define WCD938X_HPHL_COMP_EN_MASK
#define WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL
#define WCD938X_TX_SC_CLK_EN_MASK
#define WCD938X_DIGITAL_CDC_HPH_DSM_A1_0
#define WCD938X_DIGITAL_CDC_HPH_DSM_A1_1
#define WCD938X_DIGITAL_CDC_HPH_DSM_A2_0
#define WCD938X_DIGITAL_CDC_HPH_DSM_A2_1
#define WCD938X_DIGITAL_CDC_HPH_DSM_A3_0
#define WCD938X_DIGITAL_CDC_HPH_DSM_A3_1
#define WCD938X_DIGITAL_CDC_HPH_DSM_A4_0
#define WCD938X_DIGITAL_CDC_HPH_DSM_A4_1
#define WCD938X_DIGITAL_CDC_HPH_DSM_A5_0
#define WCD938X_DIGITAL_CDC_HPH_DSM_A5_1
#define WCD938X_DIGITAL_CDC_HPH_DSM_A6_0
#define WCD938X_DIGITAL_CDC_HPH_DSM_A7_0
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_0
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_1
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_2
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_3
#define WCD938X_DIGITAL_CDC_HPH_DSM_R1
#define WCD938X_DIGITAL_CDC_HPH_DSM_R2
#define WCD938X_DIGITAL_CDC_HPH_DSM_R3
#define WCD938X_DIGITAL_CDC_HPH_DSM_R4
#define WCD938X_DIGITAL_CDC_HPH_DSM_R5
#define WCD938X_DIGITAL_CDC_HPH_DSM_R6
#define WCD938X_DIGITAL_CDC_HPH_DSM_R7
#define WCD938X_DIGITAL_CDC_AUX_DSM_A1_0
#define WCD938X_DIGITAL_CDC_AUX_DSM_A1_1
#define WCD938X_DIGITAL_CDC_AUX_DSM_A2_0
#define WCD938X_DIGITAL_CDC_AUX_DSM_A2_1
#define WCD938X_DIGITAL_CDC_AUX_DSM_A3_0
#define WCD938X_DIGITAL_CDC_AUX_DSM_A3_1
#define WCD938X_DIGITAL_CDC_AUX_DSM_A4_0
#define WCD938X_DIGITAL_CDC_AUX_DSM_A4_1
#define WCD938X_DIGITAL_CDC_AUX_DSM_A5_0
#define WCD938X_DIGITAL_CDC_AUX_DSM_A5_1
#define WCD938X_DIGITAL_CDC_AUX_DSM_A6_0
#define WCD938X_DIGITAL_CDC_AUX_DSM_A7_0
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_0
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_1
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_2
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_3
#define WCD938X_DIGITAL_CDC_AUX_DSM_R1
#define WCD938X_DIGITAL_CDC_AUX_DSM_R2
#define WCD938X_DIGITAL_CDC_AUX_DSM_R3
#define WCD938X_DIGITAL_CDC_AUX_DSM_R4
#define WCD938X_DIGITAL_CDC_AUX_DSM_R5
#define WCD938X_DIGITAL_CDC_AUX_DSM_R6
#define WCD938X_DIGITAL_CDC_AUX_DSM_R7
#define WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0
#define WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2
#define WCD938X_DIGITAL_CDC_HPH_GAIN_CTL
#define WCD938X_HPHL_RX_EN_MASK
#define WCD938X_HPHR_RX_EN_MASK
#define WCD938X_DIGITAL_CDC_AUX_GAIN_CTL
#define WCD938X_AUX_EN_MASK
#define WCD938X_DIGITAL_CDC_EAR_PATH_CTL
#define WCD938X_DIGITAL_CDC_SWR_CLH
#define WCD938X_DIGITAL_SWR_CLH_BYP
#define WCD938X_DIGITAL_CDC_TX0_CTL
#define WCD938X_DIGITAL_CDC_TX1_CTL
#define WCD938X_DIGITAL_CDC_TX2_CTL
#define WCD938X_DIGITAL_CDC_TX_RST
#define WCD938X_DIGITAL_CDC_REQ_CTL
#define WCD938X_FS_RATE_4P8_MASK
#define WCD938X_NO_NOTCH_MASK
#define WCD938X_DIGITAL_CDC_RST
#define WCD938X_DIGITAL_CDC_AMIC_CTL
#define WCD938X_AMIC1_IN_SEL_DMIC
#define WCD938X_AMIC1_IN_SEL_AMIC
#define WCD938X_AMIC1_IN_SEL_MASK
#define WCD938X_AMIC3_IN_SEL_MASK
#define WCD938X_AMIC4_IN_SEL_MASK
#define WCD938X_AMIC5_IN_SEL_MASK
#define WCD938X_DIGITAL_CDC_DMIC_CTL
#define WCD938X_DMIC_CLK_SCALING_EN_MASK
#define WCD938X_DIGITAL_CDC_DMIC1_CTL
#define WCD938X_DMIC_CLK_EN_MASK
#define WCD938X_DIGITAL_CDC_DMIC2_CTL
#define WCD938X_DIGITAL_CDC_DMIC3_CTL
#define WCD938X_DIGITAL_CDC_DMIC4_CTL
#define WCD938X_DIGITAL_EFUSE_PRG_CTL
#define WCD938X_DIGITAL_EFUSE_CTL
#define WCD938X_DIGITAL_CDC_DMIC_RATE_1_2
#define WCD938X_DIGITAL_CDC_DMIC_RATE_3_4
#define WCD938X_DMIC1_RATE_MASK
#define WCD938X_DMIC2_RATE_MASK
#define WCD938X_DMIC3_RATE_MASK
#define WCD938X_DMIC4_RATE_MASK
#define WCD938X_DMIC4_RATE_2P4MHZ

#define WCD938X_DIGITAL_PDM_WD_CTL0
#define WCD938X_PDM_WD_EN_MASK
#define WCD938X_DIGITAL_PDM_WD_CTL1
#define WCD938X_DIGITAL_PDM_WD_CTL2
#define WCD938X_AUX_PDM_WD_EN_MASK
#define WCD938X_DIGITAL_INTR_MODE
#define WCD938X_DIGITAL_INTR_MASK_0
#define WCD938X_DIGITAL_INTR_MASK_1
#define WCD938X_DIGITAL_INTR_MASK_2
#define WCD938X_DIGITAL_INTR_STATUS_0
#define WCD938X_DIGITAL_INTR_STATUS_1
#define WCD938X_DIGITAL_INTR_STATUS_2
#define WCD938X_DIGITAL_INTR_CLEAR_0
#define WCD938X_DIGITAL_INTR_CLEAR_1
#define WCD938X_DIGITAL_INTR_CLEAR_2
#define WCD938X_DIGITAL_INTR_LEVEL_0
#define WCD938X_DIGITAL_INTR_LEVEL_1
#define WCD938X_DIGITAL_INTR_LEVEL_2
#define WCD938X_DIGITAL_INTR_SET_0
#define WCD938X_DIGITAL_INTR_SET_1
#define WCD938X_DIGITAL_INTR_SET_2
#define WCD938X_DIGITAL_INTR_TEST_0
#define WCD938X_DIGITAL_INTR_TEST_1
#define WCD938X_DIGITAL_INTR_TEST_2
#define WCD938X_DIGITAL_TX_MODE_DBG_EN
#define WCD938X_DIGITAL_TX_MODE_DBG_0_1
#define WCD938X_DIGITAL_TX_MODE_DBG_2_3
#define WCD938X_DIGITAL_LB_IN_SEL_CTL
#define WCD938X_DIGITAL_LOOP_BACK_MODE
#define WCD938X_DIGITAL_SWR_DAC_TEST
#define WCD938X_DIGITAL_SWR_HM_TEST_RX_0
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_0
#define WCD938X_DIGITAL_SWR_HM_TEST_RX_1
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_1
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_2
#define WCD938X_DIGITAL_SWR_HM_TEST_0
#define WCD938X_DIGITAL_SWR_HM_TEST_1
#define WCD938X_DIGITAL_PAD_CTL_SWR_0
#define WCD938X_DIGITAL_PAD_CTL_SWR_1
#define WCD938X_DIGITAL_I2C_CTL
#define WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE
#define WCD938X_DIGITAL_EFUSE_TEST_CTL_0
#define WCD938X_DIGITAL_EFUSE_TEST_CTL_1
#define WCD938X_DIGITAL_EFUSE_T_DATA_0
#define WCD938X_DIGITAL_EFUSE_T_DATA_1
#define WCD938X_DIGITAL_PAD_CTL_PDM_RX0
#define WCD938X_DIGITAL_PAD_CTL_PDM_RX1
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX0
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX1
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX2
#define WCD938X_DIGITAL_PAD_INP_DIS_0
#define WCD938X_DIGITAL_PAD_INP_DIS_1
#define WCD938X_DIGITAL_DRIVE_STRENGTH_0
#define WCD938X_DIGITAL_DRIVE_STRENGTH_1
#define WCD938X_DIGITAL_DRIVE_STRENGTH_2
#define WCD938X_DIGITAL_RX_DATA_EDGE_CTL
#define WCD938X_DIGITAL_TX_DATA_EDGE_CTL
#define WCD938X_DIGITAL_GPIO_MODE
#define WCD938X_DIGITAL_PIN_CTL_OE
#define WCD938X_DIGITAL_PIN_CTL_DATA_0
#define WCD938X_DIGITAL_PIN_CTL_DATA_1
#define WCD938X_DIGITAL_PIN_STATUS_0
#define WCD938X_DIGITAL_PIN_STATUS_1
#define WCD938X_DIGITAL_DIG_DEBUG_CTL
#define WCD938X_DIGITAL_DIG_DEBUG_EN
#define WCD938X_DIGITAL_ANA_CSR_DBG_ADD
#define WCD938X_DIGITAL_ANA_CSR_DBG_CTL
#define WCD938X_DIGITAL_SSP_DBG
#define WCD938X_DIGITAL_MODE_STATUS_0
#define WCD938X_DIGITAL_MODE_STATUS_1
#define WCD938X_DIGITAL_SPARE_0
#define WCD938X_DIGITAL_SPARE_1
#define WCD938X_DIGITAL_SPARE_2
#define WCD938X_DIGITAL_EFUSE_REG_0
#define WCD938X_ID_MASK
#define WCD938X_DIGITAL_EFUSE_REG_1
#define WCD938X_DIGITAL_EFUSE_REG_2
#define WCD938X_DIGITAL_EFUSE_REG_3
#define WCD938X_DIGITAL_EFUSE_REG_4
#define WCD938X_DIGITAL_EFUSE_REG_5
#define WCD938X_DIGITAL_EFUSE_REG_6
#define WCD938X_DIGITAL_EFUSE_REG_7
#define WCD938X_DIGITAL_EFUSE_REG_8
#define WCD938X_DIGITAL_EFUSE_REG_9
#define WCD938X_DIGITAL_EFUSE_REG_10
#define WCD938X_DIGITAL_EFUSE_REG_11
#define WCD938X_DIGITAL_EFUSE_REG_12
#define WCD938X_DIGITAL_EFUSE_REG_13
#define WCD938X_DIGITAL_EFUSE_REG_14
#define WCD938X_DIGITAL_EFUSE_REG_15
#define WCD938X_DIGITAL_EFUSE_REG_16
#define WCD938X_DIGITAL_EFUSE_REG_17
#define WCD938X_DIGITAL_EFUSE_REG_18
#define WCD938X_DIGITAL_EFUSE_REG_19
#define WCD938X_DIGITAL_EFUSE_REG_20
#define WCD938X_DIGITAL_EFUSE_REG_21
#define WCD938X_DIGITAL_EFUSE_REG_22
#define WCD938X_DIGITAL_EFUSE_REG_23
#define WCD938X_DIGITAL_EFUSE_REG_24
#define WCD938X_DIGITAL_EFUSE_REG_25
#define WCD938X_DIGITAL_EFUSE_REG_26
#define WCD938X_DIGITAL_EFUSE_REG_27
#define WCD938X_DIGITAL_EFUSE_REG_28
#define WCD938X_DIGITAL_EFUSE_REG_29
#define WCD938X_DIGITAL_EFUSE_REG_30
#define WCD938X_DIGITAL_EFUSE_REG_31
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_0
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_1
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_2
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_3
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_4
#define WCD938X_DIGITAL_DEM_BYPASS_DATA0
#define WCD938X_DIGITAL_DEM_BYPASS_DATA1
#define WCD938X_DIGITAL_DEM_BYPASS_DATA2
#define WCD938X_DIGITAL_DEM_BYPASS_DATA3
#define WCD938X_MAX_REGISTER

#define WCD938X_MAX_SWR_PORTS
#define WCD938X_MAX_TX_SWR_PORTS
#define WCD938X_MAX_SWR_CH_IDS

struct wcd938x_sdw_ch_info {};

#define WCD_SDW_CH(id, pn, cmask)

enum wcd938x_tx_sdw_ports {};

enum wcd938x_tx_sdw_channels {};

enum wcd938x_rx_sdw_ports {};

enum wcd938x_rx_sdw_channels {};

struct wcd938x_priv;
struct wcd938x_sdw_priv {};

#if IS_ENABLED(CONFIG_SND_SOC_WCD938X_SDW)
int wcd938x_sdw_free(struct wcd938x_sdw_priv *wcd,
		     struct snd_pcm_substream *substream,
		     struct snd_soc_dai *dai);
int wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv *wcd,
			       struct snd_soc_dai *dai,
			       void *stream, int direction);
int wcd938x_sdw_hw_params(struct wcd938x_sdw_priv *wcd,
			  struct snd_pcm_substream *substream,
			  struct snd_pcm_hw_params *params,
			  struct snd_soc_dai *dai);

struct device *wcd938x_sdw_device_get(struct device_node *np);
int wcd938x_swr_get_current_bank(struct sdw_slave *sdev);

#else

static inline int wcd938x_sdw_free(struct wcd938x_sdw_priv *wcd,
		     struct snd_pcm_substream *substream,
		     struct snd_soc_dai *dai)
{
	return -EOPNOTSUPP;
}

static inline int wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv *wcd,
			       struct snd_soc_dai *dai,
			       void *stream, int direction)
{
	return -EOPNOTSUPP;
}

static inline int wcd938x_sdw_hw_params(struct wcd938x_sdw_priv *wcd,
			  struct snd_pcm_substream *substream,
			  struct snd_pcm_hw_params *params,
			  struct snd_soc_dai *dai)
{
	return -EOPNOTSUPP;
}

static inline struct device *wcd938x_sdw_device_get(struct device_node *np)
{
	return NULL;
}

static inline int wcd938x_swr_get_current_bank(struct sdw_slave *sdev)
{
	return 0;
}
#endif /* CONFIG_SND_SOC_WCD938X_SDW */
#endif /* __WCD938X_H__ */