linux/include/dt-bindings/clock/qcom,sm8550-gpucc.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H

/* GPU_CC clocks */
#define GPU_CC_AHB_CLK …
#define GPU_CC_CRC_AHB_CLK …
#define GPU_CC_CX_FF_CLK …
#define GPU_CC_CX_GMU_CLK …
#define GPU_CC_CXO_AON_CLK …
#define GPU_CC_CXO_CLK …
#define GPU_CC_DEMET_CLK …
#define GPU_CC_DEMET_DIV_CLK_SRC …
#define GPU_CC_FF_CLK_SRC …
#define GPU_CC_FREQ_MEASURE_CLK …
#define GPU_CC_GMU_CLK_SRC …
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK …
#define GPU_CC_HUB_AON_CLK …
#define GPU_CC_HUB_CLK_SRC …
#define GPU_CC_HUB_CX_INT_CLK …
#define GPU_CC_MEMNOC_GFX_CLK …
#define GPU_CC_MND1X_0_GFX3D_CLK …
#define GPU_CC_MND1X_1_GFX3D_CLK …
#define GPU_CC_PLL0 …
#define GPU_CC_PLL1 …
#define GPU_CC_SLEEP_CLK …
#define GPU_CC_XO_CLK_SRC …
#define GPU_CC_XO_DIV_CLK_SRC …

/* GPU_CC power domains */
#define GPU_CC_CX_GDSC …
#define GPU_CC_GX_GDSC …

/* GPU_CC resets */
#define GPUCC_GPU_CC_ACD_BCR …
#define GPUCC_GPU_CC_CX_BCR …
#define GPUCC_GPU_CC_FAST_HUB_BCR …
#define GPUCC_GPU_CC_FF_BCR …
#define GPUCC_GPU_CC_GFX3D_AON_BCR …
#define GPUCC_GPU_CC_GMU_BCR …
#define GPUCC_GPU_CC_GX_BCR …
#define GPUCC_GPU_CC_XO_BCR …

#endif