linux/sound/soc/codecs/wm8974.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * wm8974.h  --  WM8974 Soc Audio driver
 */

#ifndef _WM8974_H
#define _WM8974_H

/* WM8974 register space */

#define WM8974_RESET
#define WM8974_POWER1
#define WM8974_POWER2
#define WM8974_POWER3
#define WM8974_IFACE
#define WM8974_COMP
#define WM8974_CLOCK
#define WM8974_ADD
#define WM8974_GPIO
#define WM8974_DAC
#define WM8974_DACVOL
#define WM8974_ADC
#define WM8974_ADCVOL
#define WM8974_EQ1
#define WM8974_EQ2
#define WM8974_EQ3
#define WM8974_EQ4
#define WM8974_EQ5
#define WM8974_DACLIM1
#define WM8974_DACLIM2
#define WM8974_NOTCH1
#define WM8974_NOTCH2
#define WM8974_NOTCH3
#define WM8974_NOTCH4
#define WM8974_ALC1
#define WM8974_ALC2
#define WM8974_ALC3
#define WM8974_NGATE
#define WM8974_PLLN
#define WM8974_PLLK1
#define WM8974_PLLK2
#define WM8974_PLLK3
#define WM8974_ATTEN
#define WM8974_INPUT
#define WM8974_INPPGA
#define WM8974_ADCBOOST
#define WM8974_OUTPUT
#define WM8974_SPKMIX
#define WM8974_SPKVOL
#define WM8974_MONOMIX

#define WM8974_CACHEREGNUM

/* Clock divider Id's */
#define WM8974_OPCLKDIV
#define WM8974_MCLKDIV
#define WM8974_BCLKDIV

/* PLL Out dividers */
#define WM8974_OPCLKDIV_1
#define WM8974_OPCLKDIV_2
#define WM8974_OPCLKDIV_3
#define WM8974_OPCLKDIV_4

/* BCLK clock dividers */
#define WM8974_BCLKDIV_1
#define WM8974_BCLKDIV_2
#define WM8974_BCLKDIV_4
#define WM8974_BCLKDIV_8
#define WM8974_BCLKDIV_16
#define WM8974_BCLKDIV_32

/* MCLK clock dividers */
#define WM8974_MCLKDIV_1
#define WM8974_MCLKDIV_1_5
#define WM8974_MCLKDIV_2
#define WM8974_MCLKDIV_3
#define WM8974_MCLKDIV_4
#define WM8974_MCLKDIV_6
#define WM8974_MCLKDIV_8
#define WM8974_MCLKDIV_12

#endif