linux/drivers/clk/ralink/clk-mt7621.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Mediatek MT7621 Clock Driver
 * Author: Sergio Paracuellos <[email protected]>
 */

#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <dt-bindings/clock/mt7621-clk.h>
#include <dt-bindings/reset/mt7621-reset.h>

/* Configuration registers */
#define SYSC_REG_SYSTEM_CONFIG0 …
#define SYSC_REG_SYSTEM_CONFIG1 …
#define SYSC_REG_CLKCFG0 …
#define SYSC_REG_CLKCFG1 …
#define SYSC_REG_RESET_CTRL …
#define SYSC_REG_CUR_CLK_STS …
#define MEMC_REG_CPU_PLL …

#define XTAL_MODE_SEL_MASK …
#define CPU_CLK_SEL_MASK …
#define CUR_CPU_FDIV_MASK …
#define CUR_CPU_FFRAC_MASK …
#define CPU_PLL_PREDIV_MASK …
#define CPU_PLL_FBDIV_MASK …

struct mt7621_clk_priv { … };

struct mt7621_clk { … };

struct mt7621_fixed_clk { … };

struct mt7621_gate { … };

#define GATE(_id, _name, _pname, _shift) …

static struct mt7621_gate mt7621_gates[] = …;

static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw)
{ … }

static int mt7621_gate_enable(struct clk_hw *hw)
{ … }

static void mt7621_gate_disable(struct clk_hw *hw)
{ … }

static int mt7621_gate_is_enabled(struct clk_hw *hw)
{ … }

static const struct clk_ops mt7621_gate_ops = …;

static int mt7621_gate_ops_init(struct device *dev,
				struct mt7621_gate *sclk)
{ … }

static int mt7621_register_gates(struct device *dev,
				 struct clk_hw_onecell_data *clk_data,
				 struct mt7621_clk_priv *priv)
{ … }

#define FIXED(_id, _name, _rate) …

static struct mt7621_fixed_clk mt7621_fixed_clks[] = …;

static int mt7621_register_fixed_clocks(struct device *dev,
					struct clk_hw_onecell_data *clk_data)
{ … }

static inline struct mt7621_clk *to_mt7621_clk(struct clk_hw *hw)
{ … }

static unsigned long mt7621_xtal_recalc_rate(struct clk_hw *hw,
					     unsigned long parent_rate)
{ … }

static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw,
					    unsigned long xtal_clk)
{ … }

static unsigned long mt7621_bus_recalc_rate(struct clk_hw *hw,
					    unsigned long parent_rate)
{ … }

#define CLK_BASE(_name, _parent, _recalc) …

static struct mt7621_clk mt7621_clks_base[] = …;

static struct clk_hw *mt7621_clk_early[MT7621_CLK_MAX];

static int mt7621_register_early_clocks(struct device_node *np,
					struct clk_hw_onecell_data *clk_data,
					struct mt7621_clk_priv *priv)
{ … }

static void __init mt7621_clk_init(struct device_node *node)
{ … }
CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);

struct mt7621_rst { … };

static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev)
{ … }

static int mt7621_assert_device(struct reset_controller_dev *rcdev,
				unsigned long id)
{ … }

static int mt7621_deassert_device(struct reset_controller_dev *rcdev,
				  unsigned long id)
{ … }

static int mt7621_reset_device(struct reset_controller_dev *rcdev,
			       unsigned long id)
{ … }

static int mt7621_rst_xlate(struct reset_controller_dev *rcdev,
			    const struct of_phandle_args *reset_spec)
{ … }

static const struct reset_control_ops reset_ops = …;

static int mt7621_reset_init(struct device *dev, struct regmap *sysc)
{ … }

static int mt7621_clk_probe(struct platform_device *pdev)
{ … }

static const struct of_device_id mt7621_clk_of_match[] = …;

static struct platform_driver mt7621_clk_driver = …;

static int __init mt7621_clk_reset_init(void)
{ … }
arch_initcall(mt7621_clk_reset_init);