linux/drivers/clk/renesas/clk-rz.c

// SPDX-License-Identifier: GPL-2.0
/*
 * RZ/A1 Core CPG Clocks
 *
 * Copyright (C) 2013 Ideas On Board SPRL
 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>

#define CPG_FRQCR …
#define CPG_FRQCR2 …

#define PPR0 …
#define PIBC0 …

#define MD_CLK(x) …

/* -----------------------------------------------------------------------------
 * Initialization
 */

static u16 __init rz_cpg_read_mode_pins(void)
{ … }

static struct clk * __init
rz_cpg_register_clock(struct device_node *np, void __iomem *base,
		      const char *name)
{ … }

static void __init rz_cpg_clocks_init(struct device_node *np)
{ … }
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);