linux/drivers/clk/renesas/r7s9210-cpg-mssr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * R7S9210 Clock Pulse Generator / Module Standby
 *
 * Based on r8a7795-cpg-mssr.c
 *
 * Copyright (C) 2018 Chris Brandt
 * Copyright (C) 2018 Renesas Electronics Corp.
 *
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
#include "renesas-cpg-mssr.h"

#define CPG_FRQCR …

static u8 cpg_mode;

/* Internal Clock ratio table */
static const struct { … } ratio_tab[5] = …;

enum rz_clk_types { … };

enum clk_ids { … };

static struct cpg_core_clk r7s9210_early_core_clks[] = …;

static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = …;

static struct cpg_core_clk r7s9210_core_clks[] = …;

static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = …;

/* The clock dividers in the table vary based on DT and register settings */
static void __init r7s9210_update_clk_table(struct clk *extal_clk,
					    void __iomem *base)
{ … }

static struct clk * __init rza2_cpg_clk_register(struct device *dev,
	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
	struct clk **clks, void __iomem *base,
	struct raw_notifier_head *notifiers)
{ … }

const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = …;

static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
{ … }

CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr",
		      r7s9210_cpg_mssr_early_init);