linux/include/dt-bindings/clock/r8a774b1-cpg-mssr.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright (C) 2019 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r8a774b1 CPG Core Clocks */
#define R8A774B1_CLK_Z …
#define R8A774B1_CLK_ZG …
#define R8A774B1_CLK_ZTR …
#define R8A774B1_CLK_ZTRD2 …
#define R8A774B1_CLK_ZT …
#define R8A774B1_CLK_ZX …
#define R8A774B1_CLK_S0D1 …
#define R8A774B1_CLK_S0D2 …
#define R8A774B1_CLK_S0D3 …
#define R8A774B1_CLK_S0D4 …
#define R8A774B1_CLK_S0D6 …
#define R8A774B1_CLK_S0D8 …
#define R8A774B1_CLK_S0D12 …
#define R8A774B1_CLK_S1D2 …
#define R8A774B1_CLK_S1D4 …
#define R8A774B1_CLK_S2D1 …
#define R8A774B1_CLK_S2D2 …
#define R8A774B1_CLK_S2D4 …
#define R8A774B1_CLK_S3D1 …
#define R8A774B1_CLK_S3D2 …
#define R8A774B1_CLK_S3D4 …
#define R8A774B1_CLK_LB …
#define R8A774B1_CLK_CL …
#define R8A774B1_CLK_ZB3 …
#define R8A774B1_CLK_ZB3D2 …
#define R8A774B1_CLK_CR …
#define R8A774B1_CLK_DDR …
#define R8A774B1_CLK_SD0H …
#define R8A774B1_CLK_SD0 …
#define R8A774B1_CLK_SD1H …
#define R8A774B1_CLK_SD1 …
#define R8A774B1_CLK_SD2H …
#define R8A774B1_CLK_SD2 …
#define R8A774B1_CLK_SD3H …
#define R8A774B1_CLK_SD3 …
#define R8A774B1_CLK_RPC …
#define R8A774B1_CLK_RPCD2 …
#define R8A774B1_CLK_MSO …
#define R8A774B1_CLK_HDMI …
#define R8A774B1_CLK_CSI0 …
#define R8A774B1_CLK_CP …
#define R8A774B1_CLK_CPEX …
#define R8A774B1_CLK_R …
#define R8A774B1_CLK_OSC …
#define R8A774B1_CLK_CANFD …

#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */