linux/drivers/clk/renesas/r8a77470-cpg-mssr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a77470 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 */

#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>

#include <dt-bindings/clock/r8a77470-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"

enum clk_ids { … };

static const struct cpg_core_clk r8a77470_core_clks[] __initconst = …;

static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = …;

static const unsigned int r8a77470_crit_mod_clks[] __initconst = …;

/*
 * CPG Clock Data
 */

/*
 *    MD	EXTAL		PLL0	PLL1	PLL3
 * 14 13	(MHz)		*1	*2
 *---------------------------------------------------
 * 0  0		20		x80	x78	x50
 * 0  1		26		x60	x60	x56
 * 1  0		Prohibited setting
 * 1  1		30		x52	x52	x50
 *
 * *1 :	Table 7.4 indicates VCO output (PLL0 = VCO)
 * *2 :	Table 7.4 indicates VCO output (PLL1 = VCO)
 */
#define CPG_PLL_CONFIG_INDEX(md) …

static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = …;

static int __init r8a77470_cpg_mssr_init(struct device *dev)
{ … }

const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = …;