linux/drivers/clk/renesas/clk-r8a7778.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a7778 Core CPG Clocks
 *
 * Copyright (C) 2014  Ulrich Hecht
 */

#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/soc/renesas/rcar-rst.h>

/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
static const struct { … } r8a7778_rates[] __initconst = …;

/* Clock dividers per bits 1 and 2 of MODEMR */
static const struct { … } r8a7778_divs[6] __initconst = …;

static u32 cpg_mode_rates __initdata;
static u32 cpg_mode_divs __initdata;

static struct clk * __init
r8a7778_cpg_register_clock(struct device_node *np, const char *name)
{ … }


static void __init r8a7778_cpg_clocks_init(struct device_node *np)
{ … }

CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
	       r8a7778_cpg_clocks_init);