linux/drivers/clk/renesas/r8a7745-cpg-mssr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a7745 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2016 Cogent Embedded Inc.
 */

#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>

#include <dt-bindings/clock/r8a7745-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"

enum clk_ids { … };

static const struct cpg_core_clk r8a7745_core_clks[] __initconst = …;

static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = …;

static const unsigned int r8a7745_crit_mod_clks[] __initconst = …;

/*
 * CPG Clock Data
 */

/*
 *    MD	EXTAL		PLL0	PLL1	PLL3
 * 14 13 19	(MHz)		*1	*2
 *---------------------------------------------------
 * 0  0  1	15		x200/3	x208/2	x88
 * 0  1  1	20		x150/3	x156/2	x66
 * 1  0  1	26 / 2		x230/3	x240/2	x102
 * 1  1  1	30 / 2		x200/3	x208/2	x88
 *
 * *1 :	Table 7.5b indicates VCO output (PLL0 = VCO/3)
 * *2 :	Table 7.5b indicates VCO output (PLL1 = VCO/2)
 */
#define CPG_PLL_CONFIG_INDEX(md) …

static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = …;

static int __init r8a7745_cpg_mssr_init(struct device *dev)
{ … }

const struct cpg_mssr_info r8a7745_cpg_mssr_info __initconst = …;