linux/drivers/clk/renesas/r8a774c0-cpg-mssr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a774c0 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 *
 * Based on r8a77990-cpg-mssr.c
 *
 * Copyright (C) 2015 Glider bvba
 * Copyright (C) 2015 Renesas Electronics Corp.
 */

#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>

#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"

enum clk_ids { … };

static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = …;

static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = …;

static const unsigned int r8a774c0_crit_mod_clks[] __initconst = …;

/*
 * CPG Clock Data
 */

/*
 * MD19		EXTAL (MHz)	PLL0		PLL1		PLL3
 *--------------------------------------------------------------------
 * 0		48 x 1		x100/1		x100/3		x100/3
 * 1		48 x 1		x100/1		x100/3		 x58/3
 */
#define CPG_PLL_CONFIG_INDEX(md) …

static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = …;

static int __init r8a774c0_cpg_mssr_init(struct device *dev)
{ … }

const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = …;