// SPDX-License-Identifier: GPL-2.0 /* * MTMIPS SoCs Clock Driver * Author: Sergio Paracuellos <[email protected]> */ #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset-controller.h> #include <linux/slab.h> /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG … #define SYSC_REG_CLKCFG0 … #define SYSC_REG_RESET_CTRL … #define SYSC_REG_CPU_SYS_CLKCFG … #define SYSC_REG_CPLL_CONFIG0 … #define SYSC_REG_CPLL_CONFIG1 … /* RT2880 SoC */ #define RT2880_CONFIG_CPUCLK_SHIFT … #define RT2880_CONFIG_CPUCLK_MASK … #define RT2880_CONFIG_CPUCLK_250 … #define RT2880_CONFIG_CPUCLK_266 … #define RT2880_CONFIG_CPUCLK_280 … #define RT2880_CONFIG_CPUCLK_300 … /* RT305X SoC */ #define RT305X_SYSCFG_CPUCLK_SHIFT … #define RT305X_SYSCFG_CPUCLK_MASK … #define RT305X_SYSCFG_CPUCLK_LOW … #define RT305X_SYSCFG_CPUCLK_HIGH … /* RT3352 SoC */ #define RT3352_SYSCFG0_CPUCLK_SHIFT … #define RT3352_SYSCFG0_CPUCLK_MASK … #define RT3352_SYSCFG0_CPUCLK_LOW … #define RT3352_SYSCFG0_CPUCLK_HIGH … /* RT3383 SoC */ #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 … #define RT3883_SYSCFG0_CPUCLK_SHIFT … #define RT3883_SYSCFG0_CPUCLK_MASK … #define RT3883_SYSCFG0_CPUCLK_250 … #define RT3883_SYSCFG0_CPUCLK_384 … #define RT3883_SYSCFG0_CPUCLK_480 … #define RT3883_SYSCFG0_CPUCLK_500 … /* RT5350 SoC */ #define RT5350_CLKCFG0_XTAL_SEL … #define RT5350_SYSCFG0_CPUCLK_SHIFT … #define RT5350_SYSCFG0_CPUCLK_MASK … #define RT5350_SYSCFG0_CPUCLK_360 … #define RT5350_SYSCFG0_CPUCLK_320 … #define RT5350_SYSCFG0_CPUCLK_300 … /* MT7620 and MT76x8 SoCs */ #define MT7620_XTAL_FREQ_SEL … #define CPLL_CFG0_SW_CFG … #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT … #define CPLL_CFG0_PLL_MULT_RATIO_MASK … #define CPLL_CFG0_LC_CURFCK … #define CPLL_CFG0_BYPASS_REF_CLK … #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT … #define CPLL_CFG0_PLL_DIV_RATIO_MASK … #define CPLL_CFG1_CPU_AUX1 … #define CPLL_CFG1_CPU_AUX0 … #define CLKCFG0_PERI_CLK_SEL … #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT … #define CPU_SYS_CLKCFG_OCP_RATIO_MASK … #define CPU_SYS_CLKCFG_OCP_RATIO_1 … #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 … #define CPU_SYS_CLKCFG_OCP_RATIO_2 … #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 … #define CPU_SYS_CLKCFG_OCP_RATIO_3 … #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 … #define CPU_SYS_CLKCFG_OCP_RATIO_4 … #define CPU_SYS_CLKCFG_OCP_RATIO_5 … #define CPU_SYS_CLKCFG_OCP_RATIO_10 … #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT … #define CPU_SYS_CLKCFG_CPU_FDIV_MASK … #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT … #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK … /* clock scaling */ #define CLKCFG_FDIV_MASK … #define CLKCFG_FDIV_USB_VAL … #define CLKCFG_FFRAC_MASK … #define CLKCFG_FFRAC_USB_VAL … struct mtmips_clk; struct mtmips_clk_fixed; struct mtmips_clk_factor; struct mtmips_clk_data { … }; struct mtmips_clk_priv { … }; struct mtmips_clk { … }; struct mtmips_clk_fixed { … }; struct mtmips_clk_factor { … }; static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops mtmips_periph_clk_ops = …; #define CLK_PERIPH(_name, _parent) … static struct mtmips_clk rt2880_pherip_clks[] = …; static struct mtmips_clk rt305x_pherip_clks[] = …; static struct mtmips_clk rt5350_pherip_clks[] = …; static struct mtmips_clk mt7620_pherip_clks[] = …; static struct mtmips_clk mt76x8_pherip_clks[] = …; static int mtmips_register_pherip_clocks(struct device_node *np, struct clk_hw_onecell_data *clk_data, struct mtmips_clk_priv *priv) { … } #define CLK_FIXED(_name, _parent, _rate) … static struct mtmips_clk_fixed rt305x_fixed_clocks[] = …; static struct mtmips_clk_fixed rt3352_fixed_clocks[] = …; static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = …; static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data, struct mtmips_clk_priv *priv) { … } #define CLK_FACTOR(_name, _parent, _mult, _div) … static struct mtmips_clk_factor rt2880_factor_clocks[] = …; static struct mtmips_clk_factor rt305x_factor_clocks[] = …; static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data, struct mtmips_clk_priv *priv) { … } static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw) { … } static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw, unsigned long xtal_clk) { … } static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw, unsigned long xtal_clk) { … } static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw, unsigned long xtal_clk) { … } static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw, unsigned long xtal_clk) { … } static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw, unsigned long xtal_clk) { … } static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) { … } static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw, unsigned long xtal_clk) { … } #define CLK_BASE(_name, _parent, _recalc) … static struct mtmips_clk rt2880_clks_base[] = …; static struct mtmips_clk rt305x_clks_base[] = …; static struct mtmips_clk rt3352_clks_base[] = …; static struct mtmips_clk rt3883_clks_base[] = …; static struct mtmips_clk rt5350_clks_base[] = …; static struct mtmips_clk mt7620_clks_base[] = …; static struct mtmips_clk mt76x8_clks_base[] = …; static int mtmips_register_clocks(struct device_node *np, struct clk_hw_onecell_data *clk_data, struct mtmips_clk_priv *priv) { … } static const struct mtmips_clk_data rt2880_clk_data = …; static const struct mtmips_clk_data rt305x_clk_data = …; static const struct mtmips_clk_data rt3352_clk_data = …; static const struct mtmips_clk_data rt3883_clk_data = …; static const struct mtmips_clk_data rt5350_clk_data = …; static const struct mtmips_clk_data mt7620_clk_data = …; static const struct mtmips_clk_data mt76x8_clk_data = …; static const struct of_device_id mtmips_of_match[] = …; static void __init mtmips_clk_regs_init(struct device_node *node, struct mtmips_clk_priv *priv) { … } static void __init mtmips_clk_init(struct device_node *node) { … } CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init); CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init); CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init); CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init); CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init); CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init); CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init); CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init); CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init); struct mtmips_rst { … }; static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev) { … } static int mtmips_assert_device(struct reset_controller_dev *rcdev, unsigned long id) { … } static int mtmips_deassert_device(struct reset_controller_dev *rcdev, unsigned long id) { … } static int mtmips_reset_device(struct reset_controller_dev *rcdev, unsigned long id) { … } static int mtmips_rst_xlate(struct reset_controller_dev *rcdev, const struct of_phandle_args *reset_spec) { … } static const struct reset_control_ops reset_ops = …; static int mtmips_reset_init(struct device *dev, struct regmap *sysc) { … } static int mtmips_clk_probe(struct platform_device *pdev) { … } static struct platform_driver mtmips_clk_driver = …; static int __init mtmips_clk_reset_init(void) { … } arch_initcall(mtmips_clk_reset_init);
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