linux/include/dt-bindings/clock/r8a7791-cpg-mssr.h

/* SPDX-License-Identifier: GPL-2.0+
 *
 * Copyright (C) 2015 Renesas Electronics Corp.
 */

#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r8a7791 CPG Core Clocks */
#define R8A7791_CLK_Z …
#define R8A7791_CLK_ZG …
#define R8A7791_CLK_ZTR …
#define R8A7791_CLK_ZTRD2 …
#define R8A7791_CLK_ZT …
#define R8A7791_CLK_ZX …
#define R8A7791_CLK_ZS …
#define R8A7791_CLK_HP …
#define R8A7791_CLK_I …
#define R8A7791_CLK_B …
#define R8A7791_CLK_LB …
#define R8A7791_CLK_P …
#define R8A7791_CLK_CL …
#define R8A7791_CLK_M2 …
#define R8A7791_CLK_ADSP …
#define R8A7791_CLK_ZB3 …
#define R8A7791_CLK_ZB3D2 …
#define R8A7791_CLK_DDR …
#define R8A7791_CLK_SDH …
#define R8A7791_CLK_SD0 …
#define R8A7791_CLK_SD2 …
#define R8A7791_CLK_SD3 …
#define R8A7791_CLK_MMC0 …
#define R8A7791_CLK_MP …
#define R8A7791_CLK_SSP …
#define R8A7791_CLK_SSPRS …
#define R8A7791_CLK_QSPI …
#define R8A7791_CLK_CP …
#define R8A7791_CLK_RCAN …
#define R8A7791_CLK_R …
#define R8A7791_CLK_OSC …

#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */