linux/drivers/clk/renesas/r8a77970-cpg-mssr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2017-2018 Cogent Embedded Inc.
 *
 * Based on r8a7795-cpg-mssr.c
 *
 * Copyright (C) 2015 Glider bvba
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>

#include <dt-bindings/clock/r8a77970-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-cpg-lib.h"
#include "rcar-gen3-cpg.h"

#define CPG_SD0CKCR …

enum r8a77970_clk_types { … };

enum clk_ids { … };

static const struct clk_div_table cpg_sd0h_div_table[] = …;

static const struct clk_div_table cpg_sd0_div_table[] = …;

static const struct cpg_core_clk r8a77970_core_clks[] __initconst = …;

static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = …;

static const unsigned int r8a77970_crit_mod_clks[] __initconst = …;

/*
 * CPG Clock Data
 */

/*
 *   MD		EXTAL		PLL0	PLL1	PLL3
 * 14 13 19	(MHz)
 *-------------------------------------------------
 * 0  0  0	16.66 x 1	x192	x192	x96
 * 0  0  1	16.66 x 1	x192	x192	x80
 * 0  1  0	20    x 1	x160	x160	x80
 * 0  1  1	20    x 1	x160	x160	x66
 * 1  0  0	27    / 2	x236	x236	x118
 * 1  0  1	27    / 2	x236	x236	x98
 * 1  1  0	33.33 / 2	x192	x192	x96
 * 1  1  1	33.33 / 2	x192	x192	x80
 */
#define CPG_PLL_CONFIG_INDEX(md) …

static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = …;

static int __init r8a77970_cpg_mssr_init(struct device *dev)
{ … }

static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
	struct clk **clks, void __iomem *base,
	struct raw_notifier_head *notifiers)
{ … }

const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = …;