linux/include/dt-bindings/clock/r8a779a0-cpg-mssr.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2020 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r8a779A0 CPG Core Clocks */
#define R8A779A0_CLK_Z0 …
#define R8A779A0_CLK_ZX …
#define R8A779A0_CLK_Z1 …
#define R8A779A0_CLK_ZR …
#define R8A779A0_CLK_ZS …
#define R8A779A0_CLK_ZT …
#define R8A779A0_CLK_ZTR …
#define R8A779A0_CLK_S1D1 …
#define R8A779A0_CLK_S1D2 …
#define R8A779A0_CLK_S1D4 …
#define R8A779A0_CLK_S1D8 …
#define R8A779A0_CLK_S1D12 …
#define R8A779A0_CLK_S3D1 …
#define R8A779A0_CLK_S3D2 …
#define R8A779A0_CLK_S3D4 …
#define R8A779A0_CLK_LB …
#define R8A779A0_CLK_CP …
#define R8A779A0_CLK_CL …
#define R8A779A0_CLK_CL16MCK …
#define R8A779A0_CLK_ZB30 …
#define R8A779A0_CLK_ZB30D2 …
#define R8A779A0_CLK_ZB30D4 …
#define R8A779A0_CLK_ZB31 …
#define R8A779A0_CLK_ZB31D2 …
#define R8A779A0_CLK_ZB31D4 …
#define R8A779A0_CLK_SD0H …
#define R8A779A0_CLK_SD0 …
#define R8A779A0_CLK_RPC …
#define R8A779A0_CLK_RPCD2 …
#define R8A779A0_CLK_MSO …
#define R8A779A0_CLK_CANFD …
#define R8A779A0_CLK_CSI0 …
#define R8A779A0_CLK_FRAY …
#define R8A779A0_CLK_DSI …
#define R8A779A0_CLK_VIP …
#define R8A779A0_CLK_ADGH …
#define R8A779A0_CLK_CNNDSP …
#define R8A779A0_CLK_ICU …
#define R8A779A0_CLK_ICUD2 …
#define R8A779A0_CLK_VCBUS …
#define R8A779A0_CLK_CBFUSA …
#define R8A779A0_CLK_R …
#define R8A779A0_CLK_OSC …

#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */