// SPDX-License-Identifier: GPL-2.0-only // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. #include <linux/cleanup.h> #include <linux/module.h> #include <linux/init.h> #include <linux/io.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/of_clk.h> #include <linux/clk-provider.h> #include <sound/soc.h> #include <sound/soc-dapm.h> #include <linux/pm_runtime.h> #include <linux/of_platform.h> #include <sound/tlv.h> #include "lpass-macro-common.h" #include "lpass-wsa-macro.h" #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL … #define CDC_WSA_MCLK_EN_MASK … #define CDC_WSA_MCLK_ENABLE … #define CDC_WSA_MCLK_DISABLE … #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL … #define CDC_WSA_FS_CNT_EN_MASK … #define CDC_WSA_FS_CNT_ENABLE … #define CDC_WSA_FS_CNT_DISABLE … #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL … #define CDC_WSA_SWR_CLK_EN_MASK … #define CDC_WSA_SWR_CLK_ENABLE … #define CDC_WSA_SWR_RST_EN_MASK … #define CDC_WSA_SWR_RST_ENABLE … #define CDC_WSA_SWR_RST_DISABLE … #define CDC_WSA_TOP_TOP_CFG0 … #define CDC_WSA_TOP_TOP_CFG1 … #define CDC_WSA_TOP_FREQ_MCLK … #define CDC_WSA_TOP_DEBUG_BUS_SEL … #define CDC_WSA_TOP_DEBUG_EN0 … #define CDC_WSA_TOP_DEBUG_EN1 … #define CDC_WSA_TOP_DEBUG_DSM_LB … #define CDC_WSA_TOP_RX_I2S_CTL … #define CDC_WSA_TOP_TX_I2S_CTL … #define CDC_WSA_TOP_I2S_CLK … #define CDC_WSA_TOP_I2S_RESET … #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 … #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 … #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 … #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 … #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 … #define CDC_WSA_RX_MIX_TX1_SEL_MASK … #define CDC_WSA_RX_MIX_TX1_SEL_SHFT … #define CDC_WSA_RX_MIX_TX0_SEL_MASK … #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 … #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 … #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL … #define CDC_WSA_TX_SPKR_PROT_RESET_MASK … #define CDC_WSA_TX_SPKR_PROT_RESET … #define CDC_WSA_TX_SPKR_PROT_NO_RESET … #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK … #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE … #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE … #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK … #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K … #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 … #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL … #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 … #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL … #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 … #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL … #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 … #define CDC_WSA_INTR_CTRL_CFG … #define CDC_WSA_INTR_CTRL_CLR_COMMIT … #define CDC_WSA_INTR_CTRL_PIN1_MASK0 … #define CDC_WSA_INTR_CTRL_PIN1_STATUS0 … #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0 … #define CDC_WSA_INTR_CTRL_PIN2_MASK0 … #define CDC_WSA_INTR_CTRL_PIN2_STATUS0 … #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0 … #define CDC_WSA_INTR_CTRL_LEVEL0 … #define CDC_WSA_INTR_CTRL_BYPASS0 … #define CDC_WSA_INTR_CTRL_SET0 … #define CDC_WSA_RX0_RX_PATH_CTL … #define CDC_WSA_RX_PATH_CLK_EN_MASK … #define CDC_WSA_RX_PATH_CLK_ENABLE … #define CDC_WSA_RX_PATH_CLK_DISABLE … #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK … #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE … #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE … #define CDC_WSA_RX0_RX_PATH_CFG0 … #define CDC_WSA_RX_PATH_COMP_EN_MASK … #define CDC_WSA_RX_PATH_COMP_ENABLE … #define CDC_WSA_RX_PATH_HD2_EN_MASK … #define CDC_WSA_RX_PATH_HD2_ENABLE … #define CDC_WSA_RX_PATH_SPKR_RATE_MASK … #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072 … #define CDC_WSA_RX0_RX_PATH_CFG1 … #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK … #define CDC_WSA_RX_PATH_SMART_BST_ENABLE … #define CDC_WSA_RX_PATH_SMART_BST_DISABLE … #define CDC_WSA_RX0_RX_PATH_CFG2 … #define CDC_WSA_RX0_RX_PATH_CFG3 … #define CDC_WSA_RX_DC_DCOEFF_MASK … #define CDC_WSA_RX0_RX_VOL_CTL … #define CDC_WSA_RX0_RX_PATH_MIX_CTL … #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK … #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE … #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE … #define CDC_WSA_RX0_RX_PATH_MIX_CFG … #define CDC_WSA_RX0_RX_VOL_MIX_CTL … #define CDC_WSA_RX0_RX_PATH_SEC0 … #define CDC_WSA_RX0_RX_PATH_SEC1 … #define CDC_WSA_RX_PGA_HALF_DB_MASK … #define CDC_WSA_RX_PGA_HALF_DB_ENABLE … #define CDC_WSA_RX_PGA_HALF_DB_DISABLE … #define CDC_WSA_RX0_RX_PATH_SEC2 … #define CDC_WSA_RX0_RX_PATH_SEC3 … #define CDC_WSA_RX_PATH_HD2_SCALE_MASK … #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK … #define CDC_WSA_RX0_RX_PATH_SEC5 … #define CDC_WSA_RX0_RX_PATH_SEC6 … #define CDC_WSA_RX0_RX_PATH_SEC7 … #define CDC_WSA_RX0_RX_PATH_MIX_SEC0 … #define CDC_WSA_RX0_RX_PATH_MIX_SEC1 … #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL … #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK … #define CDC_WSA_RX_DSMDEM_CLK_ENABLE … #define CDC_WSA_RX1_RX_PATH_CTL … #define CDC_WSA_RX1_RX_PATH_CFG0 … #define CDC_WSA_RX1_RX_PATH_CFG1 … #define CDC_WSA_RX1_RX_PATH_CFG2 … #define CDC_WSA_RX1_RX_PATH_CFG3 … #define CDC_WSA_RX1_RX_VOL_CTL … #define CDC_WSA_RX1_RX_PATH_MIX_CTL … #define CDC_WSA_RX1_RX_PATH_MIX_CFG … #define CDC_WSA_RX1_RX_VOL_MIX_CTL … #define CDC_WSA_RX1_RX_PATH_SEC0 … #define CDC_WSA_RX1_RX_PATH_SEC1 … #define CDC_WSA_RX1_RX_PATH_SEC2 … #define CDC_WSA_RX1_RX_PATH_SEC3 … #define CDC_WSA_RX1_RX_PATH_SEC5 … #define CDC_WSA_RX1_RX_PATH_SEC6 … #define CDC_WSA_RX1_RX_PATH_SEC7 … #define CDC_WSA_RX1_RX_PATH_MIX_SEC0 … #define CDC_WSA_RX1_RX_PATH_MIX_SEC1 … #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL … #define CDC_WSA_BOOST0_BOOST_PATH_CTL … #define CDC_WSA_BOOST_PATH_CLK_EN_MASK … #define CDC_WSA_BOOST_PATH_CLK_ENABLE … #define CDC_WSA_BOOST_PATH_CLK_DISABLE … #define CDC_WSA_BOOST0_BOOST_CTL … #define CDC_WSA_BOOST0_BOOST_CFG1 … #define CDC_WSA_BOOST0_BOOST_CFG2 … #define CDC_WSA_BOOST1_BOOST_PATH_CTL … #define CDC_WSA_BOOST1_BOOST_CTL … #define CDC_WSA_BOOST1_BOOST_CFG1 … #define CDC_WSA_BOOST1_BOOST_CFG2 … #define CDC_WSA_COMPANDER0_CTL0 … #define CDC_WSA_COMPANDER_CLK_EN_MASK … #define CDC_WSA_COMPANDER_CLK_ENABLE … #define CDC_WSA_COMPANDER_SOFT_RST_MASK … #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE … #define CDC_WSA_COMPANDER_HALT_MASK … #define CDC_WSA_COMPANDER_HALT … #define CDC_WSA_COMPANDER0_CTL1 … #define CDC_WSA_COMPANDER0_CTL2 … #define CDC_WSA_COMPANDER0_CTL3 … #define CDC_WSA_COMPANDER0_CTL4 … #define CDC_WSA_COMPANDER0_CTL5 … #define CDC_WSA_COMPANDER0_CTL6 … #define CDC_WSA_COMPANDER0_CTL7 … /* CDC_WSA_COMPANDER1_CTLx and CDC_WSA_SOFTCLIPx differ per LPASS codec versions */ #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL … #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK … #define CDC_WSA_EC_HQ_EC_CLK_ENABLE … #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 … #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK … #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K … #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL … #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 … #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL … #define CDC_WSA_SPLINE_ASRC0_CTL0 … #define CDC_WSA_SPLINE_ASRC0_CTL1 … #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL … #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB … #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB … #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB … #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB … #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO … #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL … #define CDC_WSA_SPLINE_ASRC1_CTL0 … #define CDC_WSA_SPLINE_ASRC1_CTL1 … #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL … #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB … #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB … #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB … #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB … #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO … #define WSA_MAX_OFFSET … /* LPASS codec version <=2.4 register offsets */ #define CDC_WSA_COMPANDER1_CTL0 … #define CDC_WSA_COMPANDER1_CTL1 … #define CDC_WSA_COMPANDER1_CTL2 … #define CDC_WSA_COMPANDER1_CTL3 … #define CDC_WSA_COMPANDER1_CTL4 … #define CDC_WSA_COMPANDER1_CTL5 … #define CDC_WSA_COMPANDER1_CTL6 … #define CDC_WSA_COMPANDER1_CTL7 … #define CDC_WSA_SOFTCLIP0_CRC … #define CDC_WSA_SOFTCLIP_CLK_EN_MASK … #define CDC_WSA_SOFTCLIP_CLK_ENABLE … #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL … #define CDC_WSA_SOFTCLIP_EN_MASK … #define CDC_WSA_SOFTCLIP_ENABLE … #define CDC_WSA_SOFTCLIP1_CRC … #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL … /* LPASS codec version >=2.5 register offsets */ #define CDC_WSA_TOP_FS_UNGATE … #define CDC_WSA_TOP_GRP_SEL … #define CDC_WSA_TOP_FS_UNGATE2 … #define CDC_2_5_WSA_COMPANDER0_CTL8 … #define CDC_2_5_WSA_COMPANDER0_CTL9 … #define CDC_2_5_WSA_COMPANDER0_CTL10 … #define CDC_2_5_WSA_COMPANDER0_CTL11 … #define CDC_2_5_WSA_COMPANDER0_CTL12 … #define CDC_2_5_WSA_COMPANDER0_CTL13 … #define CDC_2_5_WSA_COMPANDER0_CTL14 … #define CDC_2_5_WSA_COMPANDER0_CTL15 … #define CDC_2_5_WSA_COMPANDER0_CTL16 … #define CDC_2_5_WSA_COMPANDER0_CTL17 … #define CDC_2_5_WSA_COMPANDER0_CTL18 … #define CDC_2_5_WSA_COMPANDER0_CTL19 … #define CDC_2_5_WSA_COMPANDER1_CTL0 … #define CDC_2_5_WSA_COMPANDER1_CTL1 … #define CDC_2_5_WSA_COMPANDER1_CTL2 … #define CDC_2_5_WSA_COMPANDER1_CTL3 … #define CDC_2_5_WSA_COMPANDER1_CTL4 … #define CDC_2_5_WSA_COMPANDER1_CTL5 … #define CDC_2_5_WSA_COMPANDER1_CTL6 … #define CDC_2_5_WSA_COMPANDER1_CTL7 … #define CDC_2_5_WSA_COMPANDER1_CTL8 … #define CDC_2_5_WSA_COMPANDER1_CTL9 … #define CDC_2_5_WSA_COMPANDER1_CTL10 … #define CDC_2_5_WSA_COMPANDER1_CTL11 … #define CDC_2_5_WSA_COMPANDER1_CTL12 … #define CDC_2_5_WSA_COMPANDER1_CTL13 … #define CDC_2_5_WSA_COMPANDER1_CTL14 … #define CDC_2_5_WSA_COMPANDER1_CTL15 … #define CDC_2_5_WSA_COMPANDER1_CTL16 … #define CDC_2_5_WSA_COMPANDER1_CTL17 … #define CDC_2_5_WSA_COMPANDER1_CTL18 … #define CDC_2_5_WSA_COMPANDER1_CTL19 … #define CDC_2_5_WSA_SOFTCLIP0_CRC … #define CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL … #define CDC_2_5_WSA_SOFTCLIP1_CRC … #define CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL … #define WSA_MACRO_RX_RATES … #define WSA_MACRO_RX_MIX_RATES … #define WSA_MACRO_RX_FORMATS … #define WSA_MACRO_ECHO_RATES … #define WSA_MACRO_ECHO_FORMATS … #define NUM_INTERPOLATORS … #define WSA_NUM_CLKS_MAX … #define WSA_MACRO_MCLK_FREQ … #define WSA_MACRO_MUX_CFG_OFFSET … #define WSA_MACRO_MUX_CFG1_OFFSET … #define WSA_MACRO_RX_PATH_OFFSET … #define WSA_MACRO_RX_PATH_CFG3_OFFSET … #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET … #define WSA_MACRO_FS_RATE_MASK … #define WSA_MACRO_EC_MIX_TX0_MASK … #define WSA_MACRO_EC_MIX_TX1_MASK … #define WSA_MACRO_MAX_DMA_CH_PER_PORT … enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; struct interp_sample_rate { … }; static struct interp_sample_rate int_prim_sample_rate_val[] = …; static struct interp_sample_rate int_mix_sample_rate_val[] = …; enum { … }; /** * struct wsa_reg_layout - Register layout differences * @rx_intx_1_mix_inp0_sel_mask: register mask for RX_INTX_1_MIX_INP0_SEL_MASK * @rx_intx_1_mix_inp1_sel_mask: register mask for RX_INTX_1_MIX_INP1_SEL_MASK * @rx_intx_1_mix_inp2_sel_mask: register mask for RX_INTX_1_MIX_INP2_SEL_MASK * @rx_intx_2_sel_mask: register mask for RX_INTX_2_SEL_MASK * @compander1_reg_offset: offset between compander registers (compander1 - compander0) * @softclip0_reg_base: base address of softclip0 register * @softclip1_reg_offset: offset between compander registers (softclip1 - softclip0) */ struct wsa_reg_layout { … }; struct wsa_macro { … }; #define to_wsa_macro(_hw) … static const struct wsa_reg_layout wsa_codec_v2_1 = …; static const struct wsa_reg_layout wsa_codec_v2_5 = …; static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); static const char *const rx_text_v2_1[] = …; static const char *const rx_text_v2_5[] = …; static const char *const rx_mix_text_v2_1[] = …; static const char *const rx_mix_text_v2_5[] = …; static const char *const rx_mix_ec_text[] = …; static const char *const rx_mux_text[] = …; static const char *const rx_sidetone_mix_text[] = …; static const char * const wsa_macro_ear_spkr_pa_gain_text[] = …; static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum, wsa_macro_ear_spkr_pa_gain_text); /* RX INT0 */ static const struct soc_enum rx0_prim_inp0_chain_enum_v2_1 = …; static const struct soc_enum rx0_prim_inp1_chain_enum_v2_1 = …; static const struct soc_enum rx0_prim_inp2_chain_enum_v2_1 = …; static const struct soc_enum rx0_mix_chain_enum_v2_1 = …; static const struct soc_enum rx0_prim_inp0_chain_enum_v2_5 = …; static const struct soc_enum rx0_prim_inp1_chain_enum_v2_5 = …; static const struct soc_enum rx0_prim_inp2_chain_enum_v2_5 = …; static const struct soc_enum rx0_mix_chain_enum_v2_5 = …; static const struct soc_enum rx0_sidetone_mix_enum = …; static const struct snd_kcontrol_new rx0_prim_inp0_mux_v2_1 = …; static const struct snd_kcontrol_new rx0_prim_inp1_mux_v2_1 = …; static const struct snd_kcontrol_new rx0_prim_inp2_mux_v2_1 = …; static const struct snd_kcontrol_new rx0_mix_mux_v2_1 = …; static const struct snd_kcontrol_new rx0_prim_inp0_mux_v2_5 = …; static const struct snd_kcontrol_new rx0_prim_inp1_mux_v2_5 = …; static const struct snd_kcontrol_new rx0_prim_inp2_mux_v2_5 = …; static const struct snd_kcontrol_new rx0_mix_mux_v2_5 = …; static const struct snd_kcontrol_new rx0_sidetone_mix_mux = …; /* RX INT1 */ static const struct soc_enum rx1_prim_inp0_chain_enum_v2_1 = …; static const struct soc_enum rx1_prim_inp1_chain_enum_v2_1 = …; static const struct soc_enum rx1_prim_inp2_chain_enum_v2_1 = …; static const struct soc_enum rx1_mix_chain_enum_v2_1 = …; static const struct soc_enum rx1_prim_inp0_chain_enum_v2_5 = …; static const struct soc_enum rx1_prim_inp1_chain_enum_v2_5 = …; static const struct soc_enum rx1_prim_inp2_chain_enum_v2_5 = …; static const struct soc_enum rx1_mix_chain_enum_v2_5 = …; static const struct snd_kcontrol_new rx1_prim_inp0_mux_v2_1 = …; static const struct snd_kcontrol_new rx1_prim_inp1_mux_v2_1 = …; static const struct snd_kcontrol_new rx1_prim_inp2_mux_v2_1 = …; static const struct snd_kcontrol_new rx1_mix_mux_v2_1 = …; static const struct snd_kcontrol_new rx1_prim_inp0_mux_v2_5 = …; static const struct snd_kcontrol_new rx1_prim_inp1_mux_v2_5 = …; static const struct snd_kcontrol_new rx1_prim_inp2_mux_v2_5 = …; static const struct snd_kcontrol_new rx1_mix_mux_v2_5 = …; static const struct soc_enum rx_mix_ec0_enum = …; static const struct soc_enum rx_mix_ec1_enum = …; static const struct snd_kcontrol_new rx_mix_ec0_mux = …; static const struct snd_kcontrol_new rx_mix_ec1_mux = …; static const struct reg_default wsa_defaults[] = …; static const struct reg_default wsa_defaults_v2_1[] = …; static const struct reg_default wsa_defaults_v2_5[] = …; static bool wsa_is_wronly_register(struct device *dev, unsigned int reg) { … } static bool wsa_is_rw_register_v2_1(struct device *dev, unsigned int reg) { … } static bool wsa_is_rw_register_v2_5(struct device *dev, unsigned int reg) { … } static bool wsa_is_rw_register(struct device *dev, unsigned int reg) { … } static bool wsa_is_writeable_register(struct device *dev, unsigned int reg) { … } static bool wsa_is_readable_register_v2_1(struct device *dev, unsigned int reg) { … } static bool wsa_is_readable_register_v2_5(struct device *dev, unsigned int reg) { … } static bool wsa_is_readable_register(struct device *dev, unsigned int reg) { … } static bool wsa_is_volatile_register_v2_1(struct device *dev, unsigned int reg) { … } static bool wsa_is_volatile_register_v2_5(struct device *dev, unsigned int reg) { … } static bool wsa_is_volatile_register(struct device *dev, unsigned int reg) { … } static const struct regmap_config wsa_regmap_config = …; /** * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost * settings based on speaker mode. * * @component: codec instance * @mode: Indicates speaker configuration mode. * * Returns 0 on success or -EINVAL on error. */ int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode) { … } EXPORT_SYMBOL(…); static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, u8 int_prim_fs_rate_reg_val, u32 sample_rate) { … } static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, u8 int_mix_fs_rate_reg_val, u32 sample_rate) { … } static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai, u32 sample_rate) { … } static int wsa_macro_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static int wsa_macro_get_channel_map(const struct snd_soc_dai *dai, unsigned int *tx_num, unsigned int *tx_slot, unsigned int *rx_num, unsigned int *rx_slot) { … } static const struct snd_soc_dai_ops wsa_macro_dai_ops = …; static struct snd_soc_dai_driver wsa_macro_dai[] = …; static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable) { … } static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static void wsa_macro_hd2_control(struct snd_soc_component *component, u16 reg, int event) { … } static int wsa_macro_config_compander(struct snd_soc_component *component, int comp, int event) { … } static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component, struct wsa_macro *wsa, int path, bool enable) { … } static int wsa_macro_config_softclip(struct snd_soc_component *component, int path, int event) { … } static bool wsa_macro_adie_lb(struct snd_soc_component *component, int interp_idx) { … } static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind) { … } static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component, u16 reg, int event) { … } static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component, struct wsa_macro *wsa, int event, int gain_reg) { … } static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static const struct snd_kcontrol_new wsa_macro_snd_controls[] = …; static const struct soc_enum rx_mux_enum = …; static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = …; static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static const struct snd_kcontrol_new aif_vi_mixer[] = …; static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = …; static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets_v2_1[] = …; static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets_v2_5[] = …; static const struct snd_soc_dapm_route wsa_audio_map[] = …; static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) { … } static int wsa_macro_component_probe(struct snd_soc_component *comp) { … } static int swclk_gate_enable(struct clk_hw *hw) { … } static void swclk_gate_disable(struct clk_hw *hw) { … } static int swclk_gate_is_enabled(struct clk_hw *hw) { … } static unsigned long swclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops swclk_gate_ops = …; static int wsa_macro_register_mclk_output(struct wsa_macro *wsa) { … } static const struct snd_soc_component_driver wsa_macro_component_drv = …; static int wsa_macro_probe(struct platform_device *pdev) { … } static void wsa_macro_remove(struct platform_device *pdev) { … } static int __maybe_unused wsa_macro_runtime_suspend(struct device *dev) { … } static int __maybe_unused wsa_macro_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops wsa_macro_pm_ops = …; static const struct of_device_id wsa_macro_dt_match[] = …; MODULE_DEVICE_TABLE(of, wsa_macro_dt_match); static struct platform_driver wsa_macro_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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