// SPDX-License-Identifier: GPL-2.0-only // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. #include <linux/cleanup.h> #include <linux/module.h> #include <linux/init.h> #include <linux/io.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/clk.h> #include <sound/soc.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc-dapm.h> #include <sound/tlv.h> #include <linux/of_clk.h> #include <linux/clk-provider.h> #include "lpass-macro-common.h" #define CDC_RX_TOP_TOP_CFG0 … #define CDC_RX_TOP_SWR_CTRL … #define CDC_RX_TOP_DEBUG … #define CDC_RX_TOP_DEBUG_BUS … #define CDC_RX_TOP_DEBUG_EN0 … #define CDC_RX_TOP_DEBUG_EN1 … #define CDC_RX_TOP_DEBUG_EN2 … #define CDC_RX_TOP_HPHL_COMP_WR_LSB … #define CDC_RX_TOP_HPHL_COMP_WR_MSB … #define CDC_RX_TOP_HPHL_COMP_LUT … #define CDC_RX_TOP_HPH_LUT_BYPASS_MASK … #define CDC_RX_TOP_HPHL_COMP_RD_LSB … #define CDC_RX_TOP_HPHL_COMP_RD_MSB … #define CDC_RX_TOP_HPHR_COMP_WR_LSB … #define CDC_RX_TOP_HPHR_COMP_WR_MSB … #define CDC_RX_TOP_HPHR_COMP_LUT … #define CDC_RX_TOP_HPHR_COMP_RD_LSB … #define CDC_RX_TOP_HPHR_COMP_RD_MSB … #define CDC_RX_TOP_DSD0_DEBUG_CFG0 … #define CDC_RX_TOP_DSD0_DEBUG_CFG1 … #define CDC_RX_TOP_DSD0_DEBUG_CFG2 … #define CDC_RX_TOP_DSD0_DEBUG_CFG3 … #define CDC_RX_TOP_DSD1_DEBUG_CFG0 … #define CDC_RX_TOP_DSD1_DEBUG_CFG1 … #define CDC_RX_TOP_DSD1_DEBUG_CFG2 … #define CDC_RX_TOP_DSD1_DEBUG_CFG3 … #define CDC_RX_TOP_RX_I2S_CTL … #define CDC_RX_TOP_TX_I2S2_CTL … #define CDC_RX_TOP_I2S_CLK … #define CDC_RX_TOP_I2S_RESET … #define CDC_RX_TOP_I2S_MUX … #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL … #define CDC_RX_CLK_MCLK_EN_MASK … #define CDC_RX_CLK_MCLK_ENABLE … #define CDC_RX_CLK_MCLK2_EN_MASK … #define CDC_RX_CLK_MCLK2_ENABLE … #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL … #define CDC_RX_FS_MCLK_CNT_EN_MASK … #define CDC_RX_FS_MCLK_CNT_ENABLE … #define CDC_RX_FS_MCLK_CNT_CLR_MASK … #define CDC_RX_FS_MCLK_CNT_CLR … #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL … #define CDC_RX_SWR_CLK_EN_MASK … #define CDC_RX_SWR_RESET_MASK … #define CDC_RX_SWR_RESET … #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL … #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL … #define CDC_RX_SOFTCLIP_CRC … #define CDC_RX_SOFTCLIP_CLK_EN_MASK … #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL … #define CDC_RX_SOFTCLIP_EN_MASK … #define CDC_RX_INP_MUX_RX_INT0_CFG0 … #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK … #define CDC_RX_INTX_1_MIX_INP1_SEL_MASK … #define CDC_RX_INP_MUX_RX_INT0_CFG1 … #define CDC_RX_INTX_2_SEL_MASK … #define CDC_RX_INTX_1_MIX_INP2_SEL_MASK … #define CDC_RX_INP_MUX_RX_INT1_CFG0 … #define CDC_RX_INP_MUX_RX_INT1_CFG1 … #define CDC_RX_INP_MUX_RX_INT2_CFG0 … #define CDC_RX_INP_MUX_RX_INT2_CFG1 … #define CDC_RX_INP_MUX_RX_MIX_CFG4 … #define CDC_RX_INP_MUX_RX_MIX_CFG5 … #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 … #define CDC_RX_CLSH_CRC … #define CDC_RX_CLSH_CLK_EN_MASK … #define CDC_RX_CLSH_DLY_CTRL … #define CDC_RX_CLSH_DECAY_CTRL … #define CDC_RX_CLSH_DECAY_RATE_MASK … #define CDC_RX_CLSH_HPH_V_PA … #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK … #define CDC_RX_CLSH_EAR_V_PA … #define CDC_RX_CLSH_HPH_V_HD … #define CDC_RX_CLSH_EAR_V_HD … #define CDC_RX_CLSH_K1_MSB … #define CDC_RX_CLSH_K1_MSB_COEFF_MASK … #define CDC_RX_CLSH_K1_LSB … #define CDC_RX_CLSH_K2_MSB … #define CDC_RX_CLSH_K2_LSB … #define CDC_RX_CLSH_IDLE_CTRL … #define CDC_RX_CLSH_IDLE_HPH … #define CDC_RX_CLSH_IDLE_EAR … #define CDC_RX_CLSH_TEST0 … #define CDC_RX_CLSH_TEST1 … #define CDC_RX_CLSH_OVR_VREF … #define CDC_RX_CLSH_CLSG_CTL … #define CDC_RX_CLSH_CLSG_CFG1 … #define CDC_RX_CLSH_CLSG_CFG2 … #define CDC_RX_BCL_VBAT_PATH_CTL … #define CDC_RX_BCL_VBAT_CFG … #define CDC_RX_BCL_VBAT_ADC_CAL1 … #define CDC_RX_BCL_VBAT_ADC_CAL2 … #define CDC_RX_BCL_VBAT_ADC_CAL3 … #define CDC_RX_BCL_VBAT_PK_EST1 … #define CDC_RX_BCL_VBAT_PK_EST2 … #define CDC_RX_BCL_VBAT_PK_EST3 … #define CDC_RX_BCL_VBAT_RF_PROC1 … #define CDC_RX_BCL_VBAT_RF_PROC2 … #define CDC_RX_BCL_VBAT_TAC1 … #define CDC_RX_BCL_VBAT_TAC2 … #define CDC_RX_BCL_VBAT_TAC3 … #define CDC_RX_BCL_VBAT_TAC4 … #define CDC_RX_BCL_VBAT_GAIN_UPD1 … #define CDC_RX_BCL_VBAT_GAIN_UPD2 … #define CDC_RX_BCL_VBAT_GAIN_UPD3 … #define CDC_RX_BCL_VBAT_GAIN_UPD4 … #define CDC_RX_BCL_VBAT_GAIN_UPD5 … #define CDC_RX_BCL_VBAT_DEBUG1 … #define CDC_RX_BCL_VBAT_GAIN_UPD_MON … #define CDC_RX_BCL_VBAT_GAIN_MON_VAL … #define CDC_RX_BCL_VBAT_BAN … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 … #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 … #define CDC_RX_BCL_VBAT_ATTN1 … #define CDC_RX_BCL_VBAT_ATTN2 … #define CDC_RX_BCL_VBAT_ATTN3 … #define CDC_RX_BCL_VBAT_DECODE_CTL1 … #define CDC_RX_BCL_VBAT_DECODE_CTL2 … #define CDC_RX_BCL_VBAT_DECODE_CFG1 … #define CDC_RX_BCL_VBAT_DECODE_CFG2 … #define CDC_RX_BCL_VBAT_DECODE_CFG3 … #define CDC_RX_BCL_VBAT_DECODE_CFG4 … #define CDC_RX_BCL_VBAT_DECODE_ST … #define CDC_RX_INTR_CTRL_CFG … #define CDC_RX_INTR_CTRL_CLR_COMMIT … #define CDC_RX_INTR_CTRL_PIN1_MASK0 … #define CDC_RX_INTR_CTRL_PIN1_STATUS0 … #define CDC_RX_INTR_CTRL_PIN1_CLEAR0 … #define CDC_RX_INTR_CTRL_PIN2_MASK0 … #define CDC_RX_INTR_CTRL_PIN2_STATUS0 … #define CDC_RX_INTR_CTRL_PIN2_CLEAR0 … #define CDC_RX_INTR_CTRL_LEVEL0 … #define CDC_RX_INTR_CTRL_BYPASS0 … #define CDC_RX_INTR_CTRL_SET0 … #define CDC_RX_RXn_RX_PATH_CTL(rx, n) … #define CDC_RX_RX0_RX_PATH_CTL … #define CDC_RX_PATH_RESET_EN_MASK … #define CDC_RX_PATH_CLK_EN_MASK … #define CDC_RX_PATH_CLK_ENABLE … #define CDC_RX_PATH_PGA_MUTE_MASK … #define CDC_RX_PATH_PGA_MUTE_ENABLE … #define CDC_RX_PATH_PCM_RATE_MASK … #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) … #define CDC_RX_RXn_COMP_EN_MASK … #define CDC_RX_RX0_RX_PATH_CFG0 … #define CDC_RX_RXn_CLSH_EN_MASK … #define CDC_RX_DLY_ZN_EN_MASK … #define CDC_RX_DLY_ZN_ENABLE … #define CDC_RX_RXn_HD2_EN_MASK … #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) … #define CDC_RX_RXn_SIDETONE_EN_MASK … #define CDC_RX_RX0_RX_PATH_CFG1 … #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK … #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) … #define CDC_RX_RXn_HPF_CUT_FREQ_MASK … #define CDC_RX_RX0_RX_PATH_CFG2 … #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) … #define CDC_RX_RX0_RX_PATH_CFG3 … #define CDC_RX_DC_COEFF_SEL_MASK … #define CDC_RX_DC_COEFF_SEL_TWO … #define CDC_RX_RXn_RX_VOL_CTL(rx, n) … #define CDC_RX_RX0_RX_VOL_CTL … #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) … #define CDC_RX_RXn_MIX_PCM_RATE_MASK … #define CDC_RX_RXn_MIX_RESET_MASK … #define CDC_RX_RXn_MIX_RESET … #define CDC_RX_RXn_MIX_CLK_EN_MASK … #define CDC_RX_RX0_RX_PATH_MIX_CTL … #define CDC_RX_RX0_RX_PATH_MIX_CFG … #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) … #define CDC_RX_RX0_RX_VOL_MIX_CTL … #define CDC_RX_RX0_RX_PATH_SEC1 … #define CDC_RX_RX0_RX_PATH_SEC2 … #define CDC_RX_RX0_RX_PATH_SEC3 … #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) … #define CDC_RX_RX0_RX_PATH_SEC4 … #define CDC_RX_RX0_RX_PATH_SEC7 … #define CDC_RX_RXn_RX_PATH_SEC7(rx, n) … #define CDC_RX_DSM_OUT_DELAY_SEL_MASK … #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE … #define CDC_RX_RX0_RX_PATH_MIX_SEC0 … #define CDC_RX_RX0_RX_PATH_MIX_SEC1 … #define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n) … #define CDC_RX_RXn_DSM_CLK_EN_MASK … #define CDC_RX_RX0_RX_PATH_DSM_CTL … #define CDC_RX_RX0_RX_PATH_DSM_DATA1 … #define CDC_RX_RX0_RX_PATH_DSM_DATA2 … #define CDC_RX_RX0_RX_PATH_DSM_DATA3 … #define CDC_RX_RX0_RX_PATH_DSM_DATA4 … #define CDC_RX_RX0_RX_PATH_DSM_DATA5 … #define CDC_RX_RX0_RX_PATH_DSM_DATA6 … /* RX offsets prior to 2.5 codec version */ #define CDC_RX_RX1_RX_PATH_CTL … #define CDC_RX_RX1_RX_PATH_CFG0 … #define CDC_RX_RX1_RX_PATH_CFG1 … #define CDC_RX_RX1_RX_PATH_CFG2 … #define CDC_RX_RX1_RX_PATH_CFG3 … #define CDC_RX_RX1_RX_VOL_CTL … #define CDC_RX_RX1_RX_PATH_MIX_CTL … #define CDC_RX_RX1_RX_PATH_MIX_CFG … #define CDC_RX_RX1_RX_VOL_MIX_CTL … #define CDC_RX_RX1_RX_PATH_SEC1 … #define CDC_RX_RX1_RX_PATH_SEC2 … #define CDC_RX_RX1_RX_PATH_SEC3 … #define CDC_RX_RXn_HD2_ALPHA_MASK … #define CDC_RX_RX1_RX_PATH_SEC4 … #define CDC_RX_RX1_RX_PATH_SEC7 … #define CDC_RX_RX1_RX_PATH_MIX_SEC0 … #define CDC_RX_RX1_RX_PATH_MIX_SEC1 … #define CDC_RX_RX1_RX_PATH_DSM_CTL … #define CDC_RX_RX1_RX_PATH_DSM_DATA1 … #define CDC_RX_RX1_RX_PATH_DSM_DATA2 … #define CDC_RX_RX1_RX_PATH_DSM_DATA3 … #define CDC_RX_RX1_RX_PATH_DSM_DATA4 … #define CDC_RX_RX1_RX_PATH_DSM_DATA5 … #define CDC_RX_RX1_RX_PATH_DSM_DATA6 … #define CDC_RX_RX2_RX_PATH_CTL … #define CDC_RX_RX2_RX_PATH_CFG0 … #define CDC_RX_RX2_CLSH_EN_MASK … #define CDC_RX_RX2_DLY_Z_EN_MASK … #define CDC_RX_RX2_RX_PATH_CFG1 … #define CDC_RX_RX2_RX_PATH_CFG2 … #define CDC_RX_RX2_RX_PATH_CFG3 … #define CDC_RX_RX2_RX_VOL_CTL … #define CDC_RX_RX2_RX_PATH_MIX_CTL … #define CDC_RX_RX2_RX_PATH_MIX_CFG … #define CDC_RX_RX2_RX_VOL_MIX_CTL … #define CDC_RX_RX2_RX_PATH_SEC0 … #define CDC_RX_RX2_RX_PATH_SEC1 … #define CDC_RX_RX2_RX_PATH_SEC2 … #define CDC_RX_RX2_RX_PATH_SEC3 … #define CDC_RX_RX2_RX_PATH_SEC4 … #define CDC_RX_RX2_RX_PATH_SEC5 … #define CDC_RX_RX2_RX_PATH_SEC6 … #define CDC_RX_RX2_RX_PATH_SEC7 … #define CDC_RX_RX2_RX_PATH_MIX_SEC0 … #define CDC_RX_RX2_RX_PATH_MIX_SEC1 … #define CDC_RX_RX2_RX_PATH_DSM_CTL … /* LPASS CODEC version 2.5 rx reg offsets */ #define CDC_2_5_RX_RX1_RX_PATH_CTL … #define CDC_2_5_RX_RX1_RX_PATH_CFG0 … #define CDC_2_5_RX_RX1_RX_PATH_CFG1 … #define CDC_2_5_RX_RX1_RX_PATH_CFG2 … #define CDC_2_5_RX_RX1_RX_PATH_CFG3 … #define CDC_2_5_RX_RX1_RX_VOL_CTL … #define CDC_2_5_RX_RX1_RX_PATH_MIX_CTL … #define CDC_2_5_RX_RX1_RX_PATH_MIX_CFG … #define CDC_2_5_RX_RX1_RX_VOL_MIX_CTL … #define CDC_2_5_RX_RX1_RX_PATH_SEC1 … #define CDC_2_5_RX_RX1_RX_PATH_SEC2 … #define CDC_2_5_RX_RX1_RX_PATH_SEC3 … #define CDC_2_5_RX_RX1_RX_PATH_SEC4 … #define CDC_2_5_RX_RX1_RX_PATH_SEC7 … #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0 … #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1 … #define CDC_2_5_RX_RX1_RX_PATH_DSM_CTL … #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1 … #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2 … #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3 … #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4 … #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5 … #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6 … #define CDC_2_5_RX_RX2_RX_PATH_CTL … #define CDC_2_5_RX_RX2_RX_PATH_CFG0 … #define CDC_2_5_RX_RX2_RX_PATH_CFG1 … #define CDC_2_5_RX_RX2_RX_PATH_CFG2 … #define CDC_2_5_RX_RX2_RX_PATH_CFG3 … #define CDC_2_5_RX_RX2_RX_VOL_CTL … #define CDC_2_5_RX_RX2_RX_PATH_MIX_CTL … #define CDC_2_5_RX_RX2_RX_PATH_MIX_CFG … #define CDC_2_5_RX_RX2_RX_VOL_MIX_CTL … #define CDC_2_5_RX_RX2_RX_PATH_SEC0 … #define CDC_2_5_RX_RX2_RX_PATH_SEC1 … #define CDC_2_5_RX_RX2_RX_PATH_SEC2 … #define CDC_2_5_RX_RX2_RX_PATH_SEC3 … #define CDC_2_5_RX_RX2_RX_PATH_SEC4 … #define CDC_2_5_RX_RX2_RX_PATH_SEC5 … #define CDC_2_5_RX_RX2_RX_PATH_SEC6 … #define CDC_2_5_RX_RX2_RX_PATH_SEC7 … #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0 … #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1 … #define CDC_2_5_RX_RX2_RX_PATH_DSM_CTL … #define CDC_RX_IDLE_DETECT_PATH_CTL … #define CDC_RX_IDLE_DETECT_CFG0 … #define CDC_RX_IDLE_DETECT_CFG1 … #define CDC_RX_IDLE_DETECT_CFG2 … #define CDC_RX_IDLE_DETECT_CFG3 … #define CDC_RX_COMPANDERn_CTL0(n) … #define CDC_RX_COMPANDERn_CLK_EN_MASK … #define CDC_RX_COMPANDERn_SOFT_RST_MASK … #define CDC_RX_COMPANDERn_HALT_MASK … #define CDC_RX_COMPANDER0_CTL0 … #define CDC_RX_COMPANDER0_CTL1 … #define CDC_RX_COMPANDER0_CTL2 … #define CDC_RX_COMPANDER0_CTL3 … #define CDC_RX_COMPANDER0_CTL4 … #define CDC_RX_COMPANDER0_CTL5 … #define CDC_RX_COMPANDER0_CTL6 … #define CDC_RX_COMPANDER0_CTL7 … #define CDC_RX_COMPANDER1_CTL0 … #define CDC_RX_COMPANDER1_CTL1 … #define CDC_RX_COMPANDER1_CTL2 … #define CDC_RX_COMPANDER1_CTL3 … #define CDC_RX_COMPANDER1_CTL4 … #define CDC_RX_COMPANDER1_CTL5 … #define CDC_RX_COMPANDER1_CTL6 … #define CDC_RX_COMPANDER1_CTL7 … #define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK … #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL … #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL … #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL … #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 … #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 … #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 … #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 … #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 … #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 … #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 … #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 … #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL … #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 … #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL … #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 … #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL … #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 … #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL … #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 … #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL … #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 … #define CDC_RX_EC_ASRC0_CLK_RST_CTL … #define CDC_RX_EC_ASRC0_CTL0 … #define CDC_RX_EC_ASRC0_CTL1 … #define CDC_RX_EC_ASRC0_FIFO_CTL … #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB … #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB … #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB … #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB … #define CDC_RX_EC_ASRC0_STATUS_FIFO … #define CDC_RX_EC_ASRC1_CLK_RST_CTL … #define CDC_RX_EC_ASRC1_CTL0 … #define CDC_RX_EC_ASRC1_CTL1 … #define CDC_RX_EC_ASRC1_FIFO_CTL … #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB … #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB … #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB … #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB … #define CDC_RX_EC_ASRC1_STATUS_FIFO … #define CDC_RX_EC_ASRC2_CLK_RST_CTL … #define CDC_RX_EC_ASRC2_CTL0 … #define CDC_RX_EC_ASRC2_CTL1 … #define CDC_RX_EC_ASRC2_FIFO_CTL … #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB … #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB … #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB … #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB … #define CDC_RX_EC_ASRC2_STATUS_FIFO … #define CDC_RX_DSD0_PATH_CTL … #define CDC_RX_DSD0_CFG0 … #define CDC_RX_DSD0_CFG1 … #define CDC_RX_DSD0_CFG2 … #define CDC_RX_DSD1_PATH_CTL … #define CDC_RX_DSD1_CFG0 … #define CDC_RX_DSD1_CFG1 … #define CDC_RX_DSD1_CFG2 … #define RX_MAX_OFFSET … #define MCLK_FREQ … #define RX_MACRO_RATES … /* Fractional Rates */ #define RX_MACRO_FRAC_RATES … #define RX_MACRO_FORMATS … #define RX_MACRO_ECHO_RATES … #define RX_MACRO_ECHO_FORMATS … #define RX_MACRO_MAX_DMA_CH_PER_PORT … #define RX_MACRO_EC_MIX_TX0_MASK … #define RX_MACRO_EC_MIX_TX1_MASK … #define RX_MACRO_EC_MIX_TX2_MASK … #define COMP_MAX_COEFF … #define RX_NUM_CLKS_MAX … struct comp_coeff_val { … }; enum { … }; static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = …; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; /* Codec supports 2 IIR filters */ enum { … }; /* Each IIR has 5 Filter Stages */ enum { … }; #define RX_MACRO_IIR_FILTER_SIZE … #define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) … struct interp_sample_rate { … }; static struct interp_sample_rate sr_val_tbl[] = …; enum { … }; enum { … }; struct rx_macro { … }; #define to_rx_macro(_hw) … struct wcd_iir_filter_ctl { … }; static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); static const char * const rx_int_mix_mux_text[] = …; static const char * const rx_prim_mix_text[] = …; static const char * const rx_sidetone_mix_text[] = …; static const char * const iir_inp_mux_text[] = …; static const char * const rx_int_dem_inp_mux_text[] = …; static const char * const rx_int0_1_interp_mux_text[] = …; static const char * const rx_int1_1_interp_mux_text[] = …; static const char * const rx_int2_1_interp_mux_text[] = …; static const char * const rx_int0_2_interp_mux_text[] = …; static const char * const rx_int1_2_interp_mux_text[] = …; static const char * const rx_int2_2_interp_mux_text[] = …; static const char *const rx_macro_mux_text[] = …; static const char *const rx_macro_hph_pwr_mode_text[] = …; static const char * const rx_echo_mux_text[] = …; static const struct soc_enum rx_macro_hph_pwr_mode_enum = …; static const struct soc_enum rx_mix_tx2_mux_enum = …; static const struct soc_enum rx_mix_tx1_mux_enum = …; static const struct soc_enum rx_mix_tx0_mux_enum = …; static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0, rx_int_mix_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0, rx_int_mix_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0, rx_int_mix_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4, rx_prim_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, rx_sidetone_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, rx_sidetone_mix_text); static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, rx_sidetone_mix_text); static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0, iir_inp_mux_text); static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0, iir_inp_mux_text); static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0, iir_inp_mux_text); static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0, iir_inp_mux_text); static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0, iir_inp_mux_text); static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0, iir_inp_mux_text); static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0, iir_inp_mux_text); static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0, iir_inp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0, rx_int0_1_interp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0, rx_int1_1_interp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0, rx_int2_1_interp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0, rx_int0_2_interp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0, rx_int1_2_interp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0, rx_int2_2_interp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0, rx_int_dem_inp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0, rx_int_dem_inp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_2_5_int1_dem_inp_enum, CDC_2_5_RX_RX1_RX_PATH_CFG1, 0, rx_int_dem_inp_mux_text); static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); static const struct snd_kcontrol_new rx_mix_tx1_mux = …; static const struct snd_kcontrol_new rx_mix_tx2_mux = …; static const struct snd_kcontrol_new rx_int0_2_mux = …; static const struct snd_kcontrol_new rx_int1_2_mux = …; static const struct snd_kcontrol_new rx_int2_2_mux = …; static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = …; static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = …; static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = …; static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = …; static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = …; static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = …; static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = …; static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = …; static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = …; static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = …; static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = …; static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = …; static const struct snd_kcontrol_new iir0_inp0_mux = …; static const struct snd_kcontrol_new iir0_inp1_mux = …; static const struct snd_kcontrol_new iir0_inp2_mux = …; static const struct snd_kcontrol_new iir0_inp3_mux = …; static const struct snd_kcontrol_new iir1_inp0_mux = …; static const struct snd_kcontrol_new iir1_inp1_mux = …; static const struct snd_kcontrol_new iir1_inp2_mux = …; static const struct snd_kcontrol_new iir1_inp3_mux = …; static const struct snd_kcontrol_new rx_int0_1_interp_mux = …; static const struct snd_kcontrol_new rx_int1_1_interp_mux = …; static const struct snd_kcontrol_new rx_int2_1_interp_mux = …; static const struct snd_kcontrol_new rx_int0_2_interp_mux = …; static const struct snd_kcontrol_new rx_int1_2_interp_mux = …; static const struct snd_kcontrol_new rx_int2_2_interp_mux = …; static const struct snd_kcontrol_new rx_mix_tx0_mux = …; static const struct reg_default rx_defaults[] = …; static const struct reg_default rx_2_5_defaults[] = …; static const struct reg_default rx_pre_2_5_defaults[] = …; static bool rx_is_wronly_register(struct device *dev, unsigned int reg) { … } static bool rx_is_volatile_register(struct device *dev, unsigned int reg) { … } static bool rx_pre_2_5_is_rw_register(struct device *dev, unsigned int reg) { … } static bool rx_2_5_is_rw_register(struct device *dev, unsigned int reg) { … } static bool rx_is_rw_register(struct device *dev, unsigned int reg) { … } static bool rx_is_writeable_register(struct device *dev, unsigned int reg) { … } static bool rx_is_readable_register(struct device *dev, unsigned int reg) { … } static const struct regmap_config rx_regmap_config = …; static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static const struct snd_kcontrol_new rx_int0_dem_inp_mux = …; static const struct snd_kcontrol_new rx_int1_dem_inp_mux = …; static const struct snd_kcontrol_new rx_2_5_int1_dem_inp_mux = …; static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, int rate_reg_val, u32 sample_rate) { … } static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, int rate_reg_val, u32 sample_rate) { … } static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai, u32 sample_rate) { … } static int rx_macro_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static int rx_macro_get_channel_map(const struct snd_soc_dai *dai, unsigned int *tx_num, unsigned int *tx_slot, unsigned int *rx_num, unsigned int *rx_slot) { … } static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) { … } static const struct snd_soc_dai_ops rx_macro_dai_ops = …; static struct snd_soc_dai_driver rx_macro_dai[] = …; static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) { … } static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static bool rx_macro_adie_lb(struct snd_soc_component *component, int interp_idx) { … } static int rx_macro_enable_interp_clk(struct snd_soc_component *component, int event, int interp_idx); static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int rx_macro_config_compander(struct snd_soc_component *component, struct rx_macro *rx, int comp, int event) { … } static int rx_macro_load_compander_coeff(struct snd_soc_component *component, struct rx_macro *rx, int comp, int event) { … } static void rx_macro_enable_softclip_clk(struct snd_soc_component *component, struct rx_macro *rx, bool enable) { … } static int rx_macro_config_softclip(struct snd_soc_component *component, struct rx_macro *rx, int event) { … } static int rx_macro_config_aux_hpf(struct snd_soc_component *component, struct rx_macro *rx, int event) { … } static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) { … } static int rx_macro_config_classh(struct snd_soc_component *component, struct rx_macro *rx, int interp_n, int event) { … } static void rx_macro_hd2_control(struct snd_soc_component *component, u16 interp_idx, int event) { … } static int rx_macro_get_compander(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_set_compander(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static const struct snd_kcontrol_new rx_macro_rx0_mux = …; static const struct snd_kcontrol_new rx_macro_rx1_mux = …; static const struct snd_kcontrol_new rx_macro_rx2_mux = …; static const struct snd_kcontrol_new rx_macro_rx3_mux = …; static const struct snd_kcontrol_new rx_macro_rx4_mux = …; static const struct snd_kcontrol_new rx_macro_rx5_mux = …; static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component, struct rx_macro *rx, u16 interp_idx, int event) { … } static int rx_macro_enable_interp_clk(struct snd_soc_component *component, int event, int interp_idx) { … } static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static uint32_t get_iir_band_coeff(struct snd_soc_component *component, int iir_idx, int band_idx, int coeff_idx) { … } static void set_iir_band_coeff(struct snd_soc_component *component, int iir_idx, int band_idx, uint32_t value) { … } static int rx_macro_put_iir_band_audio_mixer( struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *ucontrol) { … } static const struct snd_kcontrol_new rx_macro_def_snd_controls[] = …; static const struct snd_kcontrol_new rx_macro_2_5_snd_controls[] = …; static const struct snd_kcontrol_new rx_macro_snd_controls[] = …; static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { … } static const struct snd_soc_dapm_widget rx_macro_2_5_dapm_widgets[] = …; static const struct snd_soc_dapm_widget rx_macro_def_dapm_widgets[] = …; static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = …; static const struct snd_soc_dapm_route rx_audio_map[] = …; static int rx_macro_component_probe(struct snd_soc_component *component) { … } static int swclk_gate_enable(struct clk_hw *hw) { … } static void swclk_gate_disable(struct clk_hw *hw) { … } static int swclk_gate_is_enabled(struct clk_hw *hw) { … } static unsigned long swclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops swclk_gate_ops = …; static int rx_macro_register_mclk_output(struct rx_macro *rx) { … } static const struct snd_soc_component_driver rx_macro_component_drv = …; static int rx_macro_probe(struct platform_device *pdev) { … } static void rx_macro_remove(struct platform_device *pdev) { … } static const struct of_device_id rx_macro_dt_match[] = …; MODULE_DEVICE_TABLE(of, rx_macro_dt_match); static int __maybe_unused rx_macro_runtime_suspend(struct device *dev) { … } static int __maybe_unused rx_macro_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops rx_macro_pm_ops = …; static struct platform_driver rx_macro_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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