linux/drivers/clk/renesas/r8a779a0-cpg-mssr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2020 Renesas Electronics Corp.
 *
 * Based on r8a7795-cpg-mssr.c
 *
 * Copyright (C) 2015 Glider bvba
 * Copyright (C) 2015 Renesas Electronics Corp.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>

#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen4-cpg.h"

enum clk_ids { … };

#define DEF_PLL(_name, _id, _offset) …

static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = …;

static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = …;

static const unsigned int r8a779a0_crit_mod_clks[] __initconst = …;

/*
 * CPG Clock Data
 */
/*
 *   MD	 EXTAL		PLL1	PLL20	PLL30	PLL4	PLL5	OSC
 * 14 13 (MHz)			   21	   31
 * ----------------------------------------------------------------
 * 0  0	 16.66 x 1	x128	x216	x128	x144	x192	/16
 * 0  1	 20    x 1	x106	x180	x106	x120	x160	/19
 * 1  0	 Prohibited setting
 * 1  1	 33.33 / 2	x128	x216	x128	x144	x192	/32
 */
#define CPG_PLL_CONFIG_INDEX(md) …
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = …;


static int __init r8a779a0_cpg_mssr_init(struct device *dev)
{ … }

const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = …;