linux/drivers/clk/renesas/r8a779f0-cpg-mssr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 *
 * Based on r8a779a0-cpg-mssr.c
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>

#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen4-cpg.h"

enum clk_ids { … };

static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = …;

static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = …;

static const unsigned int r8a779f0_crit_mod_clks[] __initconst = …;

/*
 * CPG Clock Data
 */
/*
 *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL4	PLL5	PLL6	OSC
 * 14 13 (MHz)
 * ------------------------------------------------------------------------
 * 0  0	 16    / 1	x200	x150	x200	n/a	x200	x134	/15
 * 0  1	 20    / 1	x160	x120	x160	n/a	x160	x106	/19
 * 1  0	 Prohibited setting
 * 1  1	 40    / 2	x160	x120	x160	n/a	x160	x106	/38
 */
#define CPG_PLL_CONFIG_INDEX(md) …

static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = …;

static int __init r8a779f0_cpg_mssr_init(struct device *dev)
{ … }

const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = …;