/* SPDX-License-Identifier: GPL-2.0+ */ /* * AMD ALSA SoC PDM Driver * * Copyright 2020 Advanced Micro Devices, Inc. */ #include "rn_chip_offset_byte.h" #define ACP_DEVS … #define ACP_PHY_BASE_ADDRESS … #define ACP_REG_START … #define ACP_REG_END … #define ACP_DEVICE_ID … #define ACP_POWER_ON … #define ACP_POWER_ON_IN_PROGRESS … #define ACP_POWER_OFF … #define ACP_POWER_OFF_IN_PROGRESS … #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK … #define ACP_PGFSM_CNTL_POWER_ON_MASK … #define ACP_PGFSM_CNTL_POWER_OFF_MASK … #define ACP_PGFSM_STATUS_MASK … #define ACP_POWERED_ON … #define ACP_POWER_ON_IN_PROGRESS … #define ACP_POWERED_OFF … #define ACP_POWER_OFF_IN_PROGRESS … #define ACP_ERROR_MASK … #define ACP_EXT_INTR_STAT_CLEAR_MASK … #define PDM_DMA_STAT … #define PDM_DMA_INTR_MASK … #define ACP_ERROR_STAT … #define PDM_DECIMATION_FACTOR … #define ACP_PDM_CLK_FREQ_MASK … #define ACP_WOV_GAIN_CONTROL … #define ACP_PDM_ENABLE … #define ACP_PDM_DISABLE … #define ACP_PDM_DMA_EN_STATUS … #define TWO_CH … #define DELAY_US … #define ACP_COUNTER … /* time in ms for runtime suspend delay */ #define ACP_SUSPEND_DELAY_MS … #define ACP_SRAM_PTE_OFFSET … #define PAGE_SIZE_4K_ENABLE … #define MEM_WINDOW_START … #define CAPTURE_MIN_NUM_PERIODS … #define CAPTURE_MAX_NUM_PERIODS … #define CAPTURE_MAX_PERIOD_SIZE … #define CAPTURE_MIN_PERIOD_SIZE … #define MAX_BUFFER … #define MIN_BUFFER … #define ACP_DMIC_AUTO … struct pdm_dev_data { … }; struct pdm_stream_instance { … }; acp_pdm_dma_count; static inline u32 rn_readl(void __iomem *base_addr) { … } static inline void rn_writel(u32 val, void __iomem *base_addr) { … } /* Machine configuration */ int snd_amd_acp_find_config(struct pci_dev *pci);
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