/* SPDX-License-Identifier: GPL-2.0 */ /* * R9A06G032 sysctrl IDs * * Copyright (C) 2018 Renesas Electronics Europe Limited * * Michel Pollet <[email protected]>, <[email protected]> */ #ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ #define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ #define R9A06G032_CLK_PLL_USB … #define R9A06G032_CLK_48 … #define R9A06G032_MSEBIS_CLK … #define R9A06G032_MSEBIM_CLK … #define R9A06G032_CLK_DDRPHY_PLLCLK … #define R9A06G032_CLK50 … #define R9A06G032_CLK25 … #define R9A06G032_CLK125 … #define R9A06G032_CLK_P5_PG1 … #define R9A06G032_CLK_REF_SYNC … #define R9A06G032_CLK_25_PG4 … #define R9A06G032_CLK_25_PG5 … #define R9A06G032_CLK_25_PG6 … #define R9A06G032_CLK_25_PG7 … #define R9A06G032_CLK_25_PG8 … #define R9A06G032_CLK_ADC … #define R9A06G032_CLK_ECAT100 … #define R9A06G032_CLK_HSR100 … #define R9A06G032_CLK_I2C0 … #define R9A06G032_CLK_I2C1 … #define R9A06G032_CLK_MII_REF … #define R9A06G032_CLK_NAND … #define R9A06G032_CLK_NOUSBP2_PG6 … #define R9A06G032_CLK_P1_PG2 … #define R9A06G032_CLK_P1_PG3 … #define R9A06G032_CLK_P1_PG4 … #define R9A06G032_CLK_P4_PG3 … #define R9A06G032_CLK_P4_PG4 … #define R9A06G032_CLK_P6_PG1 … #define R9A06G032_CLK_P6_PG2 … #define R9A06G032_CLK_P6_PG3 … #define R9A06G032_CLK_P6_PG4 … #define R9A06G032_CLK_PCI_USB … #define R9A06G032_CLK_QSPI0 … #define R9A06G032_CLK_QSPI1 … #define R9A06G032_CLK_RGMII_REF … #define R9A06G032_CLK_RMII_REF … #define R9A06G032_CLK_SDIO0 … #define R9A06G032_CLK_SDIO1 … #define R9A06G032_CLK_SERCOS100 … #define R9A06G032_CLK_SLCD … #define R9A06G032_CLK_SPI0 … #define R9A06G032_CLK_SPI1 … #define R9A06G032_CLK_SPI2 … #define R9A06G032_CLK_SPI3 … #define R9A06G032_CLK_SPI4 … #define R9A06G032_CLK_SPI5 … #define R9A06G032_CLK_SWITCH … #define R9A06G032_HCLK_ECAT125 … #define R9A06G032_HCLK_PINCONFIG … #define R9A06G032_HCLK_SERCOS … #define R9A06G032_HCLK_SGPIO2 … #define R9A06G032_HCLK_SGPIO3 … #define R9A06G032_HCLK_SGPIO4 … #define R9A06G032_HCLK_TIMER0 … #define R9A06G032_HCLK_TIMER1 … #define R9A06G032_HCLK_USBF … #define R9A06G032_HCLK_USBH … #define R9A06G032_HCLK_USBPM … #define R9A06G032_CLK_48_PG_F … #define R9A06G032_CLK_48_PG4 … #define R9A06G032_CLK_DDRPHY_PCLK … #define R9A06G032_CLK_FW … #define R9A06G032_CLK_CRYPTO … #define R9A06G032_CLK_WATCHDOG … #define R9A06G032_CLK_A7MP … #define R9A06G032_HCLK_CAN0 … #define R9A06G032_HCLK_CAN1 … #define R9A06G032_HCLK_DELTASIGMA … #define R9A06G032_HCLK_PWMPTO … #define R9A06G032_HCLK_RSV … #define R9A06G032_HCLK_SGPIO0 … #define R9A06G032_HCLK_SGPIO1 … #define R9A06G032_RTOS_MDC … #define R9A06G032_CLK_CM3 … #define R9A06G032_CLK_DDRC … #define R9A06G032_CLK_ECAT25 … #define R9A06G032_CLK_HSR50 … #define R9A06G032_CLK_HW_RTOS … #define R9A06G032_CLK_SERCOS50 … #define R9A06G032_HCLK_ADC … #define R9A06G032_HCLK_CM3 … #define R9A06G032_HCLK_CRYPTO_EIP150 … #define R9A06G032_HCLK_CRYPTO_EIP93 … #define R9A06G032_HCLK_DDRC … #define R9A06G032_HCLK_DMA0 … #define R9A06G032_HCLK_DMA1 … #define R9A06G032_HCLK_GMAC0 … #define R9A06G032_HCLK_GMAC1 … #define R9A06G032_HCLK_GPIO0 … #define R9A06G032_HCLK_GPIO1 … #define R9A06G032_HCLK_GPIO2 … #define R9A06G032_HCLK_HSR … #define R9A06G032_HCLK_I2C0 … #define R9A06G032_HCLK_I2C1 … #define R9A06G032_HCLK_LCD … #define R9A06G032_HCLK_MSEBI_M … #define R9A06G032_HCLK_MSEBI_S … #define R9A06G032_HCLK_NAND … #define R9A06G032_HCLK_PG_I … #define R9A06G032_HCLK_PG19 … #define R9A06G032_HCLK_PG20 … #define R9A06G032_HCLK_PG3 … #define R9A06G032_HCLK_PG4 … #define R9A06G032_HCLK_QSPI0 … #define R9A06G032_HCLK_QSPI1 … #define R9A06G032_HCLK_ROM … #define R9A06G032_HCLK_RTC … #define R9A06G032_HCLK_SDIO0 … #define R9A06G032_HCLK_SDIO1 … #define R9A06G032_HCLK_SEMAP … #define R9A06G032_HCLK_SPI0 … #define R9A06G032_HCLK_SPI1 … #define R9A06G032_HCLK_SPI2 … #define R9A06G032_HCLK_SPI3 … #define R9A06G032_HCLK_SPI4 … #define R9A06G032_HCLK_SPI5 … #define R9A06G032_HCLK_SWITCH … #define R9A06G032_HCLK_SWITCH_RG … #define R9A06G032_HCLK_UART0 … #define R9A06G032_HCLK_UART1 … #define R9A06G032_HCLK_UART2 … #define R9A06G032_HCLK_UART3 … #define R9A06G032_HCLK_UART4 … #define R9A06G032_HCLK_UART5 … #define R9A06G032_HCLK_UART6 … #define R9A06G032_HCLK_UART7 … #define R9A06G032_CLK_UART0 … #define R9A06G032_CLK_UART1 … #define R9A06G032_CLK_UART2 … #define R9A06G032_CLK_UART3 … #define R9A06G032_CLK_UART4 … #define R9A06G032_CLK_UART5 … #define R9A06G032_CLK_UART6 … #define R9A06G032_CLK_UART7 … #endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
Codebase Browser
linux