/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) * * Copyright (C) 2023 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ #define __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ #include <dt-bindings/clock/renesas-cpg-mssr.h> /* R9A08G045 CPG Core Clocks */ #define R9A08G045_CLK_I … #define R9A08G045_CLK_I2 … #define R9A08G045_CLK_I3 … #define R9A08G045_CLK_S0 … #define R9A08G045_CLK_SPI0 … #define R9A08G045_CLK_SPI1 … #define R9A08G045_CLK_SD0 … #define R9A08G045_CLK_SD1 … #define R9A08G045_CLK_SD2 … #define R9A08G045_CLK_M0 … #define R9A08G045_CLK_HP … #define R9A08G045_CLK_TSU … #define R9A08G045_CLK_ZT … #define R9A08G045_CLK_P0 … #define R9A08G045_CLK_P1 … #define R9A08G045_CLK_P2 … #define R9A08G045_CLK_P3 … #define R9A08G045_CLK_P4 … #define R9A08G045_CLK_P5 … #define R9A08G045_CLK_AT … #define R9A08G045_CLK_OC0 … #define R9A08G045_CLK_OC1 … #define R9A08G045_OSCCLK … #define R9A08G045_OSCCLK2 … #define R9A08G045_SWD … /* R9A08G045 Module Clocks */ #define R9A08G045_OCTA_ACLK … #define R9A08G045_OCTA_MCLK … #define R9A08G045_CA55_SCLK … #define R9A08G045_CA55_PCLK … #define R9A08G045_CA55_ATCLK … #define R9A08G045_CA55_GICCLK … #define R9A08G045_CA55_PERICLK … #define R9A08G045_CA55_ACLK … #define R9A08G045_CA55_TSCLK … #define R9A08G045_SRAM_ACPU_ACLK0 … #define R9A08G045_SRAM_ACPU_ACLK1 … #define R9A08G045_SRAM_ACPU_ACLK2 … #define R9A08G045_GIC600_GICCLK … #define R9A08G045_IA55_CLK … #define R9A08G045_IA55_PCLK … #define R9A08G045_MHU_PCLK … #define R9A08G045_SYC_CNT_CLK … #define R9A08G045_DMAC_ACLK … #define R9A08G045_DMAC_PCLK … #define R9A08G045_OSTM0_PCLK … #define R9A08G045_OSTM1_PCLK … #define R9A08G045_OSTM2_PCLK … #define R9A08G045_OSTM3_PCLK … #define R9A08G045_OSTM4_PCLK … #define R9A08G045_OSTM5_PCLK … #define R9A08G045_OSTM6_PCLK … #define R9A08G045_OSTM7_PCLK … #define R9A08G045_MTU_X_MCK_MTU3 … #define R9A08G045_POE3_CLKM_POE … #define R9A08G045_GPT_PCLK … #define R9A08G045_POEG_A_CLKP … #define R9A08G045_POEG_B_CLKP … #define R9A08G045_POEG_C_CLKP … #define R9A08G045_POEG_D_CLKP … #define R9A08G045_WDT0_PCLK … #define R9A08G045_WDT0_CLK … #define R9A08G045_WDT1_PCLK … #define R9A08G045_WDT1_CLK … #define R9A08G045_WDT2_PCLK … #define R9A08G045_WDT2_CLK … #define R9A08G045_SPI_HCLK … #define R9A08G045_SPI_ACLK … #define R9A08G045_SPI_CLK … #define R9A08G045_SPI_CLKX2 … #define R9A08G045_SDHI0_IMCLK … #define R9A08G045_SDHI0_IMCLK2 … #define R9A08G045_SDHI0_CLK_HS … #define R9A08G045_SDHI0_ACLK … #define R9A08G045_SDHI1_IMCLK … #define R9A08G045_SDHI1_IMCLK2 … #define R9A08G045_SDHI1_CLK_HS … #define R9A08G045_SDHI1_ACLK … #define R9A08G045_SDHI2_IMCLK … #define R9A08G045_SDHI2_IMCLK2 … #define R9A08G045_SDHI2_CLK_HS … #define R9A08G045_SDHI2_ACLK … #define R9A08G045_SSI0_PCLK2 … #define R9A08G045_SSI0_PCLK_SFR … #define R9A08G045_SSI1_PCLK2 … #define R9A08G045_SSI1_PCLK_SFR … #define R9A08G045_SSI2_PCLK2 … #define R9A08G045_SSI2_PCLK_SFR … #define R9A08G045_SSI3_PCLK2 … #define R9A08G045_SSI3_PCLK_SFR … #define R9A08G045_SRC_CLKP … #define R9A08G045_USB_U2H0_HCLK … #define R9A08G045_USB_U2H1_HCLK … #define R9A08G045_USB_U2P_EXR_CPUCLK … #define R9A08G045_USB_PCLK … #define R9A08G045_ETH0_CLK_AXI … #define R9A08G045_ETH0_CLK_CHI … #define R9A08G045_ETH0_REFCLK … #define R9A08G045_ETH1_CLK_AXI … #define R9A08G045_ETH1_CLK_CHI … #define R9A08G045_ETH1_REFCLK … #define R9A08G045_I2C0_PCLK … #define R9A08G045_I2C1_PCLK … #define R9A08G045_I2C2_PCLK … #define R9A08G045_I2C3_PCLK … #define R9A08G045_SCIF0_CLK_PCK … #define R9A08G045_SCIF1_CLK_PCK … #define R9A08G045_SCIF2_CLK_PCK … #define R9A08G045_SCIF3_CLK_PCK … #define R9A08G045_SCIF4_CLK_PCK … #define R9A08G045_SCIF5_CLK_PCK … #define R9A08G045_SCI0_CLKP … #define R9A08G045_SCI1_CLKP … #define R9A08G045_IRDA_CLKP … #define R9A08G045_RSPI0_CLKB … #define R9A08G045_RSPI1_CLKB … #define R9A08G045_RSPI2_CLKB … #define R9A08G045_RSPI3_CLKB … #define R9A08G045_RSPI4_CLKB … #define R9A08G045_CANFD_PCLK … #define R9A08G045_CANFD_CLK_RAM … #define R9A08G045_GPIO_HCLK … #define R9A08G045_ADC_ADCLK … #define R9A08G045_ADC_PCLK … #define R9A08G045_TSU_PCLK … #define R9A08G045_PDM_PCLK … #define R9A08G045_PDM_CCLK … #define R9A08G045_PCI_ACLK … #define R9A08G045_PCI_CLKL1PM … #define R9A08G045_SPDIF_PCLK … #define R9A08G045_I3C_PCLK … #define R9A08G045_I3C_TCLK … #define R9A08G045_VBAT_BCLK … /* R9A08G045 Resets */ #define R9A08G045_CA55_RST_1_0 … #define R9A08G045_CA55_RST_3_0 … #define R9A08G045_CA55_RST_4 … #define R9A08G045_CA55_RST_5 … #define R9A08G045_CA55_RST_6 … #define R9A08G045_CA55_RST_7 … #define R9A08G045_CA55_RST_8 … #define R9A08G045_CA55_RST_9 … #define R9A08G045_CA55_RST_10 … #define R9A08G045_CA55_RST_11 … #define R9A08G045_CA55_RST_12 … #define R9A08G045_SRAM_ACPU_ARESETN0 … #define R9A08G045_SRAM_ACPU_ARESETN1 … #define R9A08G045_SRAM_ACPU_ARESETN2 … #define R9A08G045_GIC600_GICRESET_N … #define R9A08G045_GIC600_DBG_GICRESET_N … #define R9A08G045_IA55_RESETN … #define R9A08G045_MHU_RESETN … #define R9A08G045_DMAC_ARESETN … #define R9A08G045_DMAC_RST_ASYNC … #define R9A08G045_SYC_RESETN … #define R9A08G045_OSTM0_PRESETZ … #define R9A08G045_OSTM1_PRESETZ … #define R9A08G045_OSTM2_PRESETZ … #define R9A08G045_OSTM3_PRESETZ … #define R9A08G045_OSTM4_PRESETZ … #define R9A08G045_OSTM5_PRESETZ … #define R9A08G045_OSTM6_PRESETZ … #define R9A08G045_OSTM7_PRESETZ … #define R9A08G045_MTU_X_PRESET_MTU3 … #define R9A08G045_POE3_RST_M_REG … #define R9A08G045_GPT_RST_C … #define R9A08G045_POEG_A_RST … #define R9A08G045_POEG_B_RST … #define R9A08G045_POEG_C_RST … #define R9A08G045_POEG_D_RST … #define R9A08G045_WDT0_PRESETN … #define R9A08G045_WDT1_PRESETN … #define R9A08G045_WDT2_PRESETN … #define R9A08G045_SPI_HRESETN … #define R9A08G045_SPI_ARESETN … #define R9A08G045_SDHI0_IXRST … #define R9A08G045_SDHI1_IXRST … #define R9A08G045_SDHI2_IXRST … #define R9A08G045_SSI0_RST_M2_REG … #define R9A08G045_SSI1_RST_M2_REG … #define R9A08G045_SSI2_RST_M2_REG … #define R9A08G045_SSI3_RST_M2_REG … #define R9A08G045_SRC_RST … #define R9A08G045_USB_U2H0_HRESETN … #define R9A08G045_USB_U2H1_HRESETN … #define R9A08G045_USB_U2P_EXL_SYSRST … #define R9A08G045_USB_PRESETN … #define R9A08G045_ETH0_RST_HW_N … #define R9A08G045_ETH1_RST_HW_N … #define R9A08G045_I2C0_MRST … #define R9A08G045_I2C1_MRST … #define R9A08G045_I2C2_MRST … #define R9A08G045_I2C3_MRST … #define R9A08G045_SCIF0_RST_SYSTEM_N … #define R9A08G045_SCIF1_RST_SYSTEM_N … #define R9A08G045_SCIF2_RST_SYSTEM_N … #define R9A08G045_SCIF3_RST_SYSTEM_N … #define R9A08G045_SCIF4_RST_SYSTEM_N … #define R9A08G045_SCIF5_RST_SYSTEM_N … #define R9A08G045_SCI0_RST … #define R9A08G045_SCI1_RST … #define R9A08G045_IRDA_RST … #define R9A08G045_RSPI0_RST … #define R9A08G045_RSPI1_RST … #define R9A08G045_RSPI2_RST … #define R9A08G045_RSPI3_RST … #define R9A08G045_RSPI4_RST … #define R9A08G045_CANFD_RSTP_N … #define R9A08G045_CANFD_RSTC_N … #define R9A08G045_GPIO_RSTN … #define R9A08G045_GPIO_PORT_RESETN … #define R9A08G045_GPIO_SPARE_RESETN … #define R9A08G045_ADC_PRESETN … #define R9A08G045_ADC_ADRST_N … #define R9A08G045_TSU_PRESETN … #define R9A08G045_OCTA_ARESETN … #define R9A08G045_PDM0_PRESETNT … #define R9A08G045_PCI_ARESETN … #define R9A08G045_PCI_RST_B … #define R9A08G045_PCI_RST_GP_B … #define R9A08G045_PCI_RST_PS_B … #define R9A08G045_PCI_RST_RSM_B … #define R9A08G045_PCI_RST_CFG_B … #define R9A08G045_PCI_RST_LOAD_B … #define R9A08G045_SPDIF_RST … #define R9A08G045_I3C_TRESETN … #define R9A08G045_I3C_PRESETN … #define R9A08G045_VBAT_BRESETN … /* Power domain IDs. */ #define R9A08G045_PD_ALWAYS_ON … #define R9A08G045_PD_GIC … #define R9A08G045_PD_IA55 … #define R9A08G045_PD_MHU … #define R9A08G045_PD_CORESIGHT … #define R9A08G045_PD_SYC … #define R9A08G045_PD_DMAC … #define R9A08G045_PD_GTM0 … #define R9A08G045_PD_GTM1 … #define R9A08G045_PD_GTM2 … #define R9A08G045_PD_GTM3 … #define R9A08G045_PD_GTM4 … #define R9A08G045_PD_GTM5 … #define R9A08G045_PD_GTM6 … #define R9A08G045_PD_GTM7 … #define R9A08G045_PD_MTU … #define R9A08G045_PD_POE3 … #define R9A08G045_PD_GPT … #define R9A08G045_PD_POEGA … #define R9A08G045_PD_POEGB … #define R9A08G045_PD_POEGC … #define R9A08G045_PD_POEGD … #define R9A08G045_PD_WDT0 … #define R9A08G045_PD_XSPI … #define R9A08G045_PD_SDHI0 … #define R9A08G045_PD_SDHI1 … #define R9A08G045_PD_SDHI2 … #define R9A08G045_PD_SSI0 … #define R9A08G045_PD_SSI1 … #define R9A08G045_PD_SSI2 … #define R9A08G045_PD_SSI3 … #define R9A08G045_PD_SRC … #define R9A08G045_PD_USB0 … #define R9A08G045_PD_USB1 … #define R9A08G045_PD_USB_PHY … #define R9A08G045_PD_ETHER0 … #define R9A08G045_PD_ETHER1 … #define R9A08G045_PD_I2C0 … #define R9A08G045_PD_I2C1 … #define R9A08G045_PD_I2C2 … #define R9A08G045_PD_I2C3 … #define R9A08G045_PD_SCIF0 … #define R9A08G045_PD_SCIF1 … #define R9A08G045_PD_SCIF2 … #define R9A08G045_PD_SCIF3 … #define R9A08G045_PD_SCIF4 … #define R9A08G045_PD_SCIF5 … #define R9A08G045_PD_SCI0 … #define R9A08G045_PD_SCI1 … #define R9A08G045_PD_IRDA … #define R9A08G045_PD_RSPI0 … #define R9A08G045_PD_RSPI1 … #define R9A08G045_PD_RSPI2 … #define R9A08G045_PD_RSPI3 … #define R9A08G045_PD_RSPI4 … #define R9A08G045_PD_CANFD … #define R9A08G045_PD_ADC … #define R9A08G045_PD_TSU … #define R9A08G045_PD_OCTA … #define R9A08G045_PD_PDM … #define R9A08G045_PD_PCI … #define R9A08G045_PD_SPDIF … #define R9A08G045_PD_I3C … #define R9A08G045_PD_VBAT … #define R9A08G045_PD_DDR … #define R9A08G045_PD_TZCDDR … #define R9A08G045_PD_OTFDE_DDR … #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
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