/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) * * Copyright (C) 2021 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ #define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ #include <dt-bindings/clock/renesas-cpg-mssr.h> /* R9A07G044 CPG Core Clocks */ #define R9A07G044_CLK_I … #define R9A07G044_CLK_I2 … #define R9A07G044_CLK_G … #define R9A07G044_CLK_S0 … #define R9A07G044_CLK_S1 … #define R9A07G044_CLK_SPI0 … #define R9A07G044_CLK_SPI1 … #define R9A07G044_CLK_SD0 … #define R9A07G044_CLK_SD1 … #define R9A07G044_CLK_M0 … #define R9A07G044_CLK_M1 … #define R9A07G044_CLK_M2 … #define R9A07G044_CLK_M3 … #define R9A07G044_CLK_M4 … #define R9A07G044_CLK_HP … #define R9A07G044_CLK_TSU … #define R9A07G044_CLK_ZT … #define R9A07G044_CLK_P0 … #define R9A07G044_CLK_P1 … #define R9A07G044_CLK_P2 … #define R9A07G044_CLK_AT … #define R9A07G044_OSCCLK … #define R9A07G044_CLK_P0_DIV2 … /* R9A07G044 Module Clocks */ #define R9A07G044_CA55_SCLK … #define R9A07G044_CA55_PCLK … #define R9A07G044_CA55_ATCLK … #define R9A07G044_CA55_GICCLK … #define R9A07G044_CA55_PERICLK … #define R9A07G044_CA55_ACLK … #define R9A07G044_CA55_TSCLK … #define R9A07G044_GIC600_GICCLK … #define R9A07G044_IA55_CLK … #define R9A07G044_IA55_PCLK … #define R9A07G044_MHU_PCLK … #define R9A07G044_SYC_CNT_CLK … #define R9A07G044_DMAC_ACLK … #define R9A07G044_DMAC_PCLK … #define R9A07G044_OSTM0_PCLK … #define R9A07G044_OSTM1_PCLK … #define R9A07G044_OSTM2_PCLK … #define R9A07G044_MTU_X_MCK_MTU3 … #define R9A07G044_POE3_CLKM_POE … #define R9A07G044_GPT_PCLK … #define R9A07G044_POEG_A_CLKP … #define R9A07G044_POEG_B_CLKP … #define R9A07G044_POEG_C_CLKP … #define R9A07G044_POEG_D_CLKP … #define R9A07G044_WDT0_PCLK … #define R9A07G044_WDT0_CLK … #define R9A07G044_WDT1_PCLK … #define R9A07G044_WDT1_CLK … #define R9A07G044_WDT2_PCLK … #define R9A07G044_WDT2_CLK … #define R9A07G044_SPI_CLK2 … #define R9A07G044_SPI_CLK … #define R9A07G044_SDHI0_IMCLK … #define R9A07G044_SDHI0_IMCLK2 … #define R9A07G044_SDHI0_CLK_HS … #define R9A07G044_SDHI0_ACLK … #define R9A07G044_SDHI1_IMCLK … #define R9A07G044_SDHI1_IMCLK2 … #define R9A07G044_SDHI1_CLK_HS … #define R9A07G044_SDHI1_ACLK … #define R9A07G044_GPU_CLK … #define R9A07G044_GPU_AXI_CLK … #define R9A07G044_GPU_ACE_CLK … #define R9A07G044_ISU_ACLK … #define R9A07G044_ISU_PCLK … #define R9A07G044_H264_CLK_A … #define R9A07G044_H264_CLK_P … #define R9A07G044_CRU_SYSCLK … #define R9A07G044_CRU_VCLK … #define R9A07G044_CRU_PCLK … #define R9A07G044_CRU_ACLK … #define R9A07G044_MIPI_DSI_PLLCLK … #define R9A07G044_MIPI_DSI_SYSCLK … #define R9A07G044_MIPI_DSI_ACLK … #define R9A07G044_MIPI_DSI_PCLK … #define R9A07G044_MIPI_DSI_VCLK … #define R9A07G044_MIPI_DSI_LPCLK … #define R9A07G044_LCDC_CLK_A … #define R9A07G044_LCDC_CLK_P … #define R9A07G044_LCDC_CLK_D … #define R9A07G044_SSI0_PCLK2 … #define R9A07G044_SSI0_PCLK_SFR … #define R9A07G044_SSI1_PCLK2 … #define R9A07G044_SSI1_PCLK_SFR … #define R9A07G044_SSI2_PCLK2 … #define R9A07G044_SSI2_PCLK_SFR … #define R9A07G044_SSI3_PCLK2 … #define R9A07G044_SSI3_PCLK_SFR … #define R9A07G044_SRC_CLKP … #define R9A07G044_USB_U2H0_HCLK … #define R9A07G044_USB_U2H1_HCLK … #define R9A07G044_USB_U2P_EXR_CPUCLK … #define R9A07G044_USB_PCLK … #define R9A07G044_ETH0_CLK_AXI … #define R9A07G044_ETH0_CLK_CHI … #define R9A07G044_ETH1_CLK_AXI … #define R9A07G044_ETH1_CLK_CHI … #define R9A07G044_I2C0_PCLK … #define R9A07G044_I2C1_PCLK … #define R9A07G044_I2C2_PCLK … #define R9A07G044_I2C3_PCLK … #define R9A07G044_SCIF0_CLK_PCK … #define R9A07G044_SCIF1_CLK_PCK … #define R9A07G044_SCIF2_CLK_PCK … #define R9A07G044_SCIF3_CLK_PCK … #define R9A07G044_SCIF4_CLK_PCK … #define R9A07G044_SCI0_CLKP … #define R9A07G044_SCI1_CLKP … #define R9A07G044_IRDA_CLKP … #define R9A07G044_RSPI0_CLKB … #define R9A07G044_RSPI1_CLKB … #define R9A07G044_RSPI2_CLKB … #define R9A07G044_CANFD_PCLK … #define R9A07G044_GPIO_HCLK … #define R9A07G044_ADC_ADCLK … #define R9A07G044_ADC_PCLK … #define R9A07G044_TSU_PCLK … /* R9A07G044 Resets */ #define R9A07G044_CA55_RST_1_0 … #define R9A07G044_CA55_RST_1_1 … #define R9A07G044_CA55_RST_3_0 … #define R9A07G044_CA55_RST_3_1 … #define R9A07G044_CA55_RST_4 … #define R9A07G044_CA55_RST_5 … #define R9A07G044_CA55_RST_6 … #define R9A07G044_CA55_RST_7 … #define R9A07G044_CA55_RST_8 … #define R9A07G044_CA55_RST_9 … #define R9A07G044_CA55_RST_10 … #define R9A07G044_CA55_RST_11 … #define R9A07G044_CA55_RST_12 … #define R9A07G044_GIC600_GICRESET_N … #define R9A07G044_GIC600_DBG_GICRESET_N … #define R9A07G044_IA55_RESETN … #define R9A07G044_MHU_RESETN … #define R9A07G044_DMAC_ARESETN … #define R9A07G044_DMAC_RST_ASYNC … #define R9A07G044_SYC_RESETN … #define R9A07G044_OSTM0_PRESETZ … #define R9A07G044_OSTM1_PRESETZ … #define R9A07G044_OSTM2_PRESETZ … #define R9A07G044_MTU_X_PRESET_MTU3 … #define R9A07G044_POE3_RST_M_REG … #define R9A07G044_GPT_RST_C … #define R9A07G044_POEG_A_RST … #define R9A07G044_POEG_B_RST … #define R9A07G044_POEG_C_RST … #define R9A07G044_POEG_D_RST … #define R9A07G044_WDT0_PRESETN … #define R9A07G044_WDT1_PRESETN … #define R9A07G044_WDT2_PRESETN … #define R9A07G044_SPI_RST … #define R9A07G044_SDHI0_IXRST … #define R9A07G044_SDHI1_IXRST … #define R9A07G044_GPU_RESETN … #define R9A07G044_GPU_AXI_RESETN … #define R9A07G044_GPU_ACE_RESETN … #define R9A07G044_ISU_ARESETN … #define R9A07G044_ISU_PRESETN … #define R9A07G044_H264_X_RESET_VCP … #define R9A07G044_H264_CP_PRESET_P … #define R9A07G044_CRU_CMN_RSTB … #define R9A07G044_CRU_PRESETN … #define R9A07G044_CRU_ARESETN … #define R9A07G044_MIPI_DSI_CMN_RSTB … #define R9A07G044_MIPI_DSI_ARESET_N … #define R9A07G044_MIPI_DSI_PRESET_N … #define R9A07G044_LCDC_RESET_N … #define R9A07G044_SSI0_RST_M2_REG … #define R9A07G044_SSI1_RST_M2_REG … #define R9A07G044_SSI2_RST_M2_REG … #define R9A07G044_SSI3_RST_M2_REG … #define R9A07G044_SRC_RST … #define R9A07G044_USB_U2H0_HRESETN … #define R9A07G044_USB_U2H1_HRESETN … #define R9A07G044_USB_U2P_EXL_SYSRST … #define R9A07G044_USB_PRESETN … #define R9A07G044_ETH0_RST_HW_N … #define R9A07G044_ETH1_RST_HW_N … #define R9A07G044_I2C0_MRST … #define R9A07G044_I2C1_MRST … #define R9A07G044_I2C2_MRST … #define R9A07G044_I2C3_MRST … #define R9A07G044_SCIF0_RST_SYSTEM_N … #define R9A07G044_SCIF1_RST_SYSTEM_N … #define R9A07G044_SCIF2_RST_SYSTEM_N … #define R9A07G044_SCIF3_RST_SYSTEM_N … #define R9A07G044_SCIF4_RST_SYSTEM_N … #define R9A07G044_SCI0_RST … #define R9A07G044_SCI1_RST … #define R9A07G044_IRDA_RST … #define R9A07G044_RSPI0_RST … #define R9A07G044_RSPI1_RST … #define R9A07G044_RSPI2_RST … #define R9A07G044_CANFD_RSTP_N … #define R9A07G044_CANFD_RSTC_N … #define R9A07G044_GPIO_RSTN … #define R9A07G044_GPIO_PORT_RESETN … #define R9A07G044_GPIO_SPARE_RESETN … #define R9A07G044_ADC_PRESETN … #define R9A07G044_ADC_ADRST_N … #define R9A07G044_TSU_PRESETN … /* Power domain IDs. */ #define R9A07G044_PD_ALWAYS_ON … #define R9A07G044_PD_GIC … #define R9A07G044_PD_IA55 … #define R9A07G044_PD_MHU … #define R9A07G044_PD_CORESIGHT … #define R9A07G044_PD_SYC … #define R9A07G044_PD_DMAC … #define R9A07G044_PD_GTM0 … #define R9A07G044_PD_GTM1 … #define R9A07G044_PD_GTM2 … #define R9A07G044_PD_MTU … #define R9A07G044_PD_POE3 … #define R9A07G044_PD_GPT … #define R9A07G044_PD_POEGA … #define R9A07G044_PD_POEGB … #define R9A07G044_PD_POEGC … #define R9A07G044_PD_POEGD … #define R9A07G044_PD_WDT0 … #define R9A07G044_PD_WDT1 … #define R9A07G044_PD_SPI … #define R9A07G044_PD_SDHI0 … #define R9A07G044_PD_SDHI1 … #define R9A07G044_PD_3DGE … #define R9A07G044_PD_ISU … #define R9A07G044_PD_VCPL4 … #define R9A07G044_PD_CRU … #define R9A07G044_PD_MIPI_DSI … #define R9A07G044_PD_LCDC … #define R9A07G044_PD_SSI0 … #define R9A07G044_PD_SSI1 … #define R9A07G044_PD_SSI2 … #define R9A07G044_PD_SSI3 … #define R9A07G044_PD_SRC … #define R9A07G044_PD_USB0 … #define R9A07G044_PD_USB1 … #define R9A07G044_PD_USB_PHY … #define R9A07G044_PD_ETHER0 … #define R9A07G044_PD_ETHER1 … #define R9A07G044_PD_I2C0 … #define R9A07G044_PD_I2C1 … #define R9A07G044_PD_I2C2 … #define R9A07G044_PD_I2C3 … #define R9A07G044_PD_SCIF0 … #define R9A07G044_PD_SCIF1 … #define R9A07G044_PD_SCIF2 … #define R9A07G044_PD_SCIF3 … #define R9A07G044_PD_SCIF4 … #define R9A07G044_PD_SCI0 … #define R9A07G044_PD_SCI1 … #define R9A07G044_PD_IRDA … #define R9A07G044_PD_RSPI0 … #define R9A07G044_PD_RSPI1 … #define R9A07G044_PD_RSPI2 … #define R9A07G044_PD_CANFD … #define R9A07G044_PD_ADC … #define R9A07G044_PD_TSU … #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
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