// SPDX-License-Identifier: GPL-2.0 /* * R9A06G032 clock driver * * Copyright (C) 2018 Renesas Electronics Europe Limited * * Michel Pollet <[email protected]>, <[email protected]> */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/math64.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_domain.h> #include <linux/slab.h> #include <linux/soc/renesas/r9a06g032-sysctrl.h> #include <linux/spinlock.h> #include <dt-bindings/clock/r9a06g032-sysctrl.h> #define R9A06G032_SYSCTRL_USB … #define R9A06G032_SYSCTRL_USB_H2MODE … #define R9A06G032_SYSCTRL_DMAMUX … /** * struct regbit - describe one bit in a register * @reg: offset of register relative to base address, * expressed in units of 32-bit words (not bytes), * @bit: which bit (0 to 31) in the register * * This structure is used to compactly encode the location * of a single bit in a register. Five bits are needed to * encode the bit number. With uint16_t data type, this * leaves 11 bits to encode a register offset up to 2047. * * Since registers are aligned on 32-bit boundaries, the * offset will be specified in 32-bit words rather than bytes. * This allows encoding an offset up to 0x1FFC (8188) bytes. * * Helper macro RB() takes care of converting the register * offset from bytes to 32-bit words. */ struct regbit { … }; #define RB(_reg, _bit) … /** * struct r9a06g032_gate - clock-related control bits * @gate: clock enable/disable * @reset: clock module reset (active low) * @ready: enables NoC forwarding of read/write requests to device, * (eg. device is ready to handle read/write requests) * @midle: request to idle the NoC interconnect * * Each of these fields describes a single bit in a register, * which controls some aspect of clock gating. The @gate field * is mandatory, this one enables/disables the clock. The * other fields are optional, with zero indicating "not used". * * In most cases there is a @reset bit which needs to be * de-asserted to bring the module out of reset. * * Modules may also need to signal when they are @ready to * handle requests (read/writes) from the NoC interconnect. * * Similarly, the @midle bit is used to idle the master. */ struct r9a06g032_gate { … }; enum gate_type { … }; /** * struct r9a06g032_clkdesc - describe a single clock * @name: string describing this clock * @managed: boolean indicating if this clock should be * started/stopped as part of power management * @type: see enum @gate_type * @index: the ID of this clock element * @source: the ID+1 of the parent clock element. * Root clock uses ID of ~0 (PARENT_ID); * @gate: clock enable/disable * @div: substructure for clock divider * @div.min: smallest permitted clock divider * @div.max: largest permitted clock divider * @div.reg: clock divider register offset, in 32-bit words * @div.table: optional list of fixed clock divider values; * must be in ascending order, zero for unused * @ffc: substructure for fixed-factor clocks * @ffc.div: divisor for fixed-factor clock * @ffc.mul: multiplier for fixed-factor clock * @dual: substructure for dual clock gates * @dual.group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7 * @dual.sel: select either g1/r1 or g2/r2 as clock source * @dual.g1: 1st source gate (clock enable/disable) * @dual.r1: 1st source reset (module reset) * @dual.g2: 2nd source gate (clock enable/disable) * @dual.r2: 2nd source reset (module reset) * * Describes a single element in the clock tree hierarchy. * As there are quite a large number of clock elements, this * structure is packed tightly to conserve space. */ struct r9a06g032_clkdesc { … }; /* * The last three arguments are not currently used, * but are kept in the r9a06g032_clocks table below. */ #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) … #define D_GATE(_idx, _n, _src, ...) … #define D_MODULE(_idx, _n, _src, ...) … #define D_ROOT(_idx, _n, _mul, _div) … #define D_FFC(_idx, _n, _src, _div) … #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) … #define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) … /* Internal clock IDs */ #define R9A06G032_CLKOUT … #define R9A06G032_CLKOUT_D10 … #define R9A06G032_CLKOUT_D16 … #define R9A06G032_CLKOUT_D160 … #define R9A06G032_CLKOUT_D1OR2 … #define R9A06G032_CLKOUT_D20 … #define R9A06G032_CLKOUT_D40 … #define R9A06G032_CLKOUT_D5 … #define R9A06G032_CLKOUT_D8 … #define R9A06G032_DIV_ADC … #define R9A06G032_DIV_I2C … #define R9A06G032_DIV_NAND … #define R9A06G032_DIV_P1_PG … #define R9A06G032_DIV_P2_PG … #define R9A06G032_DIV_P3_PG … #define R9A06G032_DIV_P4_PG … #define R9A06G032_DIV_P5_PG … #define R9A06G032_DIV_P6_PG … #define R9A06G032_DIV_QSPI0 … #define R9A06G032_DIV_QSPI1 … #define R9A06G032_DIV_REF_SYNC … #define R9A06G032_DIV_SDIO0 … #define R9A06G032_DIV_SDIO1 … #define R9A06G032_DIV_SWITCH … #define R9A06G032_DIV_UART … #define R9A06G032_DIV_MOTOR … #define R9A06G032_CLK_DDRPHY_PLLCLK_D4 … #define R9A06G032_CLK_ECAT100_D4 … #define R9A06G032_CLK_HSR100_D2 … #define R9A06G032_CLK_REF_SYNC_D4 … #define R9A06G032_CLK_REF_SYNC_D8 … #define R9A06G032_CLK_SERCOS100_D2 … #define R9A06G032_DIV_CA7 … #define R9A06G032_UART_GROUP_012 … #define R9A06G032_UART_GROUP_34567 … #define R9A06G032_CLOCK_COUNT … static const struct r9a06g032_clkdesc r9a06g032_clocks[] = …; struct r9a06g032_priv { … }; static struct r9a06g032_priv *sysctrl_priv; /* Exported helper to access the DMAMUX register */ int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) { … } EXPORT_SYMBOL_GPL(…); static void clk_rdesc_set(struct r9a06g032_priv *clocks, struct regbit rb, unsigned int on) { … } static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb) { … } /* * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's * clock gate framework as the gates on the R9A06G032 have a special enabling * sequence, therefore we use this little proxy. */ struct r9a06g032_clk_gate { … }; #define to_r9a06g032_gate(_hw) … static int create_add_module_clock(struct of_phandle_args *clkspec, struct device *dev) { … } static int r9a06g032_attach_dev(struct generic_pm_domain *pd, struct device *dev) { … } static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev) { … } static int r9a06g032_add_clk_domain(struct device *dev) { … } static void r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, struct r9a06g032_gate *g, int on) { … } static int r9a06g032_clk_gate_enable(struct clk_hw *hw) { … } static void r9a06g032_clk_gate_disable(struct clk_hw *hw) { … } static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops r9a06g032_clk_gate_ops = …; static struct clk * r9a06g032_register_gate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) { … } struct r9a06g032_clk_div { … }; #define to_r9a06g032_div(_hw) … static unsigned long r9a06g032_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } /* * Attempts to find a value that is in range of min,max, * and if a table of set dividers was specified for this * register, try to find the fixed divider that is the closest * to the target frequency */ static long r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk, unsigned long rate, unsigned long prate) { … } static int r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static int r9a06g032_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops r9a06g032_clk_div_ops = …; static struct clk * r9a06g032_register_div(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) { … } /* * This clock provider handles the case of the R9A06G032 where you have * peripherals that have two potential clock source and two gates, one for * each of the clock source - the used clock source (for all sub clocks) * is selected by a single bit. * That single bit affects all sub-clocks, and therefore needs to change the * active gate (and turn the others off) and force a recalculation of the rates. * * This implements two clock providers, one 'bitselect' that * handles the switch between both parents, and another 'dualgate' * that knows which gate to poke at, depending on the parent's bit position. */ struct r9a06g032_clk_bitsel { … }; #define to_clk_bitselect(_hw) … static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw) { … } static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index) { … } static const struct clk_ops clk_bitselect_ops = …; static struct clk * r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) { … } struct r9a06g032_clk_dualgate { … }; #define to_clk_dualgate(_hw) … static int r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable) { … } static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw) { … } static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw) { … } static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops r9a06g032_clk_dualgate_ops = …; static struct clk * r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc, struct regbit sel) { … } static void r9a06g032_clocks_del_clk_provider(void *data) { … } static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks) { … } static int __init r9a06g032_clocks_probe(struct platform_device *pdev) { … } static const struct of_device_id r9a06g032_match[] = …; static struct platform_driver r9a06g032_clock_driver = …; static int __init r9a06g032_clocks_init(void) { … } subsys_initcall(r9a06g032_clocks_init);
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