// SPDX-License-Identifier: GPL-2.0-only /* * Driver for Atmel I2S controller * * Copyright (C) 2015 Atmel Corporation * * Author: Cyrille Pitchen <[email protected]> */ #include <linux/init.h> #include <linux/module.h> #include <linux/device.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/clk.h> #include <linux/mfd/syscon.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/initval.h> #include <sound/soc.h> #include <sound/dmaengine_pcm.h> #define ATMEL_I2SC_MAX_TDM_CHANNELS … /* * ---- I2S Controller Register map ---- */ #define ATMEL_I2SC_CR … #define ATMEL_I2SC_MR … #define ATMEL_I2SC_SR … #define ATMEL_I2SC_SCR … #define ATMEL_I2SC_SSR … #define ATMEL_I2SC_IER … #define ATMEL_I2SC_IDR … #define ATMEL_I2SC_IMR … #define ATMEL_I2SC_RHR … #define ATMEL_I2SC_THR … #define ATMEL_I2SC_VERSION … /* * ---- Control Register (Write-only) ---- */ #define ATMEL_I2SC_CR_RXEN … #define ATMEL_I2SC_CR_RXDIS … #define ATMEL_I2SC_CR_CKEN … #define ATMEL_I2SC_CR_CKDIS … #define ATMEL_I2SC_CR_TXEN … #define ATMEL_I2SC_CR_TXDIS … #define ATMEL_I2SC_CR_SWRST … /* * ---- Mode Register (Read/Write) ---- */ #define ATMEL_I2SC_MR_MODE_MASK … #define ATMEL_I2SC_MR_MODE_SLAVE … #define ATMEL_I2SC_MR_MODE_MASTER … #define ATMEL_I2SC_MR_DATALENGTH_MASK … #define ATMEL_I2SC_MR_DATALENGTH_32_BITS … #define ATMEL_I2SC_MR_DATALENGTH_24_BITS … #define ATMEL_I2SC_MR_DATALENGTH_20_BITS … #define ATMEL_I2SC_MR_DATALENGTH_18_BITS … #define ATMEL_I2SC_MR_DATALENGTH_16_BITS … #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT … #define ATMEL_I2SC_MR_DATALENGTH_8_BITS … #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT … #define ATMEL_I2SC_MR_FORMAT_MASK … #define ATMEL_I2SC_MR_FORMAT_I2S … #define ATMEL_I2SC_MR_FORMAT_LJ … #define ATMEL_I2SC_MR_FORMAT_TDM … #define ATMEL_I2SC_MR_FORMAT_TDMLJ … /* Left audio samples duplicated to right audio channel */ #define ATMEL_I2SC_MR_RXMONO … /* Receiver uses one DMA channel ... */ #define ATMEL_I2SC_MR_RXDMA_MASK … #define ATMEL_I2SC_MR_RXDMA_SINGLE … #define ATMEL_I2SC_MR_RXDMA_MULTIPLE … /* I2SDO output of I2SC is internally connected to I2SDI input */ #define ATMEL_I2SC_MR_RXLOOP … /* Left audio samples duplicated to right audio channel */ #define ATMEL_I2SC_MR_TXMONO … /* Transmitter uses one DMA channel ... */ #define ATMEL_I2SC_MR_TXDMA_MASK … #define ATMEL_I2SC_MR_TXDMA_SINGLE … #define ATMEL_I2SC_MR_TXDME_MULTIPLE … /* x sample transmitted when underrun */ #define ATMEL_I2SC_MR_TXSAME_MASK … #define ATMEL_I2SC_MR_TXSAME_ZERO … #define ATMEL_I2SC_MR_TXSAME_PREVIOUS … /* Audio Clock to I2SC Master Clock ratio */ #define ATMEL_I2SC_MR_IMCKDIV_MASK … #define ATMEL_I2SC_MR_IMCKDIV(div) … /* Master Clock to fs ratio */ #define ATMEL_I2SC_MR_IMCKFS_MASK … #define ATMEL_I2SC_MR_IMCKFS(fs) … /* Master Clock mode */ #define ATMEL_I2SC_MR_IMCKMODE_MASK … /* 0: No master clock generated (selected clock drives I2SCK pin) */ #define ATMEL_I2SC_MR_IMCKMODE_I2SCK … /* 1: master clock generated (internally generated clock drives I2SMCK pin) */ #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK … /* Slot Width */ /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */ /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */ #define ATMEL_I2SC_MR_IWS … /* * ---- Status Registers ---- */ #define ATMEL_I2SC_SR_RXEN … #define ATMEL_I2SC_SR_RXRDY … #define ATMEL_I2SC_SR_RXOR … #define ATMEL_I2SC_SR_TXEN … #define ATMEL_I2SC_SR_TXRDY … #define ATMEL_I2SC_SR_TXUR … /* Receive Overrun Channel */ #define ATMEL_I2SC_SR_RXORCH_MASK … #define ATMEL_I2SC_SR_RXORCH(ch) … /* Transmit Underrun Channel */ #define ATMEL_I2SC_SR_TXURCH_MASK … #define ATMEL_I2SC_SR_TXURCH(ch) … /* * ---- Interrupt Enable/Disable/Mask Registers ---- */ #define ATMEL_I2SC_INT_RXRDY … #define ATMEL_I2SC_INT_RXOR … #define ATMEL_I2SC_INT_TXRDY … #define ATMEL_I2SC_INT_TXUR … static const struct regmap_config atmel_i2s_regmap_config = …; struct atmel_i2s_gck_param { … }; #define I2S_MCK_12M288 … #define I2S_MCK_11M2896 … #define I2S_MCK_6M144 … /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */ static const struct atmel_i2s_gck_param gck_params[] = …; struct atmel_i2s_dev; struct atmel_i2s_caps { … }; struct atmel_i2s_dev { … }; static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id) { … } #define ATMEL_I2S_RATES … #define ATMEL_I2S_FORMATS … static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) { … } static int atmel_i2s_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs) { … } static int atmel_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev, bool enabled) { … } static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { … } static int atmel_i2s_dai_probe(struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops atmel_i2s_dai_ops = …; static struct snd_soc_dai_driver atmel_i2s_dai = …; static const struct snd_soc_component_driver atmel_i2s_component = …; static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev, struct device_node *np) { … } static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = …; static const struct of_device_id atmel_i2s_dt_ids[] = …; MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids); static int atmel_i2s_probe(struct platform_device *pdev) { … } static void atmel_i2s_remove(struct platform_device *pdev) { … } static struct platform_driver atmel_i2s_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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