/* SPDX-License-Identifier: GPL-2.0 */ /* * RZ/G2L Clock Pulse Generator * * Copyright (C) 2021 Renesas Electronics Corp. * */ #ifndef __RENESAS_RZG2L_CPG_H__ #define __RENESAS_RZG2L_CPG_H__ #include <linux/notifier.h> #define CPG_SIPLL5_STBY … #define CPG_SIPLL5_CLK1 … #define CPG_SIPLL5_CLK3 … #define CPG_SIPLL5_CLK4 … #define CPG_SIPLL5_CLK5 … #define CPG_SIPLL5_MON … #define CPG_PL1_DDIV … #define CPG_PL2_DDIV … #define CPG_PL3A_DDIV … #define CPG_PL6_DDIV … #define CPG_CLKSTATUS … #define CPG_PL3_SSEL … #define CPG_PL6_SSEL … #define CPG_PL6_ETH_SSEL … #define CPG_PL5_SDIV … #define CPG_RST_MON … #define CPG_BUS_ACPU_MSTOP … #define CPG_BUS_MCPU1_MSTOP … #define CPG_BUS_MCPU2_MSTOP … #define CPG_BUS_PERI_COM_MSTOP … #define CPG_BUS_PERI_CPU_MSTOP … #define CPG_BUS_PERI_DDR_MSTOP … #define CPG_BUS_REG0_MSTOP … #define CPG_BUS_REG1_MSTOP … #define CPG_BUS_TZCDDR_MSTOP … #define CPG_MHU_MSTOP … #define CPG_BUS_MCPU3_MSTOP … #define CPG_BUS_PERI_CPU2_MSTOP … #define CPG_OTHERFUNC1_REG … #define CPG_SIPLL5_STBY_RESETB … #define CPG_SIPLL5_STBY_RESETB_WEN … #define CPG_SIPLL5_STBY_SSCG_EN_WEN … #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN … #define CPG_SIPLL5_CLK4_RESV_LSB … #define CPG_SIPLL5_MON_PLL5_LOCK … #define CPG_OTHERFUNC1_REG_RES0_ON_WEN … #define CPG_PL5_SDIV_DIV_DSI_A_WEN … #define CPG_PL5_SDIV_DIV_DSI_B_WEN … #define CPG_CLKSTATUS_SELSDHI0_STS … #define CPG_CLKSTATUS_SELSDHI1_STS … /* n = 0/1/2 for PLL1/4/6 */ #define CPG_SAMPLL_CLK1(n) … #define CPG_SAMPLL_CLK2(n) … #define PLL146_CONF(n) … #define DDIV_PACK(offset, bitpos, size) … #define DIVPL1A … #define DIVPL2A … #define DIVDSILPCLK … #define DIVPL3A … #define DIVPL3B … #define DIVPL3C … #define DIVGPU … #define SEL_PLL_PACK(offset, bitpos, size) … #define SEL_PLL3_3 … #define SEL_PLL5_4 … #define SEL_PLL6_2 … #define SEL_GPU2 … #define EXTAL_FREQ_IN_MEGA_HZ … /** * Definitions of CPG Core Clocks * * These include: * - Clock outputs exported to DT * - External input clocks * - Internal CPG clocks */ struct cpg_core_clk { … }; enum clk_types { … }; #define DEF_TYPE(_name, _id, _type...) … #define DEF_BASE(_name, _id, _type, _parent...) … #define DEF_SAMPLL(_name, _id, _parent, _conf) … #define DEF_G3S_PLL(_name, _id, _parent, _conf) … #define DEF_INPUT(_name, _id) … #define DEF_FIXED(_name, _id, _parent, _mult, _div) … #define DEF_DIV(_name, _id, _parent, _conf, _dtable) … #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) … #define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \ _max_rate, _clk_flags, _notif) … #define DEF_MUX(_name, _id, _conf, _parent_names) … #define DEF_MUX_RO(_name, _id, _conf, _parent_names) … #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) … #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) … #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) … #define DEF_DSI_DIV(_name, _id, _parent, _flag) … /** * struct rzg2l_mod_clk - Module Clocks definitions * * @name: handle between common and hardware-specific interfaces * @id: clock index in array containing all Core and Module Clocks * @parent: id of parent clock * @off: register offset * @bit: ON/MON bit * @is_coupled: flag to indicate coupled clock */ struct rzg2l_mod_clk { … }; #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) … #define DEF_MOD(_name, _id, _parent, _off, _bit) … #define DEF_COUPLED(_name, _id, _parent, _off, _bit) … /** * struct rzg2l_reset - Reset definitions * * @off: register offset * @bit: reset bit * @monbit: monitor bit in CPG_RST_MON register, -1 if none */ struct rzg2l_reset { … }; #define DEF_RST_MON(_id, _off, _bit, _monbit) … #define DEF_RST(_id, _off, _bit) … /** * struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure * @off: register offset * @mask: register mask */ struct rzg2l_cpg_reg_conf { … }; #define DEF_REG_CONF(_off, _mask) … /** * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure * @mstop: MSTOP register configuration */ struct rzg2l_cpg_pm_domain_conf { … }; /** * struct rzg2l_cpg_pm_domain_init_data - PM domain init data * @name: PM domain name * @conf: PM domain configuration * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*) * @id: PM domain ID (similar to the ones defined in * include/dt-bindings/clock/<soc-id>-cpg.h) */ struct rzg2l_cpg_pm_domain_init_data { … }; #define DEF_PD(_name, _id, _mstop_conf, _flags) … /* Power domain flags. */ #define RZG2L_PD_F_ALWAYS_ON … #define RZG2L_PD_F_NONE … /** * struct rzg2l_cpg_info - SoC-specific CPG Description * * @core_clks: Array of Core Clock definitions * @num_core_clks: Number of entries in core_clks[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @num_total_core_clks: Total number of Core Clocks (exported + internal) * * @mod_clks: Array of Module Clock definitions * @num_mod_clks: Number of entries in mod_clks[] * @num_hw_mod_clks: Number of Module Clocks supported by the hardware * * @resets: Array of Module Reset definitions * @num_resets: Number of entries in resets[] * * @crit_mod_clks: Array with Module Clock IDs of critical clocks that * should not be disabled without a knowledgeable driver * @num_crit_mod_clks: Number of entries in crit_mod_clks[] * @pm_domains: PM domains init data array * @num_pm_domains: Number of PM domains * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers */ struct rzg2l_cpg_info { … }; extern const struct rzg2l_cpg_info r9a07g043_cpg_info; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; extern const struct rzg2l_cpg_info r9a07g054_cpg_info; extern const struct rzg2l_cpg_info r9a08g045_cpg_info; extern const struct rzg2l_cpg_info r9a09g011_cpg_info; int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data); int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); #endif
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