linux/drivers/clk/renesas/r9a07g043-cpg.c

// SPDX-License-Identifier: GPL-2.0
/*
 * RZ/G2UL CPG driver
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>

#include <dt-bindings/clock/r9a07g043-cpg.h>

#include "rzg2l-cpg.h"

/* Specific registers. */
#define CPG_PL2SDHI_DSEL …

/* Clock select configuration. */
#define SEL_SDHI0 …
#define SEL_SDHI1 …

/* Clock status configuration. */
#define SEL_SDHI0_STS …
#define SEL_SDHI1_STS …

enum clk_ids { … };

/* Divider tables */
static const struct clk_div_table dtable_1_8[] = …;

static const struct clk_div_table dtable_1_32[] = …;

/* Mux clock tables */
static const char * const sel_pll3_3[] = …;
static const char * const sel_pll6_2[]	= …;
static const char * const sel_sdhi[] = …;

static const u32 mtable_sdhi[] = …;

static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = …;

static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = …;

static const struct rzg2l_reset r9a07g043_resets[] = …;

static const unsigned int r9a07g043_crit_mod_clks[] __initconst = …;

#ifdef CONFIG_ARM64
static const unsigned int r9a07g043_no_pm_mod_clks[] = {
	MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
	MOD_CLK_BASE + R9A07G043_CRU_VCLK,
};
#endif

const struct rzg2l_cpg_info r9a07g043_cpg_info = …;