/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ACP_HW_H #define __ACP_HW_H #include "include/acp_2_2_d.h" #include "include/acp_2_2_sh_mask.h" #define ACP_PAGE_SIZE_4K_ENABLE … #define ACP_PLAYBACK_PTE_OFFSET … #define ACP_CAPTURE_PTE_OFFSET … /* Playback and Capture Offset for Stoney */ #define ACP_ST_PLAYBACK_PTE_OFFSET … #define ACP_ST_CAPTURE_PTE_OFFSET … #define ACP_ST_BT_PLAYBACK_PTE_OFFSET … #define ACP_ST_BT_CAPTURE_PTE_OFFSET … #define ACP_GARLIC_CNTL_DEFAULT … #define ACP_ONION_CNTL_DEFAULT … #define ACP_PHYSICAL_BASE … /* * In case of I2S SP controller instance, Stoney uses SRAM bank 1 for * playback and SRAM Bank 2 for capture where as in case of BT I2S * Instance, Stoney uses SRAM Bank 3 for playback & SRAM Bank 4 will * be used for capture. Carrizo uses I2S SP controller instance. SRAM Banks * 1, 2, 3, 4 will be used for playback & SRAM Banks 5, 6, 7, 8 will be used * for capture scenario. */ #define ACP_SRAM_BANK_1_ADDRESS … #define ACP_SRAM_BANK_2_ADDRESS … #define ACP_SRAM_BANK_3_ADDRESS … #define ACP_SRAM_BANK_4_ADDRESS … #define ACP_SRAM_BANK_5_ADDRESS … #define ACP_DMA_RESET_TIME … #define ACP_CLOCK_EN_TIME_OUT_VALUE … #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE … #define ACP_DMA_COMPLETE_TIME_OUT_VALUE … #define ACP_SRAM_BASE_ADDRESS … #define ACP_DAGB_GRP_SRAM_BASE_ADDRESS … #define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET … #define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS … #define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS … #define TO_ACP_I2S_1 … #define TO_ACP_I2S_2 … #define TO_BLUETOOTH … #define FROM_ACP_I2S_1 … #define FROM_ACP_I2S_2 … #define FROM_BLUETOOTH … #define I2S_SP_INSTANCE … #define I2S_BT_INSTANCE … #define I2S_MICSP_INSTANCE … #define CAP_CHANNEL0 … #define CAP_CHANNEL1 … #define ACP_TILE_ON_MASK … #define ACP_TILE_OFF_MASK … #define ACP_TILE_ON_RETAIN_REG_MASK … #define ACP_TILE_OFF_RETAIN_REG_MASK … #define ACP_TILE_P1_MASK … #define ACP_TILE_P2_MASK … #define ACP_TILE_DSP0_MASK … #define ACP_TILE_DSP1_MASK … #define ACP_TILE_DSP2_MASK … /* Playback DMA channels */ #define SYSRAM_TO_ACP_CH_NUM … #define ACP_TO_I2S_DMA_CH_NUM … /* Capture DMA channels */ #define I2S_TO_ACP_DMA_CH_NUM … #define ACP_TO_SYSRAM_CH_NUM … /* Playback DMA Channels for I2S BT instance */ #define SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM … #define ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM … /* Capture DMA Channels for I2S BT Instance */ #define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM … #define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM … /* Playback DMA channels for I2S MICSP instance */ #define SYSRAM_TO_ACP_MICSP_INSTANCE_CH_NUM … #define ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM … #define NUM_DSCRS_PER_CHANNEL … #define PLAYBACK_START_DMA_DESCR_CH12 … #define PLAYBACK_END_DMA_DESCR_CH12 … #define PLAYBACK_START_DMA_DESCR_CH13 … #define PLAYBACK_END_DMA_DESCR_CH13 … #define CAPTURE_START_DMA_DESCR_CH14 … #define CAPTURE_END_DMA_DESCR_CH14 … #define CAPTURE_START_DMA_DESCR_CH15 … #define CAPTURE_END_DMA_DESCR_CH15 … /* I2S BT Instance DMA Descriptors */ #define PLAYBACK_START_DMA_DESCR_CH8 … #define PLAYBACK_END_DMA_DESCR_CH8 … #define PLAYBACK_START_DMA_DESCR_CH9 … #define PLAYBACK_END_DMA_DESCR_CH9 … #define CAPTURE_START_DMA_DESCR_CH10 … #define CAPTURE_END_DMA_DESCR_CH10 … #define CAPTURE_START_DMA_DESCR_CH11 … #define CAPTURE_END_DMA_DESCR_CH11 … /* I2S MICSP Instance DMA Descriptors */ #define PLAYBACK_START_DMA_DESCR_CH4 … #define PLAYBACK_END_DMA_DESCR_CH4 … #define PLAYBACK_START_DMA_DESCR_CH5 … #define PLAYBACK_END_DMA_DESCR_CH5 … #define mmACP_I2S_16BIT_RESOLUTION_EN … #define ACP_I2S_MIC_16BIT_RESOLUTION_EN … #define ACP_I2S_MICSP_16BIT_RESOLUTION_EN … #define ACP_I2S_SP_16BIT_RESOLUTION_EN … #define ACP_I2S_BT_16BIT_RESOLUTION_EN … #define ACP_BT_UART_PAD_SELECT_MASK … enum acp_dma_priority_level { … }; struct audio_substream_data { … }; struct audio_drv_data { … }; /* * this structure used for platform data transfer between machine driver * and dma driver */ struct acp_platform_info { … }; acp_dma_count; enum { … }; enum { … }; acp_dma_dscr_transfer_t; extern bool acp_bt_uart_enable; #endif /*__ACP_HW_H */
Codebase Browser
linux