// SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2014-2015 Broadcom Corporation #include <linux/debugfs.h> #include <linux/dma-mapping.h> #include <linux/init.h> #include <linux/io.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/timer.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/soc-dai.h> #include "cygnus-ssp.h" /* Register offset needed for ASoC PCM module */ #define INTH_R5F_STATUS_OFFSET … #define INTH_R5F_CLEAR_OFFSET … #define INTH_R5F_MASK_SET_OFFSET … #define INTH_R5F_MASK_CLEAR_OFFSET … #define BF_REARM_FREE_MARK_OFFSET … #define BF_REARM_FULL_MARK_OFFSET … /* Ring Buffer Ctrl Regs --- Start */ /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_RDADDR_REG_BASE */ #define SRC_RBUF_0_RDADDR_OFFSET … #define SRC_RBUF_1_RDADDR_OFFSET … #define SRC_RBUF_2_RDADDR_OFFSET … #define SRC_RBUF_3_RDADDR_OFFSET … #define SRC_RBUF_4_RDADDR_OFFSET … #define SRC_RBUF_5_RDADDR_OFFSET … #define SRC_RBUF_6_RDADDR_OFFSET … /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_WRADDR_REG_BASE */ #define SRC_RBUF_0_WRADDR_OFFSET … #define SRC_RBUF_1_WRADDR_OFFSET … #define SRC_RBUF_2_WRADDR_OFFSET … #define SRC_RBUF_3_WRADDR_OFFSET … #define SRC_RBUF_4_WRADDR_OFFSET … #define SRC_RBUF_5_WRADDR_OFFSET … #define SRC_RBUF_6_WRADDR_OFFSET … /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_BASEADDR_REG_BASE */ #define SRC_RBUF_0_BASEADDR_OFFSET … #define SRC_RBUF_1_BASEADDR_OFFSET … #define SRC_RBUF_2_BASEADDR_OFFSET … #define SRC_RBUF_3_BASEADDR_OFFSET … #define SRC_RBUF_4_BASEADDR_OFFSET … #define SRC_RBUF_5_BASEADDR_OFFSET … #define SRC_RBUF_6_BASEADDR_OFFSET … /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_ENDADDR_REG_BASE */ #define SRC_RBUF_0_ENDADDR_OFFSET … #define SRC_RBUF_1_ENDADDR_OFFSET … #define SRC_RBUF_2_ENDADDR_OFFSET … #define SRC_RBUF_3_ENDADDR_OFFSET … #define SRC_RBUF_4_ENDADDR_OFFSET … #define SRC_RBUF_5_ENDADDR_OFFSET … #define SRC_RBUF_6_ENDADDR_OFFSET … /* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_FREE_MARK_REG_BASE */ #define SRC_RBUF_0_FREE_MARK_OFFSET … #define SRC_RBUF_1_FREE_MARK_OFFSET … #define SRC_RBUF_2_FREE_MARK_OFFSET … #define SRC_RBUF_3_FREE_MARK_OFFSET … #define SRC_RBUF_4_FREE_MARK_OFFSET … #define SRC_RBUF_5_FREE_MARK_OFFSET … #define SRC_RBUF_6_FREE_MARK_OFFSET … /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_RDADDR_REG_BASE */ #define DST_RBUF_0_RDADDR_OFFSET … #define DST_RBUF_1_RDADDR_OFFSET … #define DST_RBUF_2_RDADDR_OFFSET … #define DST_RBUF_3_RDADDR_OFFSET … #define DST_RBUF_4_RDADDR_OFFSET … #define DST_RBUF_5_RDADDR_OFFSET … /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_WRADDR_REG_BASE */ #define DST_RBUF_0_WRADDR_OFFSET … #define DST_RBUF_1_WRADDR_OFFSET … #define DST_RBUF_2_WRADDR_OFFSET … #define DST_RBUF_3_WRADDR_OFFSET … #define DST_RBUF_4_WRADDR_OFFSET … #define DST_RBUF_5_WRADDR_OFFSET … /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_BASEADDR_REG_BASE */ #define DST_RBUF_0_BASEADDR_OFFSET … #define DST_RBUF_1_BASEADDR_OFFSET … #define DST_RBUF_2_BASEADDR_OFFSET … #define DST_RBUF_3_BASEADDR_OFFSET … #define DST_RBUF_4_BASEADDR_OFFSET … #define DST_RBUF_5_BASEADDR_OFFSET … /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_ENDADDR_REG_BASE */ #define DST_RBUF_0_ENDADDR_OFFSET … #define DST_RBUF_1_ENDADDR_OFFSET … #define DST_RBUF_2_ENDADDR_OFFSET … #define DST_RBUF_3_ENDADDR_OFFSET … #define DST_RBUF_4_ENDADDR_OFFSET … #define DST_RBUF_5_ENDADDR_OFFSET … /* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_FULL_MARK_REG_BASE */ #define DST_RBUF_0_FULL_MARK_OFFSET … #define DST_RBUF_1_FULL_MARK_OFFSET … #define DST_RBUF_2_FULL_MARK_OFFSET … #define DST_RBUF_3_FULL_MARK_OFFSET … #define DST_RBUF_4_FULL_MARK_OFFSET … #define DST_RBUF_5_FULL_MARK_OFFSET … /* Ring Buffer Ctrl Regs --- End */ /* Error Status Regs --- Start */ /* AUD_FMM_BF_ESR_ESRX_STATUS_REG_BASE */ #define ESR0_STATUS_OFFSET … #define ESR1_STATUS_OFFSET … #define ESR2_STATUS_OFFSET … #define ESR3_STATUS_OFFSET … #define ESR4_STATUS_OFFSET … /* AUD_FMM_BF_ESR_ESRX_STATUS_CLEAR_REG_BASE */ #define ESR0_STATUS_CLR_OFFSET … #define ESR1_STATUS_CLR_OFFSET … #define ESR2_STATUS_CLR_OFFSET … #define ESR3_STATUS_CLR_OFFSET … #define ESR4_STATUS_CLR_OFFSET … /* AUD_FMM_BF_ESR_ESRX_MASK_REG_BASE */ #define ESR0_MASK_STATUS_OFFSET … #define ESR1_MASK_STATUS_OFFSET … #define ESR2_MASK_STATUS_OFFSET … #define ESR3_MASK_STATUS_OFFSET … #define ESR4_MASK_STATUS_OFFSET … /* AUD_FMM_BF_ESR_ESRX_MASK_SET_REG_BASE */ #define ESR0_MASK_SET_OFFSET … #define ESR1_MASK_SET_OFFSET … #define ESR2_MASK_SET_OFFSET … #define ESR3_MASK_SET_OFFSET … #define ESR4_MASK_SET_OFFSET … /* AUD_FMM_BF_ESR_ESRX_MASK_CLEAR_REG_BASE */ #define ESR0_MASK_CLR_OFFSET … #define ESR1_MASK_CLR_OFFSET … #define ESR2_MASK_CLR_OFFSET … #define ESR3_MASK_CLR_OFFSET … #define ESR4_MASK_CLR_OFFSET … /* Error Status Regs --- End */ #define R5F_ESR0_SHIFT … #define R5F_ESR1_SHIFT … #define R5F_ESR2_SHIFT … #define R5F_ESR3_SHIFT … #define R5F_ESR4_SHIFT … /* Mask for R5F register. Set all relevant interrupt for playback handler */ #define ANY_PLAYBACK_IRQ … /* Mask for R5F register. Set all relevant interrupt for capture handler */ #define ANY_CAPTURE_IRQ … /* * PERIOD_BYTES_MIN is the number of bytes to at which the interrupt will tick. * This number should be a multiple of 256. Minimum value is 256 */ #define PERIOD_BYTES_MIN … static const struct snd_pcm_hardware cygnus_pcm_hw = …; static u64 cygnus_dma_dmamask = …; static struct cygnus_aio_port *cygnus_dai_get_dma_data( struct snd_pcm_substream *substream) { … } static void ringbuf_set_initial(void __iomem *audio_io, struct ringbuf_regs *p_rbuf, bool is_playback, u32 start, u32 periodsize, u32 bufsize) { … } static int configure_ringbuf_regs(struct snd_pcm_substream *substream) { … } static struct ringbuf_regs *get_ringbuf(struct snd_pcm_substream *substream) { … } static void enable_intr(struct snd_pcm_substream *substream) { … } static void disable_intr(struct snd_pcm_substream *substream) { … } static int cygnus_pcm_trigger(struct snd_soc_component *component, struct snd_pcm_substream *substream, int cmd) { … } static void cygnus_pcm_period_elapsed(struct snd_pcm_substream *substream) { … } /* * ESR0/1/3 status Description * 0x1 I2S0_out port caused interrupt * 0x2 I2S1_out port caused interrupt * 0x4 I2S2_out port caused interrupt * 0x8 SPDIF_out port caused interrupt */ static void handle_playback_irq(struct cygnus_audio *cygaud) { … } /* * ESR2/4 status Description * 0x1 I2S0_in port caused interrupt * 0x2 I2S1_in port caused interrupt * 0x4 I2S2_in port caused interrupt */ static void handle_capture_irq(struct cygnus_audio *cygaud) { … } static irqreturn_t cygnus_dma_irq(int irq, void *data) { … } static int cygnus_pcm_open(struct snd_soc_component *component, struct snd_pcm_substream *substream) { … } static int cygnus_pcm_close(struct snd_soc_component *component, struct snd_pcm_substream *substream) { … } static int cygnus_pcm_prepare(struct snd_soc_component *component, struct snd_pcm_substream *substream) { … } static snd_pcm_uframes_t cygnus_pcm_pointer(struct snd_soc_component *component, struct snd_pcm_substream *substream) { … } static int cygnus_dma_new(struct snd_soc_component *component, struct snd_soc_pcm_runtime *rtd) { … } static struct snd_soc_component_driver cygnus_soc_platform = …; int cygnus_soc_platform_register(struct device *dev, struct cygnus_audio *cygaud) { … } int cygnus_soc_platform_unregister(struct device *dev) { … } MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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