linux/drivers/clk/renesas/rcar-gen4-cpg.c

// SPDX-License-Identifier: GPL-2.0
/*
 * R-Car Gen4 Clock Pulse Generator
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 *
 * Based on rcar-gen3-cpg.c
 *
 * Copyright (C) 2015-2018 Glider bvba
 * Copyright (C) 2019 Renesas Electronics Corp.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/slab.h>

#include "renesas-cpg-mssr.h"
#include "rcar-gen4-cpg.h"
#include "rcar-cpg-lib.h"

static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata;
static unsigned int cpg_clk_extalr __initdata;
static u32 cpg_mode __initdata;

#define CPG_PLLECR …

#define CPG_PLLECR_PLLST(n) …

#define CPG_PLL1CR0 …
#define CPG_PLL1CR1 …
#define CPG_PLL2CR0 …
#define CPG_PLL2CR1 …
#define CPG_PLL3CR0 …
#define CPG_PLL3CR1 …
#define CPG_PLL4CR0 …
#define CPG_PLL4CR1 …
#define CPG_PLL6CR0 …
#define CPG_PLL6CR1 …

#define CPG_PLLxCR0_KICK …
#define CPG_PLLxCR0_NI …
#define CPG_PLLxCR0_SSMODE …
#define CPG_PLLxCR0_SSMODE_FM …
#define CPG_PLLxCR0_SSMODE_DITH …
#define CPG_PLLxCR0_SSMODE_CENT …
#define CPG_PLLxCR0_SSFREQ …
#define CPG_PLLxCR0_SSDEPT …

#define SSMODE_FM …
#define SSMODE_DITHER …
#define SSMODE_CENTER …

/* PLL Clocks */
struct cpg_pll_clk { … };

#define to_pll_clk(_hw) …

static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
					     unsigned long parent_rate)
{ … }

static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{ … }

static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{ … }

static const struct clk_ops cpg_pll_clk_ops = …;

static struct clk * __init cpg_pll_clk_register(const char *name,
						const char *parent_name,
						void __iomem *base,
						unsigned int cr0_offset,
						unsigned int cr1_offset,
						unsigned int index)

{ … }
/*
 * Z0 Clock & Z1 Clock
 */
#define CPG_FRQCRB …
#define CPG_FRQCRB_KICK …
#define CPG_FRQCRC0 …
#define CPG_FRQCRC1 …

struct cpg_z_clk { … };

#define to_z_clk(_hw) …

static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{ … }

static int cpg_z_clk_determine_rate(struct clk_hw *hw,
				    struct clk_rate_request *req)
{ … }

static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long parent_rate)
{ … }

static const struct clk_ops cpg_z_clk_ops = …;

static struct clk * __init cpg_z_clk_register(const char *name,
					      const char *parent_name,
					      void __iomem *reg,
					      unsigned int div,
					      unsigned int offset)
{ … }

/*
 * RPC Clocks
 */
static const struct clk_div_table cpg_rpcsrc_div_table[] = …;

struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
	struct clk **clks, void __iomem *base,
	struct raw_notifier_head *notifiers)
{ … }

int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
			      unsigned int clk_extalr, u32 mode)
{ … }